mem: Fix DRAM bank occupancy for streaming access
Review Request #2045 - Created Oct. 16, 2013 and submitted
| Information | |
|---|---|
| Andreas Hansson | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 9916:e254040a4aa0 --------------------------- mem: Fix DRAM bank occupancy for streaming access This patch fixes an issue that allowed more than 100% bus utilisation in certain cases.
All regressions pass (with stats update)
Posted (Oct. 24, 2013, 7:07 p.m.)
I was wondering if you consider tCCD for streaming accesses?
Posted (Oct. 24, 2013, 7:40 p.m.)
One suggestion: if streaming requests to the same row and same bank arrive with an interval bigger than tBURST, they are delayed by tCL. But in fact, they should be delayed by max(tCCD, tBURST) which is lower than tCL. I would guess this situation does not happen much with processors. However, LOW frequency IO devices which are directly connected to DRAM suffer from this. Please let me give you an example with DDR3: If requests to the same rank, same row, and same bank arrive with a period of 10ns (the time internval between two consecutive requests is 10ns), data for each request should be transfered with a delay of max(tCCD, tBURST)=5.0ns. However, in the current code, that delay is equal to tCL which 13.75ns. Please let me know if I am missing something because I am no expert.