Interleave/deinterleave operations relate to re-organizing the way data is structured when loaded to/from memory.

Say we had the following data sequentially in memory.

A[0].x
A[0].y
A[0].z
A[1].x
A[1].y
A[1].z
A[2].x
A[2].y
A[2].z
A[3].x
A[3].y
A[3].z


Lets say we want to load all of the 'z' coordinates into a SIMD register.  Such that D0 = {A[0].z, A[1].z, A[2].z, A[3].z}.  This process is called de-interleaving.  Currently we crack into micro-ops to perform each of the loads and then perform an expensive "de-interleave" micro-op.  

Since we were charging de-interleave micro-ops with 4 or 5 cycles of latency (can't remember which), they were skewing performance with respect to real hardware.  Real hardware seemingly has different micro-op decomposition and lower costs for such operations.

So, this patch is just a way to make minimal changes to bring performance back in line.  The goal was to make them have almost no performance impact.  Since O3 treats No_OpClass as "never resource constrained, single cycle latency" this was an easy way to get the desired behavior.  Additionally the new "minor" cpu also immediately executes No_OpClass instructions, so it was safe to do on the timing-focused cores.