mem: write streaming support via WriteInvalidate promotion

Information
Submitter:	Andreas Hansson
Repository:	gem5
Branch:	default
Bugs:
Depends On:
Reviewers
Groups:	Default
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Description

Changeset 10323:33baf6c26f18
---------------------------
mem: write streaming support via WriteInvalidate promotion

Support full-block writes directly rather than requiring RMW:
 * a cache line is allocated in the cache upon receipt of a
   WriteInvalidateReq, not the WriteInvalidateResp.
 * only top-level caches allocate the line; the others just pass
   the request along and invalidate as necessary.
 * to close a timing window between the *Req and the *Resp, a new
   metadata bit tracks whether another cache has read a copy of
   the new line before the writeback to memory.

Testing Done

Issue Summary

Description	From	Last Updated	Status
I would not want to call this request WriteInvalidate if it is not writing to the block. Why not just ...	Nilay Vaish	Aug. 20, 2014, 9:48 a.m.	Open
I do not like this check. You have marked that WriteInvalidateReq requires a response in packet.cc. And here you are ...	Nilay Vaish	Aug. 20, 2014, 9:48 a.m.	Open

Description:

~		Changeset 10308:159211e220a9
	~	Changeset 10308:a65bdd78f592

		mem: write streaming support via WriteInvalidate promotion

		Support full-block writes directly rather than requiring RMW:
		* a cache line is allocated in the cache upon receipt of a
		WriteInvalidateReq, not the WriteInvalidateResp.
		* only top-level caches allocate the line; the others just pass
		the request along and invalidate as necessary.
		* to close a timing window between the Req and the Resp, a new
		metadata bit tracks whether another cache has read a copy of
		the new line before the writeback to memory.

Diff:

Revision 2 (+162 -74)

Show changes

	src/mem/packet.hh
	src/mem/packet.cc
	src/mem/cache/blk.hh
	src/mem/cache/cache.hh
	src/mem/cache/cache_impl.hh

Description:

~		Changeset 10308:a65bdd78f592
	~	Changeset 10308:6bde9d243535

		mem: write streaming support via WriteInvalidate promotion

		Support full-block writes directly rather than requiring RMW:
		* a cache line is allocated in the cache upon receipt of a
		WriteInvalidateReq, not the WriteInvalidateResp.
		* only top-level caches allocate the line; the others just pass
		the request along and invalidate as necessary.
		* to close a timing window between the Req and the Resp, a new
		metadata bit tracks whether another cache has read a copy of
		the new line before the writeback to memory.

Diff:

Revision 3 (+179 -76)

Show changes

	src/mem/packet.hh
	src/mem/packet.cc
	src/mem/cache/blk.hh
	src/mem/cache/cache.hh
	src/mem/cache/cache_impl.hh

I think we need better explanation in the opening comment.  While I sort
of understand what the purpose, I feel lost in the mass of code in cache_impl.hh.

src/mem/cache/cache_impl.hh (Diff revision 3)

I would not want to call this request WriteInvalidate if it is not writing to the block.  Why not just call it invalidate?

Show all issues

src/mem/cache/cache_impl.hh (Diff revision 3)

I do not like this check.  You have marked that WriteInvalidateReq requires a response in packet.cc.  And here you are testing that pkt->cmd is not WriteInvalidateReq.

Show all issues

Description:

~		Changeset 10308:6bde9d243535
	~	Changeset 10312:451feb97bc0e

		mem: write streaming support via WriteInvalidate promotion

		Support full-block writes directly rather than requiring RMW:
		* a cache line is allocated in the cache upon receipt of a
		WriteInvalidateReq, not the WriteInvalidateResp.
		* only top-level caches allocate the line; the others just pass
		the request along and invalidate as necessary.
		* to close a timing window between the Req and the Resp, a new
		metadata bit tracks whether another cache has read a copy of
		the new line before the writeback to memory.

Diff:

Revision 4 (+206 -87)

Show changes

	src/mem/packet.hh
	src/mem/packet.cc
	src/mem/cache/base.hh
	src/mem/cache/base.cc
	src/mem/cache/blk.hh
	src/mem/cache/cache.hh
	src/mem/cache/cache_impl.hh

Description:

~		Changeset 10312:451feb97bc0e
	~	Changeset 10323:33baf6c26f18

		mem: write streaming support via WriteInvalidate promotion

		Support full-block writes directly rather than requiring RMW:
		* a cache line is allocated in the cache upon receipt of a
		WriteInvalidateReq, not the WriteInvalidateResp.
		* only top-level caches allocate the line; the others just pass
		the request along and invalidate as necessary.
		* to close a timing window between the Req and the Resp, a new
		metadata bit tracks whether another cache has read a copy of
		the new line before the writeback to memory.

Diff:

Revision 5 (+190 -79)

Show changes

	src/mem/packet.hh
	src/mem/packet.cc
	src/mem/cache/base.hh
	src/mem/cache/base.cc
	src/mem/cache/blk.hh
	src/mem/cache/cache.hh
	src/mem/cache/cache_impl.hh

very much look forward to this.
doFastWrites is always set to true. Does it make sense to add doFastWrites to the list of parameters in BaseCache.py?

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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Files

Issue Summary

Description:

Changeset 10308:159211e220a9

Changeset 10308:a65bdd78f592

Diff:

Description:

Changeset 10308:a65bdd78f592

Changeset 10308:6bde9d243535

Diff:

Description:

Changeset 10308:6bde9d243535

Changeset 10312:451feb97bc0e

Diff:

Description:

Changeset 10312:451feb97bc0e

Changeset 10323:33baf6c26f18

Diff:

Status: Closed (submitted)