mem: Page Table map api modification
Review Request #2462 - Created Oct. 6, 2014 and submitted
| Information | |
|---|---|
| Alexandru Dutu | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 10553:d4148bafebad --------------------------- mem: Page Table map api modification This patch adds uncacheable/cacheable and read-only/read-write attributes to the map method of PageTableBase. It also modifies the constructor of TlbEntry structs for all architectures to consider the new attributes.
Quick regressions testing done.
Posted (Nov. 18, 2014, 8:30 a.m.)
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src/arch/x86/pagetable.hh (Diff revision 1) -
i guess these should be const
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src/mem/page_table.hh (Diff revision 1) -
I'd suggest to specify the storage type (uint32_t)
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src/sim/process.hh (Diff revision 1) -
please update the doxygen comments
Some minor things. Looks ok for the rest.
Posted (Nov. 18, 2014, 12:05 p.m.)
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src/arch/arm/pagetable.hh (Diff revision 1) -
setting AP=3 makes the page table user-read-only.
one minor comment
Posted (Nov. 18, 2014, 2:49 p.m.)
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src/arch/alpha/pagetable.hh (Diff revision 1) -
or
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src/arch/mips/pagetable.hh (Diff revision 1) -
or
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src/arch/power/tlb.hh (Diff revision 1) -
or
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src/arch/x86/pagetable.hh (Diff revision 1) -
No need for parenthesis.
Review request changed
Updated (Nov. 19, 2014, 10:27 p.m.)
Change Summary:
Addressed raised issues.
Description: |
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Diff: |
Revision 2 (+121 -47) |