misc: Coupling gem5 with SystemC TLM2.0

Information
Submitter:	Matthias Jung
Repository:	gem5
Branch:	default
Bugs:
Depends On:
Reviewers
Groups:	Default
People:

Description

Changeset 10873:c0ac6410d7bc
---------------------------
misc: Coupling gem5 with SystemC TLM2.0
Transaction Level Modeling (TLM2.0) is widely used in industry for creating
virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
implementation of an external gem5 port, that enables the usage of gem5 as a
TLM initiator component in SystemC based virtual platforms. Both TLM coding
paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
supported.

Compared to the original patch a TLM memory manager was added. Furthermore,
the transaction object was removed and for each TLM payload a PacketPointer
that points to the original gem5 packet is added as an TLM extension.
For event handling single events are now created.

Testing Done

Issue Summary

Description	From	Last Updated	Status
I am not able to figure in which step this executable was created.	Nilay Vaish	June 18, 2015, 9:34 p.m.	Resolved
No commented code.	Nilay Vaish	June 18, 2015, 9:36 p.m.	Resolved
No commented code.	Nilay Vaish	June 18, 2015, 9:36 p.m.	Resolved
Inconsistent formatting.	Nilay Vaish	June 18, 2015, 9:44 p.m.	Resolved
There should not be any space between ( and params.	Nilay Vaish	June 18, 2015, 9:45 p.m.	Resolved
Remove this line.	Nilay Vaish	June 18, 2015, 9:46 p.m.	Resolved
if (false)?	Nilay Vaish	June 18, 2015, 9:48 p.m.	Resolved
if (false)?	Nilay Vaish	June 18, 2015, 9:48 p.m.	Resolved
There should not be any space before trans.	Nilay Vaish	June 18, 2015, 9:51 p.m.	Resolved
Inconsistent formatting of \{\}	Nilay Vaish	June 18, 2015, 9:53 p.m.	Resolved
Seems all arguments can fit in the same line.	Nilay Vaish	June 19, 2015, 2:43 p.m.	Resolved
Copyright notice missing.	Nilay Vaish	June 19, 2015, 2:45 p.m.	Resolved
Seems more than 80 characters.	Nilay Vaish	June 19, 2015, 2:47 p.m.	Resolved
notify is always true here. So why this check?	Nilay Vaish	July 14, 2015, 2:37 a.m.	Resolved

Summary:

-	misc: Coupling gem5 with SystemC TLM2.0
+	sim, arm: add checkpoint upgrader for d02b45a5

Description:

~		Transaction Level Modeling (TLM2.0) is widely used in industry for creating
~		virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
~		implementation of an external gem5 port, that enables the usage of gem5 as a
~		TLM initiator component in SystemC based virtual platforms. Both TLM coding
~		paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
~		supported.
	~	Changeset 10861:9141d87c7f71
	~	---------------------------
	~	sim, arm: add checkpoint upgrader for d02b45a5
	~
	~	The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
	~	obsoletes old checkpoints.

Branch:

+	default

Diff:

Revision 2 (+14 -1)

Show changes

	src/sim/serialize.hh
	util/cpt_upgrader.py

Summary:

-	sim, arm: add checkpoint upgrader for d02b45a5
+	misc: Coupling gem5 with SystemC TLM2.0

Description:

~		Changeset 10861:9141d87c7f71
	~	Changeset 10862:99159dd794b8
		---------------------------
~		sim, arm: add checkpoint upgrader for d02b45a5
~
~		The insertion of CONTEXTIDR_EL2 in the ARM miscellaneous registers
~		obsoletes old checkpoints.
	~	misc: Coupling gem5 with SystemC TLM2.0
	~	Transaction Level Modeling (TLM2.0) is widely used in industry for creating
	~	virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
	~	implementation of an external gem5 port, that enables the usage of gem5 as a
	+	TLM initiator component in SystemC based virtual platforms. Both TLM coding
	+	paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
	+	supported.

Diff:

Revision 3 (+1780)

Show changes

	configs/common/MemConfig.py
	configs/common/Options.py
	util/tlm/Makefile
	util/tlm/README
	util/tlm/main.cc
	util/tlm/sc_port.hh
	util/tlm/sc_port.cc
	util/tlm/sc_target.hh
	3 more

Description:

~		Changeset 10862:99159dd794b8
	~	Changeset 10873:745081501481
		---------------------------
		misc: Coupling gem5 with SystemC TLM2.0
		Transaction Level Modeling (TLM2.0) is widely used in industry for creating
		virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
		implementation of an external gem5 port, that enables the usage of gem5 as a
		TLM initiator component in SystemC based virtual platforms. Both TLM coding
		paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
		supported.

Diff:

Revision 4 (+1931)

Show changes

	configs/common/MemConfig.py
	configs/common/Options.py
	util/tlm/Makefile
	util/tlm/README
	util/tlm/main.cc
	util/tlm/run_gem5.sh
	util/tlm/sc_mm.hh
	util/tlm/sc_mm.cc
	6 more

Description:

		Changeset 10873:745081501481
		---------------------------
		misc: Coupling gem5 with SystemC TLM2.0
		Transaction Level Modeling (TLM2.0) is widely used in industry for creating
		virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
		implementation of an external gem5 port, that enables the usage of gem5 as a
		TLM initiator component in SystemC based virtual platforms. Both TLM coding
		paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
		supported.
	+
	+	A TLM memory manager was added in the latest patch.
	+	Next step is to get rid of the transaction object and attach the gem5 packet
	+	to the generic payload as an extension.

Most of the comments made below are on formatting.  As you fix these, I'll try to understand
the code and if required, provide you comments about the actual implementation itself.

util/tlm/README (Diff revision 4)

I am not able to figure in which step this executable was created.

Show all issues

util/tlm/main.cc (Diff revision 4)

No commented code.

Show all issues

util/tlm/run_gem5.sh (Diff revision 4)

No commented code.

Show all issues

util/tlm/sc_port.cc (Diff revision 4)

Inconsistent formatting.

Show all issues

util/tlm/sc_port.cc (Diff revision 4)

There should not be any space between ( and params.

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

Remove this line.

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

if (false)?

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

if (false)?

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

There should not be any space before trans.

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

Inconsistent formatting of {}

Show all issues

util/tlm/sc_target.cc (Diff revision 4)

Seems all arguments can fit in the same line.

Show all issues

util/tlm/tgen.cfg (Diff revision 4)

Show all issues

util/tlm/tlm.py (Diff revision 4)

Seems more than 80 characters.

Show all issues

Description:

~		Changeset 10873:745081501481
	~	Changeset 10873:2fdd00daa012
		---------------------------
		misc: Coupling gem5 with SystemC TLM2.0
		Transaction Level Modeling (TLM2.0) is widely used in industry for creating
		virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
		implementation of an external gem5 port, that enables the usage of gem5 as a
		TLM initiator component in SystemC based virtual platforms. Both TLM coding
		paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
		supported.

~		A TLM memory manager was added in the latest patch.
~		Next step is to get rid of the transaction object and attach the gem5 packet
~		to the generic payload as an extension.
	~	Compared to the original patch a TLM memory manager was added. Furthermore,
	~	the transaction object was removed and for each TLM payload a PacketPointer
	~	that points to the original gem5 packet is added as an TLM extension.

Diff:

Revision 5 (+1847)

Show changes

	configs/common/MemConfig.py
	configs/common/Options.py
	util/tlm/Makefile
	util/tlm/README
	util/tlm/main.cc
	util/tlm/run_gem5.sh
	util/tlm/sc_ext.hh
	util/tlm/sc_ext.cc
	8 more

I think I sort of understand what is going on in the patch.  It is

fine by me if we commit this patch, more so since the changes only

affect a couple of files in configs/common.
Just for my understanding, suppose I want to model a new component that 

communicates through some sort of transaction.  And I want that this component

be written in SystemC and the rest of the system simulation infrastructure

be provided by gem5.  Would I have to change the sc_target class to implement 

the functionality of this new component?

Matthias Jung June 22, 2015, 3:01 p.m. (June 22, 2015, 3:01 p.m.)

Exactly the sc_target is basically a simple memory stub, which can be exchanged by any TLM 2.0 compliant model.

util/tlm/sc_port.hh (Diff revision 5)

notify is always true here. So why this check?

Show all issues

Ship It!

Description:

~		Changeset 10873:2fdd00daa012
	~	Changeset 10873:c0ac6410d7bc
		---------------------------
		misc: Coupling gem5 with SystemC TLM2.0
		Transaction Level Modeling (TLM2.0) is widely used in industry for creating
		virtual platforms (IEEE 1666 SystemC). This patch contains a standard compliant
		implementation of an external gem5 port, that enables the usage of gem5 as a
		TLM initiator component in SystemC based virtual platforms. Both TLM coding
		paradigms loosely timed (b_transport) and aproximately timed (nb_transport) are
		supported.

		Compared to the original patch a TLM memory manager was added. Furthermore,
		the transaction object was removed and for each TLM payload a PacketPointer
~		that points to the original gem5 packet is added as an TLM extension.
	~	that points to the original gem5 packet is added as an TLM extension.
	+	For event handling single events are now created.

Diff:

Revision 6 (+1861)

Show changes

	configs/common/MemConfig.py
	configs/common/Options.py
	util/tlm/Makefile
	util/tlm/README
	util/tlm/main.cc
	util/tlm/run_gem5.sh
	util/tlm/sc_ext.hh
	util/tlm/sc_ext.cc
	8 more

Ship It!

You have a pending review.

Review Board 2.0.15

This change has been marked as submitted.

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Status: Closed (submitted)