diff -r 5c76426fd9ee -r 88dc51ebc6fa src/base/types.hh --- a/src/base/types.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/base/types.hh Tue Jul 07 15:32:34 2015 +0100 @@ -173,6 +173,10 @@ typedef int16_t ThreadID; const ThreadID InvalidThreadID = (ThreadID)-1; +/** Globally unique thread context ID */ +typedef int ContextID; +const ContextID InvalidContextID = (ContextID)-1; + /** * Port index/ID type, and a symbolic name for an invalid port id. */ diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/base_dyn_inst.hh --- a/src/cpu/base_dyn_inst.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/base_dyn_inst.hh Tue Jul 07 15:32:34 2015 +0100 @@ -460,7 +460,7 @@ MasterID masterId() const { return cpu->dataMasterId(); } /** Read this context's system-wide ID **/ - int contextId() const { return thread->contextId(); } + ContextID contextId() const { return thread->contextId(); } /** Returns the fault type. */ Fault getFault() const { return fault; } diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/checker/thread_context.hh --- a/src/cpu/checker/thread_context.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/checker/thread_context.hh Tue Jul 07 15:32:34 2015 +0100 @@ -96,9 +96,9 @@ int cpuId() const { return actualTC->cpuId(); } - int contextId() const { return actualTC->contextId(); } + ContextID contextId() const { return actualTC->contextId(); } - void setContextId(int id) + void setContextId(ContextID id) { actualTC->setContextId(id); checkerTC->setContextId(id); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/minor/exec_context.hh --- a/src/cpu/minor/exec_context.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/minor/exec_context.hh Tue Jul 07 15:32:34 2015 +0100 @@ -254,7 +254,7 @@ unsigned int readStCondFailures() const { return 0; } void setStCondFailures(unsigned int st_cond_failures) {} - int contextId() { return thread.contextId(); } + ContextID contextId() { return thread.contextId(); } /* ISA-specific (or at least currently ISA singleton) functions */ /* X86: TLB twiddling */ diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/o3/thread_context.hh --- a/src/cpu/o3/thread_context.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/o3/thread_context.hh Tue Jul 07 15:32:34 2015 +0100 @@ -101,7 +101,7 @@ /** Reads this CPU's Socket ID. */ virtual uint32_t socketId() const { return cpu->socketId(); } - virtual int contextId() const { return thread->contextId(); } + virtual ContextID contextId() const { return thread->contextId(); } virtual void setContextId(int id) { thread->setContextId(id); } diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/thread_context.cc --- a/src/cpu/thread_context.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/thread_context.cc Tue Jul 07 15:32:34 2015 +0100 @@ -95,9 +95,9 @@ if (id1 != id2) panic("CPU ids don't match, one: %d, two: %d", id1, id2); - id1 = one->contextId(); - id2 = two->contextId(); - if (id1 != id2) + const ContextID cid1 = one->contextId(); + const ContextID cid2 = two->contextId(); + if (cid1 != cid2) panic("Context ids don't match, one: %d, two: %d", id1, id2); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/cpu/thread_state.hh --- a/src/cpu/thread_state.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/cpu/thread_state.hh Tue Jul 07 15:32:34 2015 +0100 @@ -71,9 +71,9 @@ uint32_t socketId() const { return baseCpu->socketId(); } - int contextId() const { return _contextId; } + ContextID contextId() const { return _contextId; } - void setContextId(int id) { _contextId = id; } + void setContextId(ContextID id) { _contextId = id; } void setThreadId(ThreadID id) { _threadId = id; } @@ -153,7 +153,7 @@ BaseCPU *baseCpu; // system wide HW context id - int _contextId; + ContextID _contextId; // Index of hardware thread context on the CPU that this represents. ThreadID _threadId; diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/arm/gic_pl390.hh --- a/src/dev/arm/gic_pl390.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/arm/gic_pl390.hh Tue Jul 07 15:32:34 2015 +0100 @@ -210,7 +210,7 @@ /** software generated interrupt * @param data data to decode that indicates which cpus to interrupt */ - void softInt(int ctx_id, SWI swi); + void softInt(ContextID ctx_id, SWI swi); /** See if some processor interrupt flags need to be enabled/disabled * @param hint which set of interrupts needs to be checked diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/arm/gic_pl390.cc --- a/src/dev/arm/gic_pl390.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/arm/gic_pl390.cc Tue Jul 07 15:32:34 2015 +0100 @@ -135,7 +135,7 @@ { Addr daddr = pkt->getAddr() - distAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(GIC, "gic distributor read register %#x\n", daddr); @@ -269,7 +269,7 @@ Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < sys->numRunningContexts()); DPRINTF(GIC, "gic cpu read register %#x cpu context: %d\n", daddr, @@ -356,7 +356,7 @@ Addr daddr = pkt->getAddr() - distAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); uint32_t pkt_data M5_VAR_USED; switch (pkt->getSize()) @@ -496,7 +496,7 @@ Addr daddr = pkt->getAddr() - cpuAddr; assert(pkt->req->hasContextId()); - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); IAR iar; DPRINTF(GIC, "gic cpu write register cpu:%d %#x val: %#x\n", @@ -546,7 +546,7 @@ } void -Pl390::softInt(int ctx_id, SWI swi) +Pl390::softInt(ContextID ctx_id, SWI swi) { switch (swi.list_type) { case 1: diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/arm/timer_cpulocal.cc --- a/src/dev/arm/timer_cpulocal.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/arm/timer_cpulocal.cc Tue Jul 07 15:32:34 2015 +0100 @@ -75,7 +75,7 @@ assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Reading from CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); @@ -153,7 +153,7 @@ assert(pkt->getAddr() >= pioAddr && pkt->getAddr() < pioAddr + pioSize); assert(pkt->getSize() == 4); Addr daddr = pkt->getAddr() - pioAddr; - int cpu_id = pkt->req->contextId(); + ContextID cpu_id = pkt->req->contextId(); DPRINTF(Timer, "Writing to CpuLocalTimer at offset: %#x\n", daddr); assert(cpu_id >= 0); assert(cpu_id < CPU_MAX); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/arm/vgic.hh --- a/src/dev/arm/vgic.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/arm/vgic.hh Tue Jul 07 15:32:34 2015 +0100 @@ -222,7 +222,7 @@ Tick writeVCpu(PacketPtr pkt); Tick writeCtrl(PacketPtr pkt); - void updateIntState(int ctx_id); + void updateIntState(ContextID ctx_id); uint32_t getMISR(struct vcpuIntData *vid); void postVInt(uint32_t cpu, Tick when); void unPostVInt(uint32_t cpu); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/arm/vgic.cc --- a/src/dev/arm/vgic.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/arm/vgic.cc Tue Jul 07 15:32:34 2015 +0100 @@ -90,7 +90,7 @@ { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -134,7 +134,7 @@ { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl read register %#x\n", daddr); @@ -228,7 +228,7 @@ { Addr daddr = pkt->getAddr() - vcpuAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); assert(ctx_id < VGIC_CPU_MAX); struct vcpuIntData *vid = &vcpuData[ctx_id]; @@ -275,7 +275,7 @@ { Addr daddr = pkt->getAddr() - hvAddr; - int ctx_id = pkt->req->contextId(); + ContextID ctx_id = pkt->req->contextId(); DPRINTF(VGIC, "VGIC HVCtrl write register %#x <= %#x\n", daddr, pkt->get()); @@ -380,7 +380,7 @@ * This may raise a maintenance interrupt. */ void -VGic::updateIntState(int ctx_id) +VGic::updateIntState(ContextID ctx_id) { // @todo This should update APRs! diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/sinic.hh --- a/src/dev/sinic.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/sinic.hh Tue Jul 07 15:32:34 2015 +0100 @@ -273,10 +273,10 @@ virtual Tick write(PacketPtr pkt); virtual void drainResume() M5_ATTR_OVERRIDE; - void prepareIO(int cpu, int index); - void prepareRead(int cpu, int index); - void prepareWrite(int cpu, int index); - // Fault iprRead(Addr daddr, int cpu, uint64_t &result); + void prepareIO(ContextID cpu, int index); + void prepareRead(ContextID cpu, int index); + void prepareWrite(ContextID cpu, int index); + // Fault iprRead(Addr daddr, ContextID cpu, uint64_t &result); /** * Statistics diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/sinic.cc --- a/src/dev/sinic.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/sinic.cc Tue Jul 07 15:32:34 2015 +0100 @@ -152,7 +152,7 @@ void -Device::prepareIO(int cpu, int index) +Device::prepareIO(ContextID cpu, int index) { int size = virtualRegs.size(); if (index > size) @@ -165,7 +165,7 @@ //add stats for average number of vnics busy void -Device::prepareRead(int cpu, int index) +Device::prepareRead(ContextID cpu, int index) { using namespace Regs; prepareIO(cpu, index); @@ -206,7 +206,7 @@ } void -Device::prepareWrite(int cpu, int index) +Device::prepareWrite(ContextID cpu, int index) { prepareIO(cpu, index); } @@ -220,7 +220,7 @@ assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; @@ -270,7 +270,7 @@ * IPR read of device register Fault -Device::iprRead(Addr daddr, int cpu, uint64_t &result) +Device::iprRead(Addr daddr, ContextID cpu, uint64_t &result) { if (!regValid(daddr)) panic("invalid address: da=%#x", daddr); @@ -305,7 +305,7 @@ assert(config.command & PCI_CMD_MSE); assert(pkt->getAddr() >= BARAddrs[0] && pkt->getSize() < BARSize[0]); - int cpu = pkt->req->contextId(); + ContextID cpu = pkt->req->contextId(); Addr daddr = pkt->getAddr() - BARAddrs[0]; Addr index = daddr >> Regs::VirtualShift; Addr raddr = daddr & Regs::VirtualMask; diff -r 5c76426fd9ee -r 88dc51ebc6fa src/dev/sparc/iob.cc --- a/src/dev/sparc/iob.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/dev/sparc/iob.cc Tue Jul 07 15:32:34 2015 +0100 @@ -118,7 +118,7 @@ Iob::readJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; @@ -233,7 +233,7 @@ Iob::writeJBus(PacketPtr pkt) { Addr accessAddr = pkt->getAddr() - iobJBusAddr; - int cpuid = pkt->req->contextId(); + ContextID cpuid = pkt->req->contextId(); int index; uint64_t data; diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/abstract_mem.hh --- a/src/mem/abstract_mem.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/abstract_mem.hh Tue Jul 07 15:32:34 2015 +0100 @@ -74,7 +74,7 @@ Addr addr; // locking hw context - const int contextId; + const ContextID contextId; static Addr mask(Addr paddr) { return (paddr & ~Addr_Mask); } diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/cache/blk.hh --- a/src/mem/cache/blk.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/cache/blk.hh Tue Jul 07 15:32:34 2015 +0100 @@ -133,7 +133,7 @@ */ class Lock { public: - int contextId; // locking context + ContextID contextId; // locking context Addr lowAddr; // low address of lock range Addr highAddr; // high address of lock range diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/cache/cache_impl.hh Tue Jul 07 15:32:34 2015 +0100 @@ -340,7 +340,8 @@ return false; } - int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + ContextID id = pkt->req->hasContextId() ? + pkt->req->contextId() : InvalidContextID; // Here lat is the value passed as parameter to accessBlock() function // that can modify its value. blk = tags->accessBlock(pkt->getAddr(), pkt->isSecure(), lat, id); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/physical.cc --- a/src/mem/physical.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/physical.cc Tue Jul 07 15:32:34 2015 +0100 @@ -293,7 +293,7 @@ { // serialize all the locked addresses and their context ids vector lal_addr; - vector lal_cid; + vector lal_cid; for (auto& m : memories) { const list& locked_addrs = m->getLockedAddrList(); @@ -370,7 +370,7 @@ // unserialize the locked addresses and map them to the // appropriate memory controller vector lal_addr; - vector lal_cid; + vector lal_cid; UNSERIALIZE_CONTAINER(lal_addr); UNSERIALIZE_CONTAINER(lal_cid); for(size_t i = 0; i < lal_addr.size(); ++i) { diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/request.hh --- a/src/mem/request.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/request.hh Tue Jul 07 15:32:34 2015 +0100 @@ -295,7 +295,7 @@ uint64_t _extraData; /** The context ID (for statistics, typically). */ - int _contextId; + ContextID _contextId; /** The thread ID (id within this CPU) */ ThreadID _threadId; @@ -352,7 +352,7 @@ } Request(int asid, Addr vaddr, unsigned size, Flags flags, MasterID mid, - Addr pc, int cid, ThreadID tid) + Addr pc, ContextID cid, ThreadID tid) : _paddr(0), _size(0), _masterId(invldMasterId), _time(0), _taskId(ContextSwitchTaskId::Unknown), _asid(0), _vaddr(0), _extraData(0), _contextId(0), _threadId(0), _pc(0), @@ -368,7 +368,7 @@ * Set up CPU and thread numbers. */ void - setThreadContext(int context_id, ThreadID tid) + setThreadContext(ContextID context_id, ThreadID tid) { _contextId = context_id; _threadId = tid; @@ -590,7 +590,7 @@ } /** Accessor function for context ID.*/ - int + ContextID contextId() const { assert(privateFlags.isSet(VALID_CONTEXT_ID)); diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/ruby/slicc_interface/RubyRequest.hh --- a/src/mem/ruby/slicc_interface/RubyRequest.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/ruby/slicc_interface/RubyRequest.hh Tue Jul 07 15:32:34 2015 +0100 @@ -49,12 +49,12 @@ PrefetchBit m_Prefetch; uint8_t* data; PacketPtr pkt; - unsigned m_contextId; + ContextID m_contextId; RubyRequest(Tick curTime, uint64_t _paddr, uint8_t* _data, int _len, uint64_t _pc, RubyRequestType _type, RubyAccessMode _access_mode, PacketPtr _pkt, PrefetchBit _pb = PrefetchBit_No, - unsigned _proc_id = 100) + ContextID _proc_id = 100) : Message(curTime), m_PhysicalAddress(_paddr), m_Type(_type), diff -r 5c76426fd9ee -r 88dc51ebc6fa src/mem/ruby/system/Sequencer.cc --- a/src/mem/ruby/system/Sequencer.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/mem/ruby/system/Sequencer.cc Tue Jul 07 15:32:34 2015 +0100 @@ -665,10 +665,8 @@ Sequencer::issueRequest(PacketPtr pkt, RubyRequestType secondary_type) { assert(pkt != NULL); - int proc_id = -1; - if (pkt->req->hasContextId()) { - proc_id = pkt->req->contextId(); - } + ContextID proc_id = pkt->req->hasContextId() ? + pkt->req->contextId() : InvalidContextID; // If valid, copy the pc to the ruby request Addr pc = 0; diff -r 5c76426fd9ee -r 88dc51ebc6fa src/sim/process.hh --- a/src/sim/process.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/sim/process.hh Tue Jul 07 15:32:34 2015 +0100 @@ -73,7 +73,7 @@ System *system; // thread contexts associated with this process - std::vector contextIds; + std::vector contextIds; // number of CPUs (esxec contexts, really) assigned to this process. unsigned int numCpus() { return contextIds.size(); } @@ -176,7 +176,7 @@ // After getting registered with system object, tell process which // system-wide context id it is assigned. - void assignThreadContext(int context_id) + void assignThreadContext(ContextID context_id) { contextIds.push_back(context_id); } diff -r 5c76426fd9ee -r 88dc51ebc6fa src/sim/system.hh --- a/src/sim/system.hh Tue Jul 07 10:03:14 2015 +0100 +++ b/src/sim/system.hh Tue Jul 07 15:32:34 2015 +0100 @@ -197,7 +197,7 @@ std::vector threadContexts; int _numContexts; - ThreadContext *getThreadContext(ThreadID tid) + ThreadContext *getThreadContext(ContextID tid) { return threadContexts[tid]; } @@ -514,8 +514,9 @@ /// @return Starting address of first page Addr allocPhysPages(int npages); - int registerThreadContext(ThreadContext *tc, int assigned=-1); - void replaceThreadContext(ThreadContext *tc, int context_id); + ContextID registerThreadContext(ThreadContext *tc, + ContextID assigned = InvalidContextID); + void replaceThreadContext(ThreadContext *tc, ContextID context_id); void serialize(CheckpointOut &cp) const M5_ATTR_OVERRIDE; void unserialize(CheckpointIn &cp) M5_ATTR_OVERRIDE; diff -r 5c76426fd9ee -r 88dc51ebc6fa src/sim/system.cc --- a/src/sim/system.cc Tue Jul 07 10:03:14 2015 +0100 +++ b/src/sim/system.cc Tue Jul 07 15:32:34 2015 +0100 @@ -209,11 +209,11 @@ */ int rgdb_wait = -1; -int -System::registerThreadContext(ThreadContext *tc, int assigned) +ContextID +System::registerThreadContext(ThreadContext *tc, ContextID assigned) { int id; - if (assigned == -1) { + if (assigned == InvalidContextID) { for (id = 0; id < threadContexts.size(); id++) { if (!threadContexts[id]) break; @@ -305,7 +305,7 @@ } void -System::replaceThreadContext(ThreadContext *tc, int context_id) +System::replaceThreadContext(ThreadContext *tc, ContextID context_id) { if (context_id >= threadContexts.size()) { panic("replaceThreadContext: bad id, %d >= %d\n",