mem: Use the packet delays and do not just zero them out
Review Request #3172 - Created Oct. 30, 2015 and submitted
Information | |
---|---|
Andreas Hansson | |
gem5 | |
default | |
Reviewers | |
Default | |
Changeset 11191:d5063101794c --------------------------- mem: Use the packet delays and do not just zero them out This patch updates the I/O devices, bridge and simple memory to take the packet header and payload delay into account in their latency calculations. In all cases we add the header delay, i.e. the accumulated pipeline delay of any crossbars, and the payload delay needed for deserialisation of any payload. Due to the additional unknown latency contribution, the packet queue of the simple memory is changed to use insertion sorting based on the time stamp. Moreover, since the memory hands out exclusive (non shared) responses, we also need to ensure ordering for reads to the same address.
-
src/dev/io_device.cc (Diff revision 1) -
minor, but 'additional_latency' is rather nondescript. maybe 'transmission_delay' or 'receive_delay' or 'receive_latency' or something like thet?
-
src/dev/io_device.cc (Diff revision 1) -
out of scope for now, but just a thought: arguably this zeroing of the delay fields should probably take place in Packet::makeResponse()
-
src/mem/bridge.cc (Diff revision 1) -
why ticksToCycles()? aren't you adding a cycle value to a tick value?
-
src/mem/bridge.cc (Diff revision 1) -
likewise
-
src/mem/simple_mem.cc (Diff revision 1) -
this code looks awfully familiar :). is there a way to use PacketQueue here to avoid the redundancy?
Description: |
|
||||||||||||||||||||||||||||||||||||||||||||||||
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
Diff: |
Revision 2 (+52 -18) |
Ship It!