diff --git a/src/mem/ruby/system/CacheRecorder.cc b/src/mem/ruby/system/CacheRecorder.cc
--- a/src/mem/ruby/system/CacheRecorder.cc
+++ b/src/mem/ruby/system/CacheRecorder.cc
@@ -78,7 +78,7 @@
                                    m_block_size_bytes, 0,
                                    Request::funcMasterId);
         MemCmd::Command requestType = MemCmd::FlushReq;
-        Packet *pkt = new Packet(req, requestType);
+        PacketPtr pkt = new Packet(req, requestType);
 
         Sequencer* m_sequencer_ptr = m_seq_map[rec->m_cntrl_id];
         assert(m_sequencer_ptr != NULL);
@@ -120,7 +120,7 @@
                         current_block_size_bytes, 0, Request::funcMasterId);
             }
 
-            Packet *pkt = new Packet(req, requestType);
+            PacketPtr pkt = new Packet(req, requestType);
             pkt->dataStatic(traceRecord->m_data + rec_bytes_read);
 
             Sequencer* m_sequencer_ptr = m_seq_map[traceRecord->m_cntrl_id];
diff --git a/src/mem/ruby/system/RubySystem.hh b/src/mem/ruby/system/RubySystem.hh
--- a/src/mem/ruby/system/RubySystem.hh
+++ b/src/mem/ruby/system/RubySystem.hh
@@ -98,8 +98,8 @@
     void drainResume() override;
     void process();
     void startup() override;
-    bool functionalRead(Packet *ptr);
-    bool functionalWrite(Packet *ptr);
+    bool functionalRead(PacketPtr ptr);
+    bool functionalWrite(PacketPtr ptr);
 
     void registerNetwork(Network*);
     void registerAbstractController(AbstractController*);
diff --git a/src/mem/ruby/slicc_interface/AbstractController.hh b/src/mem/ruby/slicc_interface/AbstractController.hh
--- a/src/mem/ruby/slicc_interface/AbstractController.hh
+++ b/src/mem/ruby/slicc_interface/AbstractController.hh
@@ -92,12 +92,12 @@
 
     //! These functions are used by ruby system to read/write the data blocks
     //! that exist with in the controller.
-    virtual void functionalRead(const Addr &addr, PacketPtr) = 0;
+    virtual void functionalRead(const Addr &addr, const PacketPtr &pkt) = 0;
     void functionalMemoryRead(PacketPtr);
     //! The return value indicates the number of messages written with the
     //! data from the packet.
     virtual int functionalWriteBuffers(PacketPtr&) = 0;
-    virtual int functionalWrite(const Addr &addr, PacketPtr) = 0;
+    virtual int functionalWrite(const Addr &addr, const PacketPtr &pkt) = 0;
     int functionalMemoryWrite(PacketPtr);
 
     //! Function for enqueuing a prefetch request
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh
--- a/src/mem/ruby/slicc_interface/Message.hh
+++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -73,9 +73,9 @@
      * class that can be potentially searched for the address needs to
      * implement these methods.
      */
-    virtual bool functionalRead(Packet *pkt,
+    virtual bool functionalRead(PacketPtr const& pkt,
                                 const uint32_t &block_size_bits) = 0;
-    virtual bool functionalWrite(Packet *pkt,
+    virtual bool functionalWrite(PacketPtr const& pkt,
                                  const uint32_t &block_size_bits) = 0;
 
     //! Update the delay this message has experienced so far.
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.hh b/src/mem/ruby/slicc_interface/RubyRequest.hh
--- a/src/mem/ruby/slicc_interface/RubyRequest.hh
+++ b/src/mem/ruby/slicc_interface/RubyRequest.hh
@@ -152,8 +152,10 @@
     const PrefetchBit& getPrefetch() const { return m_Prefetch; }
 
     void print(std::ostream& out) const;
-    bool functionalRead(Packet *pkt, const uint32_t &block_size_bits);
-    bool functionalWrite(Packet *pkt, const uint32_t &block_size_bits);
+    bool functionalRead(PacketPtr const& pkt,
+                        const uint32_t &block_size_bits);
+    bool functionalWrite(PacketPtr const& pkt,
+                         const uint32_t &block_size_bits);
 };
 
 inline std::ostream&
diff --git a/src/mem/ruby/slicc_interface/RubyRequest.cc b/src/mem/ruby/slicc_interface/RubyRequest.cc
--- a/src/mem/ruby/slicc_interface/RubyRequest.cc
+++ b/src/mem/ruby/slicc_interface/RubyRequest.cc
@@ -48,7 +48,8 @@
 }
 
 bool
-RubyRequest::functionalRead(Packet *pkt, const uint32_t &block_size_bits)
+RubyRequest::functionalRead(PacketPtr const& pkt,
+                            const uint32_t &block_size_bits)
 {
     // This needs a little explanation. Initially I thought that this
     // message should be read. But the way the memtester works for now,
@@ -58,7 +59,8 @@
 }
 
 bool
-RubyRequest::functionalWrite(Packet *pkt, const uint32_t &block_size_bits)
+RubyRequest::functionalWrite(PacketPtr const& pkt,
+                             const uint32_t &block_size_bits)
 {
     // This needs a little explanation. I am not sure if this message
     // should be written. Essentially the question is how are writes
diff --git a/src/mem/ruby/structures/RubyMemoryControl.hh b/src/mem/ruby/structures/RubyMemoryControl.hh
--- a/src/mem/ruby/structures/RubyMemoryControl.hh
+++ b/src/mem/ruby/structures/RubyMemoryControl.hh
@@ -87,8 +87,8 @@
     int getRanksPerDimm() { return m_ranks_per_dimm; };
     int getDimmsPerChannel() { return m_dimms_per_channel; }
 
-    bool functionalRead(Packet *pkt);
-    uint32_t functionalWrite(Packet *pkt);
+    bool functionalRead(PacketPtr pkt);
+    uint32_t functionalWrite(PacketPtr pkt);
 
   private:
     void enqueueToDirectory(MemoryNode *req, Cycles latency);
diff --git a/src/mem/ruby/structures/RubyMemoryControl.cc b/src/mem/ruby/structures/RubyMemoryControl.cc
--- a/src/mem/ruby/structures/RubyMemoryControl.cc
+++ b/src/mem/ruby/structures/RubyMemoryControl.cc
@@ -669,7 +669,7 @@
  * being lists.
  */
 bool
-RubyMemoryControl::functionalRead(Packet *pkt)
+RubyMemoryControl::functionalRead(PacketPtr pkt)
 {
     for (std::list<MemoryNode *>::iterator it = m_input_queue.begin();
          it != m_input_queue.end(); ++it) {
@@ -710,7 +710,7 @@
  * for debugging purposes.
  */
 uint32_t
-RubyMemoryControl::functionalWrite(Packet *pkt)
+RubyMemoryControl::functionalWrite(PacketPtr pkt)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.hh
@@ -73,8 +73,8 @@
         m_net_ptr = net_ptr;
     }
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_virtual_networks, m_num_vcs, m_vc_per_vnet;
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/Router.cc
@@ -394,7 +394,7 @@
 }
 
 bool
-Router::functionalRead(Packet *pkt, uint32_t block_size_bits)
+Router::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     // Access the buffers in the router for performing a functional read
     for (unsigned int i = 0; i < m_router_buffers.size(); i++) {
@@ -416,7 +416,7 @@
 }
 
 uint32_t
-Router::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+Router::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/flit.hh
@@ -67,8 +67,8 @@
             return (n1->get_time() > n2->get_time());
     }
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    bool functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     const int m_id;
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc b/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/flit.cc
@@ -61,14 +61,14 @@
 }
 
 bool
-flit::functionalRead(Packet *pkt, uint32_t block_size_bits)
+flit::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     Message *msg = m_msg_ptr.get();
     return msg->functionalRead(pkt, block_size_bits);
 }
 
 bool
-flit::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+flit::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     Message *msg = m_msg_ptr.get();
     return msg->functionalWrite(pkt, block_size_bits);
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.hh
@@ -52,8 +52,8 @@
     void insert(flit *flt);
     void print(std::ostream& out) const;
 
-    bool functionalRead(Packet *, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     std::vector<flit *> m_buffer;
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/flitBuffer.cc
@@ -103,7 +103,7 @@
 }
 
 bool
-flitBuffer::functionalRead(Packet *pkt, uint32_t block_size_bits)
+flitBuffer::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     for (unsigned int i = 0; i < m_buffer.size(); ++i) {
         if (m_buffer[i]->functionalRead(pkt, block_size_bits)) {
@@ -114,7 +114,7 @@
 }
 
 uint32_t
-flitBuffer::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+flitBuffer::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.hh b/src/mem/ruby/network/simple/SimpleNetwork.hh
--- a/src/mem/ruby/network/simple/SimpleNetwork.hh
+++ b/src/mem/ruby/network/simple/SimpleNetwork.hh
@@ -71,8 +71,8 @@
 
     void print(std::ostream& out) const;
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     void addLink(SwitchID src, SwitchID dest, int link_latency);
diff --git a/src/mem/ruby/network/simple/SimpleNetwork.cc b/src/mem/ruby/network/simple/SimpleNetwork.cc
--- a/src/mem/ruby/network/simple/SimpleNetwork.cc
+++ b/src/mem/ruby/network/simple/SimpleNetwork.cc
@@ -182,7 +182,7 @@
  * between different switches have buffers that need to be accessed.
  */
 bool
-SimpleNetwork::functionalRead(Packet *pkt, uint32_t block_size_bits)
+SimpleNetwork::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     for (unsigned int i = 0; i < m_switches.size(); i++) {
         if (m_switches[i]->functionalRead(pkt, block_size_bits)) {
@@ -194,7 +194,7 @@
 }
 
 uint32_t
-SimpleNetwork::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+SimpleNetwork::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/simple/Switch.hh b/src/mem/ruby/network/simple/Switch.hh
--- a/src/mem/ruby/network/simple/Switch.hh
+++ b/src/mem/ruby/network/simple/Switch.hh
@@ -78,8 +78,8 @@
     void print(std::ostream& out) const;
     void init_net_ptr(SimpleNetwork* net_ptr) { m_network_ptr = net_ptr; }
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     // Private copy constructor and assignment operator
diff --git a/src/mem/ruby/network/simple/Switch.cc b/src/mem/ruby/network/simple/Switch.cc
--- a/src/mem/ruby/network/simple/Switch.cc
+++ b/src/mem/ruby/network/simple/Switch.cc
@@ -169,13 +169,13 @@
 }
 
 bool
-Switch::functionalRead(Packet *pkt, uint32_t block_size_bits)
+Switch::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     return false;
 }
 
 uint32_t
-Switch::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+Switch::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     // Access the buffers in the switch for performing a functional write
     uint32_t num_functional_writes = 0;
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.cc
@@ -158,7 +158,7 @@
  * links for reading/writing all the messages.
  */
 bool
-GarnetNetwork::functionalRead(Packet *pkt, uint32_t block_size_bits)
+GarnetNetwork::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     for (unsigned int i = 0; i < m_routers.size(); i++) {
         if (m_routers[i]->functionalRead(pkt, block_size_bits)) {
@@ -182,7 +182,7 @@
 }
 
 uint32_t
-GarnetNetwork::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+GarnetNetwork::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.hh
@@ -68,8 +68,8 @@
 
     void print(std::ostream& out) const;
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
     void init_net_ptr(GarnetNetwork* net_ptr) { m_net_ptr = net_ptr; }
 
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkInterface.cc
@@ -329,7 +329,7 @@
 }
 
 bool
-NetworkInterface::functionalRead(Packet *pkt, uint32_t block_size_bits)
+NetworkInterface::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     // Go through the internal buffers
     for (unsigned int i = 0; i < m_ni_buffers.size(); ++i) {
@@ -347,7 +347,7 @@
 }
 
 uint32_t
-NetworkInterface::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+NetworkInterface::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
     for (unsigned int i = 0; i < m_ni_buffers.size(); ++i) {
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.hh
@@ -74,8 +74,8 @@
     unsigned int getLinkUtilization() const { return m_link_utilized; }
     const std::vector<unsigned int> & getVcLoad() const { return m_vc_load; }
 
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_id;
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
--- a/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/NetworkLink.cc
@@ -133,13 +133,13 @@
 }
 
 bool
-NetworkLink::functionalRead(Packet *pkt, uint32_t block_size_bits)
+NetworkLink::functionalRead(PacketPtr pkt, uint32_t block_size_bits)
 {
     return linkBuffer->functionalRead(pkt, block_size_bits);
 }
 
 uint32_t
-NetworkLink::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+NetworkLink::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     return linkBuffer->functionalWrite(pkt, block_size_bits);
 }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.cc
@@ -252,7 +252,7 @@
 }
 
 uint32_t
-Router_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+Router_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
     num_functional_writes += m_switch->functionalWrite(pkt, block_size_bits);
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.hh
@@ -56,7 +56,7 @@
 
     inline double get_crossbar_count() { return m_crossbar_activity; }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_num_vcs;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Switch_d.cc
@@ -99,7 +99,7 @@
 }
 
 uint32_t
-Switch_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+Switch_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
    uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.hh
@@ -85,7 +85,7 @@
         return m_input_buffer->getTopFlit();
     }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_id;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/VirtualChannel_d.cc
@@ -74,7 +74,7 @@
 }
 
 uint32_t
-VirtualChannel_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+VirtualChannel_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     return m_input_buffer->functionalWrite(pkt, block_size_bits);
 }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.hh
@@ -72,7 +72,7 @@
         std::push_heap(m_buffer.begin(), m_buffer.end(), flit_d::greater);
     }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     std::vector<flit_d *> m_buffer;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/flitBuffer_d.cc
@@ -76,7 +76,7 @@
 }
 
 uint32_t
-flitBuffer_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+flitBuffer_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.hh
@@ -88,7 +88,7 @@
         }
     }
 
-    bool functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_id;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/flit_d.cc
@@ -76,7 +76,7 @@
 }
 
 bool
-flit_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+flit_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     Message *msg = m_msg_ptr.get();
     return msg->functionalWrite(pkt, block_size_bits);
diff --git a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
--- a/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
+++ b/src/mem/ruby/network/garnet/flexible-pipeline/GarnetNetwork.hh
@@ -72,11 +72,11 @@
 
     //! Function for performing a functional read. The return value
     //! indicates if a message was found that had the required address.
-    bool functionalRead(Packet *pkt, uint32_t block_size_bits);
+    bool functionalRead(PacketPtr pkt, uint32_t block_size_bits);
 
     //! Function for performing a functional write. The return value
     //! indicates the number of messages that were written.
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     GarnetNetwork(const GarnetNetwork& obj);
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.hh
@@ -86,7 +86,7 @@
         m_out_link->scheduleEventAbsolute(m_router->clockEdge(Cycles(1)));
     }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_id;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/OutputUnit_d.cc
@@ -110,7 +110,7 @@
 }
 
 uint32_t
-OutputUnit_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+OutputUnit_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     return m_out_buffer->functionalWrite(pkt, block_size_bits);
 }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/Router_d.hh
@@ -105,7 +105,7 @@
                                                       aggregate_fault_prob);
     }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     int m_virtual_networks, m_num_vcs, m_vc_per_vnet;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.hh
@@ -66,7 +66,7 @@
     int get_vnet(int vc);
     void init_net_ptr(GarnetNetwork_d *net_ptr) { m_net_ptr = net_ptr; }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     GarnetNetwork_d *m_net_ptr;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkInterface_d.cc
@@ -363,7 +363,7 @@
 }
 
 uint32_t
-NetworkInterface_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+NetworkInterface_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
     for (unsigned int i  = 0; i < m_num_vcs; ++i) {
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.hh
@@ -64,7 +64,7 @@
     inline flit_d* peekLink()       { return linkBuffer->peekTopFlit(); }
     inline flit_d* consumeLink()    { return linkBuffer->getTopFlit(); }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     const int m_id;
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/NetworkLink_d.cc
@@ -83,7 +83,7 @@
 }
 
 uint32_t
-NetworkLink_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+NetworkLink_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     return linkBuffer->functionalWrite(pkt, block_size_bits);
 }
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.cc
@@ -251,7 +251,7 @@
 }
 
 uint32_t
-GarnetNetwork_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+GarnetNetwork_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.hh
@@ -158,7 +158,7 @@
     double get_buf_write_count(unsigned int vnet) const
     { return m_num_buffer_writes[vnet]; }
 
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
     void resetStats();
 
   private:
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
--- a/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/InputUnit_d.cc
@@ -102,7 +102,7 @@
 }
 
 uint32_t
-InputUnit_d::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+InputUnit_d::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
     for (int i=0; i < m_num_vcs; i++) {
diff --git a/src/mem/protocol/Network_test-cache.sm b/src/mem/protocol/Network_test-cache.sm
--- a/src/mem/protocol/Network_test-cache.sm
+++ b/src/mem/protocol/Network_test-cache.sm
@@ -116,11 +116,11 @@
     return OOD;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("Network test does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("Network test does not support functional write.");
   }
 
diff --git a/src/mem/protocol/Network_test-dir.sm b/src/mem/protocol/Network_test-dir.sm
--- a/src/mem/protocol/Network_test-dir.sm
+++ b/src/mem/protocol/Network_test-dir.sm
@@ -78,11 +78,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("Network test does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("Network test does not support functional write.");
   }
 
diff --git a/src/mem/protocol/Network_test-msg.sm b/src/mem/protocol/Network_test-msg.sm
--- a/src/mem/protocol/Network_test-msg.sm
+++ b/src/mem/protocol/Network_test-msg.sm
@@ -41,11 +41,11 @@
   DataBlock DataBlk,           desc="data for the cache line";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     error("Network test does not support functional accesses!");
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     error("Network test does not support functional accesses!");
   }
 }
diff --git a/src/mem/protocol/RubySlicc_Defines.sm b/src/mem/protocol/RubySlicc_Defines.sm
--- a/src/mem/protocol/RubySlicc_Defines.sm
+++ b/src/mem/protocol/RubySlicc_Defines.sm
@@ -46,5 +46,5 @@
 // Functions implemented in the AbstractController class for
 // making functional access to the memory maintained by the
 // memory controllers.
-void functionalMemoryRead(Packet *pkt);
-bool functionalMemoryWrite(Packet *pkt);
+void functionalMemoryRead(PacketPtr pkt);
+bool functionalMemoryWrite(PacketPtr pkt);
diff --git a/src/mem/protocol/RubySlicc_Exports.sm b/src/mem/protocol/RubySlicc_Exports.sm
--- a/src/mem/protocol/RubySlicc_Exports.sm
+++ b/src/mem/protocol/RubySlicc_Exports.sm
@@ -57,11 +57,11 @@
   void atomicPartial(DataBlock, WriteMask);
 }
 
-bool testAndRead(Addr addr, DataBlock datablk, Packet *pkt,
+bool testAndRead(Addr addr, DataBlock datablk, PacketPtr pkt,
                  uint32_t block_size_bits);
-bool testAndReadMask(Addr addr, DataBlock datablk, WriteMask mask, Packet *pkt,
-                     uint32_t block_size_bits);
-bool testAndWrite(Addr addr, DataBlock datablk, Packet *pkt,
+bool testAndReadMask(Addr addr, DataBlock datablk, WriteMask mask,
+                     PacketPtr pkt, uint32_t block_size_bits);
+bool testAndWrite(Addr addr, DataBlock datablk, PacketPtr pkt,
                   uint32_t block_size_bits);
 
 // AccessPermission
@@ -293,11 +293,11 @@
   PrefetchBit Prefetch,      desc="Is this a prefetch request";
   MessageSizeType MessageSize;
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(PhysicalAddress, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(PhysicalAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/RubySlicc_MemControl.sm b/src/mem/protocol/RubySlicc_MemControl.sm
--- a/src/mem/protocol/RubySlicc_MemControl.sm
+++ b/src/mem/protocol/RubySlicc_MemControl.sm
@@ -62,11 +62,11 @@
   bool ReadX,                   desc="Exclusive";
   int Acks,                     desc="How many acks to expect";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/ruby/network/MessageBuffer.hh b/src/mem/ruby/network/MessageBuffer.hh
--- a/src/mem/ruby/network/MessageBuffer.hh
+++ b/src/mem/ruby/network/MessageBuffer.hh
@@ -120,7 +120,7 @@
     // to be updated with the data from the packet.
     // Return value indicates the number of messages that were updated.
     // This required for debugging the code.
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     void reanalyzeList(std::list<MsgPtr> &, Tick);
diff --git a/src/mem/ruby/network/MessageBuffer.cc b/src/mem/ruby/network/MessageBuffer.cc
--- a/src/mem/ruby/network/MessageBuffer.cc
+++ b/src/mem/ruby/network/MessageBuffer.cc
@@ -350,7 +350,7 @@
 }
 
 uint32_t
-MessageBuffer::functionalWrite(Packet *pkt, uint32_t block_size_bits)
+MessageBuffer::functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
 {
     uint32_t num_functional_writes = 0;
 
diff --git a/src/mem/ruby/network/Network.hh b/src/mem/ruby/network/Network.hh
--- a/src/mem/ruby/network/Network.hh
+++ b/src/mem/ruby/network/Network.hh
@@ -98,9 +98,9 @@
      * the network. Each network needs to implement these for functional
      * accesses to work correctly.
      */
-    virtual bool functionalRead(Packet *pkt, uint32_t block_size_bits)
+    virtual bool functionalRead(PacketPtr pkt, uint32_t block_size_bits)
     { fatal("Functional read not implemented.\n"); }
-    virtual uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits)
+    virtual uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits)
     { fatal("Functional write not implemented.\n"); }
 
   protected:
diff --git a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
--- a/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
+++ b/src/mem/ruby/network/garnet/fixed-pipeline/GarnetNetwork_d.hh
@@ -81,7 +81,7 @@
 
     //! Function for performing a functional write. The return value
     //! indicates the number of messages that were written.
-    uint32_t functionalWrite(Packet *pkt, uint32_t block_size_bits);
+    uint32_t functionalWrite(PacketPtr pkt, uint32_t block_size_bits);
 
   private:
     GarnetNetwork_d(const GarnetNetwork_d& obj);
diff --git a/src/mem/protocol/MOESI_CMP_token-dma.sm b/src/mem/protocol/MOESI_CMP_token-dma.sm
--- a/src/mem/protocol/MOESI_CMP_token-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dma.sm
@@ -74,11 +74,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional write.");
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_token-msg.sm b/src/mem/protocol/MOESI_CMP_token-msg.sm
--- a/src/mem/protocol/MOESI_CMP_token-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_token-msg.sm
@@ -66,12 +66,12 @@
   RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // No data in persistent messages
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No data in persistent messages
     return false;
   }
@@ -89,12 +89,12 @@
   RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // No data in request messages
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No data in request messages
     return false;
   }
@@ -111,12 +111,12 @@
   bool Dirty,                  desc="Is the data dirty (different than memory)?";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // No check being carried out on the message type. Would be added later.
     return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check required since all messages are written.
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
@@ -144,11 +144,11 @@
   int Len,                   desc="The length of the request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
@@ -161,11 +161,11 @@
   DataBlock DataBlk,         desc="DataBlk attached to this request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MOESI_hammer-cache.sm b/src/mem/protocol/MOESI_hammer-cache.sm
--- a/src/mem/protocol/MOESI_hammer-cache.sm
+++ b/src/mem/protocol/MOESI_hammer-cache.sm
@@ -207,7 +207,7 @@
     return L1Icache_entry;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
       testAndRead(addr, cache_entry.DataBlk, pkt, block_size_bits);
@@ -221,7 +221,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     Entry cache_entry := getCacheEntry(addr);
diff --git a/src/mem/protocol/MOESI_hammer-dir.sm b/src/mem/protocol/MOESI_hammer-dir.sm
--- a/src/mem/protocol/MOESI_hammer-dir.sm
+++ b/src/mem/protocol/MOESI_hammer-dir.sm
@@ -271,7 +271,7 @@
     getDirectoryEntry(addr).changePermission(Directory_State_to_permission(state));
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -280,7 +280,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MOESI_hammer-dma.sm b/src/mem/protocol/MOESI_hammer-dma.sm
--- a/src/mem/protocol/MOESI_hammer-dma.sm
+++ b/src/mem/protocol/MOESI_hammer-dma.sm
@@ -70,11 +70,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional write.");
   }
 
diff --git a/src/mem/protocol/MOESI_hammer-msg.sm b/src/mem/protocol/MOESI_hammer-msg.sm
--- a/src/mem/protocol/MOESI_hammer-msg.sm
+++ b/src/mem/protocol/MOESI_hammer-msg.sm
@@ -74,12 +74,12 @@
   Addr addr,             desc="Physical address for this request";
   TriggerType Type,            desc="Type of trigger";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Trigger messages do not hold any data!
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // Trigger messages do not hold any data!
     return false;
   }
@@ -101,12 +101,12 @@
         desc="time the dir forwarded the request";
   int SilentAcks, default="0", desc="silent acks from the full-bit directory";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Request messages do not hold any data
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // Request messages do not hold any data
     return false;
   }
@@ -130,7 +130,7 @@
         desc="time the dir forwarded the request";
   int SilentAcks, default="0", desc="silent acks from the full-bit directory";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // The check below ensures that data is read only from messages that
     // actually hold data.
     if (Type == CoherenceResponseType:DATA ||
@@ -144,7 +144,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // Message type does not matter since all messages are written.
     // If a protocol reads data from a packet that is not supposed
     // to hold the data, then the fault lies with the protocol.
@@ -174,11 +174,11 @@
   int Len,                   desc="The length of the request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
@@ -191,11 +191,11 @@
   DataBlock DataBlk,         desc="DataBlk attached to this request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MOESI_AMD_Base-msg.sm b/src/mem/protocol/MOESI_AMD_Base-msg.sm
--- a/src/mem/protocol/MOESI_AMD_Base-msg.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-msg.sm
@@ -142,7 +142,7 @@
   bool NoWriteConflict,             default="true", desc="write collided with CAB entry";
   int ProgramCounter,               desc="PC that accesses to this block";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:VicDirty) {
         return testAndRead(addr, DataBlk, pkt, block_size_bits);
@@ -151,7 +151,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -170,11 +170,11 @@
   bool NoAckNeeded, default="false", desc="For short circuting acks";
   int ProgramCounter,           desc="PC that accesses to this block";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -193,11 +193,11 @@
   int wfid,               desc="wavefront id for Release";
   MachineID Requestor,    desc="Node who initiated the request";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -251,7 +251,7 @@
   bool mispred,              desc="tell TCP if the block should not be bypassed";
 
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceResponseType:CPUData ||
         Type == CoherenceResponseType:MemData) {
@@ -261,7 +261,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -280,11 +280,11 @@
   bool valid, default="false", desc="Is block valid";
   bool validToInvalid, default="false", desc="Was block valid when evicted";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -324,11 +324,11 @@
   CacheId Dest,         default="CacheId_NA", desc="Cache to invalidate";
   int ProgramCounter,           desc="PC that accesses to this block";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -349,11 +349,11 @@
   MachineID Requestor,      desc="Flush Requestor";
   MachineID oRequestor,      desc="original Flush Requestor";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
diff --git a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
--- a/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-probeFilter.sm
@@ -242,7 +242,7 @@
     getDirectoryEntry(addr).DirectoryState := state;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -251,7 +251,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm
@@ -216,7 +216,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     Entry cache_entry := getCacheEntry(addr);
     if(is_valid(cache_entry)) {
       testAndRead(addr, cache_entry.DataBlk, pkt, block_size_bits);
@@ -230,7 +230,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     Entry cache_entry := getCacheEntry(addr);
diff --git a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm
@@ -547,7 +547,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -556,7 +556,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MOESI_CMP_directory-dir.sm b/src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm
@@ -193,11 +193,11 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     functionalMemoryRead(pkt);
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
     num_functional_writes := num_functional_writes + functionalMemoryWrite(pkt);
     return num_functional_writes;
diff --git a/src/mem/protocol/MOESI_CMP_directory-dma.sm b/src/mem/protocol/MOESI_CMP_directory-dma.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dma.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-dma.sm
@@ -94,11 +94,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional write.");
   }
 
diff --git a/src/mem/protocol/MOESI_CMP_directory-msg.sm b/src/mem/protocol/MOESI_CMP_directory-msg.sm
--- a/src/mem/protocol/MOESI_CMP_directory-msg.sm
+++ b/src/mem/protocol/MOESI_CMP_directory-msg.sm
@@ -72,12 +72,12 @@
   Addr addr,             desc="Physical address for this request";
   TriggerType Type,            desc="Type of trigger";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Trigger message does not hold data
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // Trigger message does not hold data
     return false;
   }
@@ -97,7 +97,7 @@
   RubyAccessMode AccessMode,    desc="user/supervisor access type";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Read only those messages that contain the data
     if (Type == CoherenceRequestType:DMA_READ ||
         Type == CoherenceRequestType:DMA_WRITE) {
@@ -106,7 +106,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check required since all messages are written
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
@@ -124,7 +124,7 @@
   int Acks,                    desc="How many acks to expect";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Read only those messages that contain the data
     if (Type == CoherenceResponseType:DATA ||
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
@@ -135,7 +135,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check required since all messages are written
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
   }
diff --git a/src/mem/protocol/MOESI_CMP_token-L1cache.sm b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L1cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L1cache.sm
@@ -243,11 +243,11 @@
     return L1Icache_entry;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
     num_functional_writes := num_functional_writes +
         testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
diff --git a/src/mem/protocol/MOESI_CMP_token-L2cache.sm b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_token-L2cache.sm
+++ b/src/mem/protocol/MOESI_CMP_token-L2cache.sm
@@ -166,11 +166,11 @@
     return localDirectory.lookup(address);
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     testAndRead(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
     num_functional_writes := num_functional_writes +
         testAndWrite(addr, getCacheEntry(addr).DataBlk, pkt, block_size_bits);
diff --git a/src/mem/protocol/MOESI_CMP_token-dir.sm b/src/mem/protocol/MOESI_CMP_token-dir.sm
--- a/src/mem/protocol/MOESI_CMP_token-dir.sm
+++ b/src/mem/protocol/MOESI_CMP_token-dir.sm
@@ -250,7 +250,7 @@
     persistentTable.markEntries(addr);
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -259,7 +259,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-CorePair.sm
@@ -330,7 +330,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -339,7 +339,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-dir.sm
@@ -261,7 +261,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -270,7 +270,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm b/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
--- a/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-Region-msg.sm
@@ -127,7 +127,7 @@
   int Acks, default="0", desc="Acks that the dir (mem ctrl) should expect to receive";
   CoherenceRequestType OriginalType, default="CoherenceRequestType_NA",  desc="Type of request from core fwded through region buffer";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:VicDirty) {
         return testAndRead(addr, DataBlk, pkt, block_size_bits);
@@ -136,7 +136,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -154,11 +154,11 @@
   MachineID Requestor,          desc="Requestor id for 3-hop requests";
   bool NoAckNeeded, default="false", desc="For short circuting acks";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -181,11 +181,11 @@
   bool valid, default="false", desc="Is block valid";
   bool validToInvalid, default="false", desc="Was block valid when evicted";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
@@ -228,7 +228,7 @@
   bool NoAckNeeded, default="false", desc="For short circuting acks";
   bool isValid, default="false", desc="Is acked block valid";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceResponseType:CPUData ||
         Type == CoherenceResponseType:MemData) {
@@ -238,7 +238,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -278,11 +278,11 @@
   TriggerType Type,             desc="Type of trigger";
   CacheId Dest,         default="CacheId_NA", desc="Cache to invalidate";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return false;
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionBuffer.sm
@@ -317,11 +317,11 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     functionalMemoryRead(pkt);
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     if (functionalMemoryWrite(pkt)) {
       return 1;
     } else {
diff --git a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-RegionDir.sm
@@ -294,11 +294,11 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     functionalMemoryRead(pkt);
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     if (functionalMemoryWrite(pkt)) {
       return 1;
     } else {
diff --git a/src/mem/protocol/MOESI_AMD_Base-dir.sm b/src/mem/protocol/MOESI_AMD_Base-dir.sm
--- a/src/mem/protocol/MOESI_AMD_Base-dir.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-dir.sm
@@ -202,7 +202,7 @@
     getDirectoryEntry(addr).DirectoryState := state;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -211,7 +211,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MESI_Two_Level-L2cache.sm b/src/mem/protocol/MESI_Two_Level-L2cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L2cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L2cache.sm
@@ -218,7 +218,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -227,7 +227,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MESI_Two_Level-dir.sm b/src/mem/protocol/MESI_Two_Level-dir.sm
--- a/src/mem/protocol/MESI_Two_Level-dir.sm
+++ b/src/mem/protocol/MESI_Two_Level-dir.sm
@@ -92,8 +92,8 @@
     void allocate(Addr);
     void deallocate(Addr);
     bool isPresent(Addr);
-    bool functionalRead(Packet *pkt);
-    int functionalWrite(Packet *pkt);
+    bool functionalRead(PacketPtr pkt);
+    int functionalWrite(PacketPtr pkt);
   }
 
 
@@ -154,7 +154,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -163,7 +163,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MESI_Two_Level-dma.sm b/src/mem/protocol/MESI_Two_Level-dma.sm
--- a/src/mem/protocol/MESI_Two_Level-dma.sm
+++ b/src/mem/protocol/MESI_Two_Level-dma.sm
@@ -70,11 +70,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional write.");
   }
 
diff --git a/src/mem/protocol/MESI_Two_Level-msg.sm b/src/mem/protocol/MESI_Two_Level-msg.sm
--- a/src/mem/protocol/MESI_Two_Level-msg.sm
+++ b/src/mem/protocol/MESI_Two_Level-msg.sm
@@ -69,7 +69,7 @@
   bool Dirty, default="false",  desc="Dirty bit";
   PrefetchBit Prefetch,         desc="Is this a prefetch request";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Type == CoherenceRequestType:PUTX) {
         return testAndRead(addr, DataBlk, pkt, block_size_bits);
@@ -78,7 +78,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -96,7 +96,7 @@
   int AckCount, default="0",  desc="number of acks in this message";
   MessageSizeType MessageSize,  desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Valid data block is only present in message with following types
     if (Type == CoherenceResponseType:DATA ||
         Type == CoherenceResponseType:DATA_EXCLUSIVE ||
@@ -108,7 +108,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
diff --git a/src/mem/protocol/MI_example-cache.sm b/src/mem/protocol/MI_example-cache.sm
--- a/src/mem/protocol/MI_example-cache.sm
+++ b/src/mem/protocol/MI_example-cache.sm
@@ -174,7 +174,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -183,7 +183,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MI_example-dir.sm b/src/mem/protocol/MI_example-dir.sm
--- a/src/mem/protocol/MI_example-dir.sm
+++ b/src/mem/protocol/MI_example-dir.sm
@@ -177,7 +177,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -186,7 +186,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MI_example-dma.sm b/src/mem/protocol/MI_example-dma.sm
--- a/src/mem/protocol/MI_example-dma.sm
+++ b/src/mem/protocol/MI_example-dma.sm
@@ -72,11 +72,11 @@
   void setAccessPermission(Addr addr, State state) {
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional read.");
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     error("DMA does not support functional write.");
   }
 
diff --git a/src/mem/protocol/MI_example-msg.sm b/src/mem/protocol/MI_example-msg.sm
--- a/src/mem/protocol/MI_example-msg.sm
+++ b/src/mem/protocol/MI_example-msg.sm
@@ -58,7 +58,7 @@
   DataBlock DataBlk,           desc="data for the cache line";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Valid data block is only present in PUTX messages
     if (Type == CoherenceRequestType:PUTX) {
         return testAndRead(addr, DataBlk, pkt, block_size_bits);
@@ -66,7 +66,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -83,13 +83,13 @@
   bool Dirty,                  desc="Is the data dirty (different than memory)?";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // A check on message type should appear here so that only those
     // messages that contain data
     return testAndRead(addr, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should read
     // data block from only those messages that contain valid data
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
@@ -118,11 +118,11 @@
   int Len,                   desc="The length of the request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
@@ -135,11 +135,11 @@
   DataBlock DataBlk,         desc="DataBlk attached to this request";
   MessageSizeType MessageSize, desc="size category of the message";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndRead(LineAddress, DataBlk, pkt, block_size_bits);
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     return testAndWrite(LineAddress, DataBlk, pkt, block_size_bits);
   }
 }
diff --git a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
--- a/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-CorePair.sm
@@ -322,7 +322,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -331,7 +331,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
--- a/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
+++ b/src/mem/protocol/MOESI_AMD_Base-L3cache.sm
@@ -194,7 +194,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -203,7 +203,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_VIPER-TCP.sm b/src/mem/protocol/GPU_VIPER-TCP.sm
--- a/src/mem/protocol/GPU_VIPER-TCP.sm
+++ b/src/mem/protocol/GPU_VIPER-TCP.sm
@@ -164,7 +164,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -173,7 +173,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_VIPER_Region-TCC.sm b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
--- a/src/mem/protocol/GPU_VIPER_Region-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER_Region-TCC.sm
@@ -174,7 +174,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -183,7 +183,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/MESI_Three_Level-L0cache.sm b/src/mem/protocol/MESI_Three_Level-L0cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L0cache.sm
@@ -207,7 +207,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -216,7 +216,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MESI_Three_Level-L1cache.sm b/src/mem/protocol/MESI_Three_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Three_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Three_Level-L1cache.sm
@@ -203,7 +203,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -212,7 +212,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
diff --git a/src/mem/protocol/MESI_Three_Level-msg.sm b/src/mem/protocol/MESI_Three_Level-msg.sm
--- a/src/mem/protocol/MESI_Three_Level-msg.sm
+++ b/src/mem/protocol/MESI_Three_Level-msg.sm
@@ -59,7 +59,7 @@
   DataBlock DataBlk,            desc="Data for the cache line (if PUTX)";
   bool Dirty, default="false",  desc="Dirty bit";
 
-  bool functionalRead(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalRead(PacketPtr pkt, uint32_t block_size_bits) {
     // Only PUTX messages contains the data block
     if (Class == CoherenceClass:PUTX) {
         return testAndRead(addr, DataBlk, pkt, block_size_bits);
@@ -68,7 +68,7 @@
     return false;
   }
 
-  bool functionalWrite(Packet *pkt, uint32_t block_size_bits) {
+  bool functionalWrite(PacketPtr pkt, uint32_t block_size_bits) {
     // No check on message type required since the protocol should
     // read data from those messages that contain the block
     return testAndWrite(addr, DataBlk, pkt, block_size_bits);
diff --git a/src/mem/protocol/MESI_Two_Level-L1cache.sm b/src/mem/protocol/MESI_Two_Level-L1cache.sm
--- a/src/mem/protocol/MESI_Two_Level-L1cache.sm
+++ b/src/mem/protocol/MESI_Two_Level-L1cache.sm
@@ -226,7 +226,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs[addr];
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -235,7 +235,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs[addr];
# Node ID 038751298a2f1160ba2bd27df18991ecb5700267
# Parent  ad4de3019da1eb0071d4b6da1bc807bac17665ec
diff --git a/src/mem/cache/cache.cc b/src/mem/cache/cache.cc
--- a/src/mem/cache/cache.cc
+++ b/src/mem/cache/cache.cc
@@ -631,7 +631,7 @@
         // create a downstream express snoop with cleared packet
         // flags, there is no need to allocate any data as the
         // packet is merely used to co-ordinate state transitions
-        Packet *snoop_pkt = new Packet(pkt, true, false);
+        PacketPtr snoop_pkt = new Packet(pkt, true, false);
 
         // also reset the bus time that the original packet has
         // not yet paid for
@@ -1356,7 +1356,7 @@
 
     while (mshr->hasTargets()) {
         MSHR::Target *target = mshr->getTarget();
-        Packet *tgt_pkt = target->pkt;
+        PacketPtr tgt_pkt = target->pkt;
 
         switch (target->source) {
           case MSHR::Target::FromCPU:
diff --git a/src/mem/packet.hh b/src/mem/packet.hh
--- a/src/mem/packet.hh
+++ b/src/mem/packet.hh
@@ -630,7 +630,7 @@
         cmd = MemCmd::BadAddressError;
     }
 
-    void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; }
+    void copyError(PacketPtr pkt) { assert(pkt->isError()); cmd = pkt->cmd; }
 
     Addr getAddr() const { assert(flags.isSet(VALID_ADDR)); return addr; }
     /**
diff --git a/src/mem/protocol/GPU_RfO-SQC.sm b/src/mem/protocol/GPU_RfO-SQC.sm
--- a/src/mem/protocol/GPU_RfO-SQC.sm
+++ b/src/mem/protocol/GPU_RfO-SQC.sm
@@ -176,7 +176,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -185,7 +185,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_RfO-TCC.sm b/src/mem/protocol/GPU_RfO-TCC.sm
--- a/src/mem/protocol/GPU_RfO-TCC.sm
+++ b/src/mem/protocol/GPU_RfO-TCC.sm
@@ -212,7 +212,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -221,7 +221,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_RfO-TCCdir.sm b/src/mem/protocol/GPU_RfO-TCCdir.sm
--- a/src/mem/protocol/GPU_RfO-TCCdir.sm
+++ b/src/mem/protocol/GPU_RfO-TCCdir.sm
@@ -301,7 +301,7 @@
     return AccessPermission:NotPresent;
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -310,7 +310,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_RfO-TCP.sm b/src/mem/protocol/GPU_RfO-TCP.sm
--- a/src/mem/protocol/GPU_RfO-TCP.sm
+++ b/src/mem/protocol/GPU_RfO-TCP.sm
@@ -205,7 +205,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -214,7 +214,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_VIPER-SQC.sm b/src/mem/protocol/GPU_VIPER-SQC.sm
--- a/src/mem/protocol/GPU_VIPER-SQC.sm
+++ b/src/mem/protocol/GPU_VIPER-SQC.sm
@@ -137,7 +137,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -146,7 +146,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);
diff --git a/src/mem/protocol/GPU_VIPER-TCC.sm b/src/mem/protocol/GPU_VIPER-TCC.sm
--- a/src/mem/protocol/GPU_VIPER-TCC.sm
+++ b/src/mem/protocol/GPU_VIPER-TCC.sm
@@ -163,7 +163,7 @@
     }
   }
 
-  void functionalRead(Addr addr, Packet *pkt) {
+  void functionalRead(Addr addr, PacketPtr pkt) {
     TBE tbe := TBEs.lookup(addr);
     if(is_valid(tbe)) {
       testAndRead(addr, tbe.DataBlk, pkt, block_size_bits);
@@ -172,7 +172,7 @@
     }
   }
 
-  int functionalWrite(Addr addr, Packet *pkt) {
+  int functionalWrite(Addr addr, PacketPtr pkt) {
     int num_functional_writes := 0;
 
     TBE tbe := TBEs.lookup(addr);