riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

Information
Submitter:	Alec Roelke
Repository:	gem5
Branch:	default
Bugs:
Depends On:
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Groups:	Default
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Description

Changeset 11690:9451dd15dc90
---------------------------
riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
extensions, which include single- and double-precision floating point
instructions.

Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
and patch 2 implemented the integer multiply extension, RV64M.

Patch 4 will implement the atomic memory instructions, RV64A, and patch
5 will add support for timing, minor, and detailed CPU models that is
missing from the first four patches.

[Fixed exception handling in floating-point instructions to conform better
to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
simulator.]
[Fixed style errors in decoder.isa.]
[Fixed some fuzz caused by modifying a previous patch.]
Signed-off by: Alec Roelke

Testing Done

Description:

~		Changeset 11649:c2a1f5ec024d
	~	Changeset 11657:f8e054c9d0d6

		riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

		Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
		extensions, which include single- and double-precision floating point
		instructions.

		Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
		and patch 2 implemented the integer multiply extension, RV64M.

		Patch 4 will implement the atomic memory instructions, RV64A, and patch
		5 will add support for timing, minor, and detailed CPU models that is
		missing from the first four patches.

~		Signed-off by: Alec Roelke
	~	[Fix exception handling in floating-point instructions to conform better
	+	to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
	+	simulator.]
	+	Signed-off by: Alec Roelke

Diff:

Revision 2 (+1051 -2)

Show changes

	src/arch/riscv/faults.hh
	src/arch/riscv/faults.cc
	src/arch/riscv/registers.hh
	src/arch/riscv/utility.hh
	src/arch/riscv/isa/bitfields.isa
	src/arch/riscv/isa/decoder.isa
	src/arch/riscv/isa/includes.isa
	src/arch/riscv/isa/operands.isa
	2 more

Description:

~		Changeset 11657:f8e054c9d0d6
	~	Changeset 11690:edbd7b2b60b4

		riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

		Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
		extensions, which include single- and double-precision floating point
		instructions.

		Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
		and patch 2 implemented the integer multiply extension, RV64M.

		Patch 4 will implement the atomic memory instructions, RV64A, and patch
		5 will add support for timing, minor, and detailed CPU models that is
		missing from the first four patches.

~		[Fix exception handling in floating-point instructions to conform better
	~	[Fixed exception handling in floating-point instructions to conform better
		to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
		simulator.]
	+	[Fixed style errors in decoder.isa.]
		Signed-off by: Alec Roelke

Diff:

Revision 3 (+1057 -1)

Show changes

	src/arch/riscv/faults.hh
	src/arch/riscv/faults.cc
	src/arch/riscv/registers.hh
	src/arch/riscv/utility.hh
	src/arch/riscv/isa/bitfields.isa
	src/arch/riscv/isa/decoder.isa
	src/arch/riscv/isa/includes.isa
	src/arch/riscv/isa/operands.isa
	2 more

Seems to work for me.

Description:

~		Changeset 11690:edbd7b2b60b4
	~	Changeset 11690:9451dd15dc90

		riscv: [Patch 3/5] Added RISCV floating point extensions RV64FD

		Third of five patches adding RISC-V to GEM5. This patch adds the RV64FD
		extensions, which include single- and double-precision floating point
		instructions.

		Patch 1 introduced RISC-V and implemented the base instruction set, RV64I
		and patch 2 implemented the integer multiply extension, RV64M.

		Patch 4 will implement the atomic memory instructions, RV64A, and patch
		5 will add support for timing, minor, and detailed CPU models that is
		missing from the first four patches.

		[Fixed exception handling in floating-point instructions to conform better
		to IEEE-754 2008 standard and behavior of the Chisel-generated RISC-V
		simulator.]
		[Fixed style errors in decoder.isa.]
	+	[Fixed some fuzz caused by modifying a previous patch.]
		Signed-off by: Alec Roelke

Diff:

Revision 4 (+1057 -1)

Show changes

	src/arch/riscv/faults.hh
	src/arch/riscv/faults.cc
	src/arch/riscv/registers.hh
	src/arch/riscv/utility.hh
	src/arch/riscv/isa/bitfields.isa
	src/arch/riscv/isa/decoder.isa
	src/arch/riscv/isa/includes.isa
	src/arch/riscv/isa/operands.isa
	2 more

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Files

Description:

Changeset 11649:c2a1f5ec024d

Changeset 11657:f8e054c9d0d6

Diff:

Description:

Changeset 11657:f8e054c9d0d6

Changeset 11690:edbd7b2b60b4

Diff:

Description:

Changeset 11690:edbd7b2b60b4

Changeset 11690:9451dd15dc90

Diff:

Status: Closed (submitted)