riscv: [Patch 5/5] Added missing support for timing CPU models

Information
Submitter:	Alec Roelke
Repository:	gem5
Branch:	default
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Description

Changeset 11692:600edba2ff50
---------------------------
riscv: [Patch 5/5] Added missing support for timing CPU models

Last of five patches adding RISC-V to GEM5. This patch adds support for
timing, minor, and detailed CPU models that was missing in the last four,
which basically consists of handling timing-mode memory accesses and
telling the minor and detailed models what a no-op instruction should
be (addi zero, zero, 0).

Patches 1-4 introduced RISC-V and implemented the base instruction set,
RV64I, and added the multiply, floating point, and atomic memory
extensions, RV64MAFD.

[Fixed compatibility with edit from patch 1.]
[Fixed compatibility with hg copy edit from patch 1.]
[Fixed some style errors in locked_mem.hh.]
Signed-off by: Alec Roelke

Testing Done

Description:

~		Changeset 11651:d87e5ddd7a2a
	~	Changeset 11659:7929ae833278

		riscv: [Patch 5/5] Added missing support for timing CPU models

		Last of five patches adding RISC-V to GEM5. This patch adds support for
		timing, minor, and detailed CPU models that was missing in the last four,
		which basically consists of handling timing-mode memory accesses and
		telling the minor and detailed models what a no-op instruction should
		be (addi zero, zero, 0).

		Patches 1-4 introduced RISC-V and implemented the base instruction set,
		RV64I, and added the multiply, floating point, and atomic memory
		extensions, RV64MAFD.

~		Signed-off by: Alec Roelke
	~	[Fixed compatibility with edit from patch 1.]
	+	Signed-off by: Alec Roelke

Diff:

Revision 2 (+92 -16)

Show changes

	build_opts/RISCV
	src/arch/riscv/isa_traits.hh
	src/arch/riscv/locked_mem.hh

Description:

~		Changeset 11659:7929ae833278
	~	Changeset 11659:7209212c989e

		riscv: [Patch 5/5] Added missing support for timing CPU models

		Last of five patches adding RISC-V to GEM5. This patch adds support for
		timing, minor, and detailed CPU models that was missing in the last four,
		which basically consists of handling timing-mode memory accesses and
		telling the minor and detailed models what a no-op instruction should
		be (addi zero, zero, 0).

		Patches 1-4 introduced RISC-V and implemented the base instruction set,
		RV64I, and added the multiply, floating point, and atomic memory
		extensions, RV64MAFD.

		[Fixed compatibility with edit from patch 1.]
	+	[Fixed compatibility with hg copy edit from patch 1.]
		Signed-off by: Alec Roelke

Diff:

Revision 3 (+145 -78)

Show changes

	build_opts/RISCV
	src/arch/riscv/isa_traits.hh
	src/arch/riscv/locked_mem.hh

Description:

~		Changeset 11659:7209212c989e
	~	Changeset 11659:da7eb5770beb

		riscv: [Patch 5/5] Added missing support for timing CPU models

		Last of five patches adding RISC-V to GEM5. This patch adds support for
		timing, minor, and detailed CPU models that was missing in the last four,
		which basically consists of handling timing-mode memory accesses and
		telling the minor and detailed models what a no-op instruction should
		be (addi zero, zero, 0).

		Patches 1-4 introduced RISC-V and implemented the base instruction set,
		RV64I, and added the multiply, floating point, and atomic memory
		extensions, RV64MAFD.

		[Fixed compatibility with edit from patch 1.]
		[Fixed compatibility with hg copy edit from patch 1.]
		Signed-off by: Alec Roelke

Diff:

Revision 4 (+94 -26)

Show changes

	build_opts/RISCV
	src/arch/riscv/isa_traits.hh
	src/arch/riscv/locked_mem.hh

Description:

~		Changeset 11659:da7eb5770beb
	~	Changeset 11692:600edba2ff50

		riscv: [Patch 5/5] Added missing support for timing CPU models

		Last of five patches adding RISC-V to GEM5. This patch adds support for
		timing, minor, and detailed CPU models that was missing in the last four,
		which basically consists of handling timing-mode memory accesses and
		telling the minor and detailed models what a no-op instruction should
		be (addi zero, zero, 0).

		Patches 1-4 introduced RISC-V and implemented the base instruction set,
		RV64I, and added the multiply, floating point, and atomic memory
		extensions, RV64MAFD.

		[Fixed compatibility with edit from patch 1.]
		[Fixed compatibility with hg copy edit from patch 1.]
	+	[Fixed some style errors in locked_mem.hh.]
		Signed-off by: Alec Roelke

Diff:

Revision 5 (+91 -24)

Show changes

	build_opts/RISCV
	src/arch/riscv/isa_traits.hh
	src/arch/riscv/locked_mem.hh

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Changeset 11651:d87e5ddd7a2a

Changeset 11659:7929ae833278

Diff:

Description:

Changeset 11659:7929ae833278

Changeset 11659:7209212c989e

Diff:

Description:

Changeset 11659:7209212c989e

Changeset 11659:da7eb5770beb

Diff:

Description:

Changeset 11659:da7eb5770beb

Changeset 11692:600edba2ff50

Diff:

Status: Closed (submitted)