riscv: [Patch 8/5] Added some regression tests to RISC-V
Review Request #3694 - Created Nov. 3, 2016 and submitted
| Information | |
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| Alec Roelke | |
| gem5 | |
| default | |
| Reviewers | |
| Default | |
Changeset 11723:ea40d2a41efb --------------------------- riscv: [Patch 8/5] Added some regression tests to RISC-V This patch is the eighth patch in a series adding RISC-V to gem5, and third of the bonus patches to the original series of five. It adds some regression tests to RISC-V. Regression tests included: - se/00.hello - se/02.insttest (split into several binaries which are not included due to large size) The tests added to 00.insttest will need to be build manually; to facilitate this, a Makefile is included. The required toolchain and compiler (riscv64-unknown-elf-gcc) can be built from the riscv-tools GitHub repository at https://github.com/riscv/riscv-tools. Note that because EBREAK only makes sense when gdb is running or while in FS mode, it is not included in the linux-rv64i insttest. ERET is not included because it does not make sense in SE mode and, in fact, causes a panic by design. Note also that not every system call is tested in linux-rv64i; of the ones defined in linux/process.hh, some have been given numbers but not definitions for the toolchain, or are merely stubs that always return 0. Of the ones that do work properly, only a subset are tested due to similar functionality. [Added directories for o3-timing tests that don't work.] Signed-off by: Alec Roelke
Not all of the tests included here will run in the O3 model. linux-rv64i and linux-rv64a both crash with this error when run:
build/RISCV/mem/page_table.cc:187: Fault PageTableBase::translate(RequestPtr): Assertion `pageAlign(req->getVaddr() + req->getSize() - 1) == pageAlign(req->getVaddr())' failed.
And linux-rv64d crashes with this error:
build/RISCV/mem/cache/cache.cc:162: void Cache::satisfyRequest(PacketPtr, CacheBlk*, bool, bool): Assertion `pkt->getOffset(blkSize) + pkt->getSize() <= blkSize' failed.
I had previously encountered the rv64d error with a pair of lr/sc instructions when creating the LR/SC patch (#3693), and apparently it is caused by an issue with the O3 model and performing a load or store that crosses a cache line. Is the other error caused by this as well?
Ship It!
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Revision 2 (+73831) |
