Review Board 2.0.15


sparc: fix bugs caused by cd7f3a1dbf55

Review Request #3806 - Created Feb. 3, 2017 and submitted

Information
Brandon Potter
gem5
default
3804
Reviewers
Default
ali, gblack, stever
Changeset 11803:0ab0146d777a
---------------------------
sparc: fix bugs caused by cd7f3a1dbf55

Turns out that SPARC SE mode relied on M5_pid being "0" in
all cases. The entries in the SPARC TLBs are accessed with
M5_pid as their context. This is buggy in the sense that it
will never work with more than one process or any
initialization that doesn't have the M5_pid value passed in
as "0".

cd7f3a1dbf55 broke the SPARC build because it deletes M5_pid
and uses a _pid with a default of "100" instead. This caused
the SPARC TLB to never return any valid lookups for any
request; the program never moved past the first instruction
with SPARC SE in the regression tester.

The solution proposed in this changeset is to initialize
the address space identification register with the PID value
that is passed into the process class as a parameter from
Python. This should return the correct responses from the TLB
since the insertions and lookups into the page table will be
using the same PID.

Furthermore, there are corner cases in the code which elevate
privileges and revert to using context "0" as the context in
the TLB. I believe that these are related to kernel level
traps and hypervisor privilege escalations, but I'm not
completely sure. I've tried to address the corner cases
properly, but it would be beneficial to have someone who is
familiar with the SPARC architecture to take a look at this
fix.

util/regress all

Issue Summary

3 0 3 0
Description From Last Updated Status
Review request changed
Updated (Feb. 17, 2017, 9:08 a.m.)

Status: Closed (submitted)