Review Board 2.0.15


sim: expand AuxVector class

Review Request #3835 - Created Feb. 23, 2017 and discarded

Information
Brandon Potter
gem5
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Reviewers
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Changeset 11891:11b2a627263e
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sim: expand AuxVector class

The AuxVector class is responsible for holding Process data (in SE Mode
of course). The data that it holds is normally setup by an OS kernel in
the process address space. The purpose behind doing this is to pass in
information that the process will need for various reasons. (Check out
the enum in the header file for an idea of what the AuxVector holds.)

The AuxVector struct was changed into a class and encapsulation methods
were added to protect access to the member variables.

The host ISA may have a different endianness than the simulated ISA.
Since data is passed between the process address space and the
simulator for auxiliary vectors, we need to worry about maintaining
endianness for the right context.

   
Review request changed
Updated (Feb. 19, 2018, 11:38 a.m.)

Status: Discarded