Review Board 2.0.15


O3CPU: Fix a bug where stores in the cpu where never marked as split.

Review Request #54 - Created July 9, 2010 and submitted

Information
Timothy Jones
gem5
Reviewers
Default 
O3CPU: Fix a bug where stores in the cpu where never marked as split.

   

  


 


 

  

  









  
 


  

 
















 



 

  


 


  



   

   
Gabe Black

   
Posted  (July 21, 2010, 5:26 p.m.)


  


  


  

   



  

   

   
    
    
   


  




   







    

     
     

      

       
        

         
          src/cpu/o3/lsq_unit.hh
          

           (Diff revision 1)

          
         
        

       
       
        
 


        
 


       
      

     

    

    


     
Is it possible for sreqLow to be non-null and TheISA::HasUnalignedMemAcc -not- to be true? In that instance, wouldn't this still be a split access? Or does the code not shown in this diff make that not work?

If this is just to make it more obvious what sort of condition your checking for a comment would be better, or if it's a sanity check sort of thing an assert.




  

   

   
    
    

   
  1. 
    
    
     
    
      
     
    
     
    This case should never happen.  In BaseDynInst<Impl>::read and BaseDynInst<Impl>::write, sreqLow and sreqHigh get set to NULL.  They are only set non-null when a request is split in two, which can only happen if TheISA::HasUnalignedMemAcc is true (and the access crosses a cache line boundary).  I'll add a comment into the code to clarify what's happening.
    
    
    
   
    2.