Review Board 2.0.15


All Review Requests

Summary Submitter Posted Last Updated
Adding a cpu model named simpleEdgeCPU into M5
pengfeidaxia
April 28th, 2010, 5:58 p.m.
ISA description files for TRIPS ISA
pengfeidaxia
April 28th, 2010, 6:29 p.m.
Make TRIPS binaries available
pengfeidaxia
April 28th, 2010, 6:37 p.m.
Adding some new options to support TRIPS ISA
pengfeidaxia
April 28th, 2010, 5:39 p.m.
eventq: add a version of insert that takes a hint
nate
April 18th, 2010, 10:32 p.m.
eventq: add classes for Clock, ClockTicker, and PeriodicEvent
nate
April 18th, 2010, 10:32 p.m.
eventq: Add a small cache to speed up insertions
nate
April 18th, 2010, 10:32 p.m.
ruby: get rid of Vector and use STL
nate
June 2nd, 2010, 3:49 p.m.
ruby: get rid of PrioHeap and use STL
nate
June 2nd, 2010, 3:55 p.m.
ruby: get rid of RefCnt and Allocator stuff use base/refcnt.hh
nate
June 2nd, 2010, 3:43 p.m.
ruby: get rid of the Map class
nate
June 2nd, 2010, 3:54 p.m.
NetworkMessage copy constructor fix. Unless I hear otherwise, I will check it in, in a couple of days.
tushar
July 6th, 2010, 8:51 a.m.
garnet: Added topology print function to Garnet printStats. Unless I hear otherwise, I will check it in, in a couple of days.
tushar
July 6th, 2010, 10:31 a.m.
ARM: Implement majority of instructions and some initial full-system support
ali
April 29th, 2010, 3:26 p.m.
Stats: Allow backing up and restoring of stats which is needed for SMARTS
tmjones
July 9th, 2010, 6:21 p.m.
Cache: Provide a function to mark caches as ready from python.
tmjones
July 9th, 2010, 6:15 p.m.
CPU: Add functions to get the number of executed instructions and set the
tmjones
July 9th, 2010, 6:13 p.m.
Fix x86 XCHG macro-op to use locked micro-ops for all memory accesses
tushar
July 20th, 2010, 5:03 p.m.
O3CPU: Fix a bug where stores in the cpu where never marked as split.
tmjones
July 9th, 2010, 6:19 p.m.
Syscall: Don't close the simulator's standard file descriptors.
tmjones
July 9th, 2010, 6:14 p.m.
Power: Provide a utility function to copy registers from one thread context
tmjones
July 9th, 2010, 5:52 p.m.
Power: The condition register should be set or cleared upon a system call
tmjones
July 21st, 2010, 12:25 p.m.
LSQ Unit: After deleting part of a split request, set it to NULL so that it
tmjones
July 16th, 2010, 6:32 p.m.
O3CPU: O3's tick event gets squashed when it is switched out. When repeatedly
tmjones
July 9th, 2010, 6:12 p.m.
Port: Only indicate that a SimpleTimingPort is drained if its send event is
tmjones
July 9th, 2010, 6:20 p.m.
[Discarded] SIMPLE TIMING: when a request is NO_ACCESS (x86 CDA microinstruction), TimingSimpleCPU::completeDataAccess must still complete
jthestness
July 27th, 2010, 3:59 p.m.
Sim: Add functionality to the simulation scripts to allow running with
tmjones
July 9th, 2010, 6:21 p.m.
eventq: Add some statistics to the event queue.
nate
April 18th, 2010, 10:32 p.m.
ThreadContext suspension / activation in O3 SMT - nanosleep syscall
ilkos
July 28th, 2010, 10:11 p.m.
sim: fold StartupCallback into SimObject
stever
June 27th, 2010, 9:24 p.m.
[Discarded] ruby: Resurrected Ruby's deterministic tests
beckmann
August 11th, 2010, 9:39 a.m.
[Discarded] imported patch brad/uncacheable_debug
beckmann
August 5th, 2010, 9:18 p.m.
M5 utility: Touch all pages in readfile buffer
jthestness
August 9th, 2010, 10:16 a.m.
TimingCPU: REPOST: Request::NO_ACCESS bypass in completeDataAccess
jthestness
July 28th, 2010, 3:54 p.m.
sim: clean up child handling
stever
July 29th, 2010, 9:44 p.m.
sim: fold checkpoint restore code into instantiate()
stever
July 29th, 2010, 9:46 p.m.
sim: fail on implicit creation of orphans via ports
stever
July 29th, 2010, 9:35 p.m.
configs: clean up checkpoint code in Simulation.py
stever
July 29th, 2010, 9:45 p.m.
bus: clean up default responder code.
stever
July 29th, 2010, 9:35 p.m.
sim: make Python Root object a singleton
stever
June 27th, 2010, 9:28 p.m.
sim: revamp unserialization procedure
stever
July 29th, 2010, 9:46 p.m.
sim: move iterating over SimObjects into Python.
stever
June 27th, 2010, 9:30 p.m.
MEM: Make CLREX a first class request operation and clear locks in caches when it in received
ali
August 13th, 2010, 9:59 a.m.
ARM: BX only conditional within at IT block
ali
August 13th, 2010, 9:53 a.m.
ARM: Add configuration for Linux/Full System
ali
August 13th, 2010, 9:41 a.m.
ARM: Change how the AMBA device ID checking is done to make it more generic
ali
August 13th, 2010, 9:45 a.m.
ARM: Implement DSB, DMB, ISB
ali
August 13th, 2010, 9:55 a.m.
ARM: Implement CLREX
ali
August 13th, 2010, 9:53 a.m.
ARM: For non-cachable accesses set the UNCACHABLE flag
ali
August 13th, 2010, 9:57 a.m.
ARM: Exclusive accessse must be double word aligned
ali
August 13th, 2010, 9:49 a.m.
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