|
|
[Discarded] Changes to the gem5 memory-system (release-0.1)
|
ahansson
|
July 15th, 2011, 9:03 a.m.
|
|
|
|
[Discarded] Changes to the gem5 memory-system (release-0.2)
|
ahansson
|
August 5th, 2011, 10:13 a.m.
|
|
|
|
[Submitted] SPARC: Fixing a minor copy-paste bug using the wrong variable
|
ahansson
|
November 24th, 2011, 10:04 a.m.
|
|
|
|
[Discarded] MEM: Add the port proxies to the source tree
|
ahansson
|
November 28th, 2011, 10:14 a.m.
|
|
|
|
[Discarded] MEM: TranslatingPorts are replaced with SETranslatingProxys
|
ahansson
|
November 28th, 2011, 10:16 a.m.
|
|
|
|
[Discarded] MEM: Changes for SETranslatingProxy integration into Ruby
|
ahansson
|
November 28th, 2011, 10:19 a.m.
|
|
|
|
[Discarded] MEM: VirtualPorts are replaced with FSTranslatingProxys
|
ahansson
|
November 28th, 2011, 10:20 a.m.
|
|
|
|
[Discarded] MEM: FunctionalPorts are replaced with PortProxys
|
ahansson
|
November 28th, 2011, 10:22 a.m.
|
|
|
|
[Submitted] MAC: Make gem5 compile and run on MacOSX 10.7.2
|
ahansson
|
December 19th, 2011, 5:50 a.m.
|
|
|
|
[Submitted] SWIG: Make gem5 compile and link with swig 2.0.4
|
ahansson
|
December 19th, 2011, 5:51 a.m.
|
|
|
|
[Submitted] MEM: Add the system port as a central access point
|
ahansson
|
December 19th, 2011, 5:52 a.m.
|
|
|
|
[Submitted] MEM: Add port proxies instead of non-structural ports
|
ahansson
|
December 19th, 2011, 5:53 a.m.
|
|
|
|
[Submitted] CPU: Moving towards a more general port across CPU models
|
ahansson
|
December 19th, 2011, 5:54 a.m.
|
|
|
|
[Submitted] MEM: Simplify ports by removing EventManager
|
ahansson
|
December 19th, 2011, 5:55 a.m.
|
|
|
|
[Submitted] MEM: Remove the notion of the default port
|
ahansson
|
December 19th, 2011, 5:56 a.m.
|
|
|
|
[Submitted] MEM: Remove Port removeConn and MemObject deletePortRefs
|
ahansson
|
December 19th, 2011, 5:57 a.m.
|
|
|
|
[Submitted] MEM: Separate queries for snooping and address ranges
|
ahansson
|
December 19th, 2011, 5:58 a.m.
|
|
|
|
[Submitted] MEM: Remove the functional ports from the memory system
|
ahansson
|
December 19th, 2011, 6 a.m.
|
|
|
|
[Submitted] MEM: Make the bus bridge unidirectional and fixed address range
|
ahansson
|
December 23rd, 2011, 1:32 a.m.
|
|
|
|
[Submitted] MEM: Removing the default port peer from Python ports
|
ahansson
|
December 23rd, 2011, 1:36 a.m.
|
|
|
|
[Submitted] MEM: Make the bus default port yet another port
|
ahansson
|
December 23rd, 2011, 1:38 a.m.
|
|
|
|
[Submitted] MEM: Differentiate functional cache accesses from CPU and memory
|
ahansson
|
January 5th, 2012, 5:17 a.m.
|
|
|
|
[Submitted] Ruby: Change the access permissions for MOESI hammer
|
ahansson
|
January 10th, 2012, 9:18 a.m.
|
|
|
|
[Submitted] MEM: Remove onRetryList from BusPort and rely on retryList
|
ahansson
|
January 18th, 2012, 2:29 a.m.
|
|
|
|
[Submitted] MEM: Introduce the master/slave port roles in the Python classes
|
ahansson
|
January 18th, 2012, 2:31 a.m.
|
|
|
|
[Submitted] MEM: Pass the ports from Python to C++ using the Swig params
|
ahansson
|
January 18th, 2012, 2:32 a.m.
|
|
|
|
[Submitted] MEM: Remove the otherPort from the cache ports
|
ahansson
|
January 18th, 2012, 2:33 a.m.
|
|
|
|
[Submitted] MEM: Explicit ports and Python binding on CopyEngine
|
ahansson
|
January 18th, 2012, 2:34 a.m.
|
|
|
|
[Submitted] MEM: Make the RubyPort physMemPort a PioPort instead of M5Port
|
ahansson
|
January 18th, 2012, 2:35 a.m.
|
|
|
|
[Discarded] [mq]: fix_broken_fs_script.patch
|
ahansson
|
January 24th, 2012, 5:03 a.m.
|
|
|
|
[Submitted] MEM: Fix fs.py by specifying the range size rather than end
|
ahansson
|
January 24th, 2012, 5:08 a.m.
|
|
|
|
[Submitted] ns_gige: Fix a missing curly brace in if-statement
|
ahansson
|
January 24th, 2012, 9:11 a.m.
|
|
|
|
[Submitted] Ruby: Connect system port in Ruby network test
|
ahansson
|
January 27th, 2012, 3:57 a.m.
|
|
|
|
[Submitted] Thread: Use inherited baseCpu rather than cpu in SimpleThread
|
ahansson
|
January 27th, 2012, 5:02 a.m.
|
|
|
|
[Submitted] MEM: Clean-up of Functional/Virtual/TranslatingPort remnants
|
ahansson
|
January 29th, 2012, 10:49 a.m.
|
|
|
|
[Submitted] Regression: Update the regress script after SE/FS merge
|
ahansson
|
February 1st, 2012, 5:51 a.m.
|
|
|
|
[Submitted] MEM: Fatal when no port can be found for an address
|
ahansson
|
February 12th, 2012, 10:22 a.m.
|
|
|
|
[Submitted] Script: Fix the scripts that use the num_cpus cache parameter
|
ahansson
|
February 13th, 2012, 2:38 a.m.
|
|
|
|
[Submitted] MEM: Fix master/slave ports in Ruby and non-regression scripts
|
ahansson
|
February 13th, 2012, 11:05 a.m.
|
|
|
|
[Submitted] CPU: Round-two unifying instr/data CPU ports across models
|
ahansson
|
February 14th, 2012, 10:34 a.m.
|
|
|
|
[Submitted] MEM: Move port creation to the memory object(s) construction
|
ahansson
|
February 14th, 2012, 10:39 a.m.
|
|
|
|
[Submitted] MEM: Make port proxies use references rather than pointers
|
ahansson
|
February 15th, 2012, 5:56 a.m.
|
|
|
|
[Submitted] MEM: Move all read/write blob functions from Port to PortProxy
|
ahansson
|
February 15th, 2012, 5:58 a.m.
|
|
|
|
[Submitted] Ruby: Simplify tester ports by not using SimpleTimingPort
|
ahansson
|
February 16th, 2012, 10:45 a.m.
|
|
|
|
[Submitted] MEM: Prepare mport for master/slave split
|
ahansson
|
February 20th, 2012, 2:55 a.m.
|
|
|
|
[Submitted] MEM: Simplify cache ports preparing for master/slave split
|
ahansson
|
February 21st, 2012, 3:21 a.m.
|
|
|
|
[Submitted] MEM: Make all the port proxy members const
|
ahansson
|
February 24th, 2012, 12:55 a.m.
|
|
|
|
[Discarded] CPU: Fix switching in of x86 CPU with interrupt and TLB ports
|
ahansson
|
February 24th, 2012, 10:32 a.m.
|
|
|
|
[Submitted] MEM: Split SimpleTimingPort into PacketQueue and ports
|
ahansson
|
February 27th, 2012, 2:29 a.m.
|
|
|
|
[Submitted] SWIG: Ensure ptrdiff_t is a known type in gcc >= 4.6.1
|
ahansson
|
February 28th, 2012, 4:53 a.m.
|
|
