diff -r 02d43b211cbc -r 56b97d79e207 src/mem/cache/base.hh --- a/src/mem/cache/base.hh Wed Jan 18 10:33:41 2012 +0000 +++ b/src/mem/cache/base.hh Wed Jan 18 10:34:35 2012 +0000 @@ -105,7 +105,7 @@ CachePort(const std::string &_name, BaseCache *_cache, const std::string &_label); - virtual void recvRangeChange() const; + virtual void recvRangeChange() const { } virtual unsigned deviceBlockSize() const; @@ -117,16 +117,12 @@ const std::string label; public: - void setOtherPort(CachePort *_otherPort) { otherPort = _otherPort; } - void setBlocked(); void clearBlocked(); bool checkFunctional(PacketPtr pkt); - CachePort *otherPort; - bool blocked; bool mustSendRetry; diff -r 02d43b211cbc -r 56b97d79e207 src/mem/cache/base.cc --- a/src/mem/cache/base.cc Wed Jan 18 10:33:41 2012 +0000 +++ b/src/mem/cache/base.cc Wed Jan 18 10:34:35 2012 +0000 @@ -44,8 +44,7 @@ BaseCache::CachePort::CachePort(const std::string &_name, BaseCache *_cache, const std::string &_label) : SimpleTimingPort(_name, _cache), cache(_cache), - label(_label), otherPort(NULL), - blocked(false), mustSendRetry(false) + label(_label), blocked(false), mustSendRetry(false) { } @@ -69,13 +68,6 @@ { } -void -BaseCache::CachePort::recvRangeChange() const -{ - otherPort->sendRangeChange(); -} - - bool BaseCache::CachePort::checkFunctional(PacketPtr pkt) { diff -r 02d43b211cbc -r 56b97d79e207 src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Wed Jan 18 10:33:41 2012 +0000 +++ b/src/mem/cache/cache_impl.hh Wed Jan 18 10:34:35 2012 +0000 @@ -77,8 +77,6 @@ "CpuSidePort"); memSidePort = new MemSidePort(p->name + "-mem_side_port", this, "MemSidePort"); - cpuSidePort->setOtherPort(memSidePort); - memSidePort->setOtherPort(cpuSidePort); tags->setCache(this); if (prefetcher)