diff -r a4c8292df21d -r 10a06bd36839 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Sat Jan 28 22:46:39 2012 -0600
+++ b/src/cpu/o3/commit_impl.hh	Sat Jan 28 22:46:41 2012 -0600
@@ -549,7 +549,8 @@
     toIEW->commitInfo[tid].robSquashing = true;
 
     toIEW->commitInfo[tid].mispredictInst = NULL;
-    toIEW->commitInfo[tid].squashInst = NULL;
+    toIEW->commitInfo[tid].squashInst =
+                                    rob->getSquashInst(tid, squashed_inst);
 
     toIEW->commitInfo[tid].pc = pc[tid];
 }
@@ -855,7 +856,8 @@
                 fromIEW->mispredictInst[tid];
             toIEW->commitInfo[tid].branchTaken =
                 fromIEW->branchTaken[tid];
-            toIEW->commitInfo[tid].squashInst = NULL;
+            toIEW->commitInfo[tid].squashInst =
+                                    rob->getSquashInst(tid, squashed_inst);
 
             toIEW->commitInfo[tid].pc = fromIEW->pc[tid];
 
diff -r a4c8292df21d -r 10a06bd36839 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Sat Jan 28 22:46:39 2012 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Sat Jan 28 22:46:41 2012 -0600
@@ -1185,8 +1185,12 @@
         // StaticInst from the rom, the current macroop, or what's already
         // in the predecoder.
         bool needMem = !inRom && !curMacroop && !predecoder.extMachInstReady();
+        fetchAddr = (thisPC.instAddr() + pcOffset) & BaseCPU::PCMask;
+        Addr block_PC = icacheBlockAlignPC(fetchAddr);
 
         if (needMem) {
+            if (!cacheDataValid[tid] || block_PC != cacheDataPC[tid]) break;
+
             if (blkOffset >= numInsts) {
                 // We need to process more memory, but we've run out of the
                 // current block.
diff -r a4c8292df21d -r 10a06bd36839 src/cpu/o3/rob.hh
--- a/src/cpu/o3/rob.hh	Sat Jan 28 22:46:39 2012 -0600
+++ b/src/cpu/o3/rob.hh	Sat Jan 28 22:46:41 2012 -0600
@@ -122,6 +122,11 @@
      */
     DynInstPtr readHeadInst(ThreadID tid);
 
+    /** Returns a pointer to the instruction with the given sequence if it is
+     *  in the ROB.
+     */
+    DynInstPtr getSquashInst(ThreadID tid, InstSeqNum squash_inst);
+
     /** Returns pointer to the tail instruction within the ROB.  There is
      *  no guarantee as to the return value if the ROB is empty.
      *  @retval Pointer to the DynInst that is at the tail of the ROB.
diff -r a4c8292df21d -r 10a06bd36839 src/cpu/o3/rob_impl.hh
--- a/src/cpu/o3/rob_impl.hh	Sat Jan 28 22:46:39 2012 -0600
+++ b/src/cpu/o3/rob_impl.hh	Sat Jan 28 22:46:41 2012 -0600
@@ -545,3 +545,15 @@
         .desc("The number of ROB writes");
 }
 
+template <class Impl>
+typename Impl::DynInstPtr
+ROB<Impl>::getSquashInst(ThreadID tid, InstSeqNum squash_inst)
+{
+    for (InstIt it = instList[tid].begin(); it != instList[tid].end(); it++)
+    {
+        if ((*it)->seqNum == squash_inst) {
+            return *it;
+        }
+    }
+    return NULL;
+}