diff -r 73116cbeacba -r 7b7e329a6acf src/arch/arm/isa.hh
--- a/src/arch/arm/isa.hh	Thu Jan 26 16:44:43 2012 -0500
+++ b/src/arch/arm/isa.hh	Fri Jan 27 03:54:56 2012 -0500
@@ -127,7 +127,7 @@
                   case MODE_UNDEFINED:
                     return INTREG_UND(reg);
                   default:
-                    panic("Flattening into an unknown mode.\n");
+                    panic("Flattening into an unknown mode %i\n", mode);
                 }
             }
         }
@@ -200,6 +200,15 @@
 
             clear();
         }
+
+        void reset(std::string core_name, ThreadID num_threads,
+                   unsigned num_vpes, BaseCPU *_cpu)
+        { clear(); }
+
+
+        void expandForMultithreading(ThreadID num_threads, unsigned num_vpes)
+        { }
+
     };
 }
 
diff -r 73116cbeacba -r 7b7e329a6acf src/arch/arm/mt.hh
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/src/arch/arm/mt.hh	Fri Jan 27 03:54:56 2012 -0500
@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2009 The Regents of The University of Michigan
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Korey Sewell
+ *
+ */
+
+#ifndef __ARCH_ARM_MT_HH__
+#define __ARCH_ARM_MT_HH__
+
+/**
+ * @file
+ *
+ * ISA-specific helper functions for multithreaded execution.
+ */
+
+#include <iostream>
+
+#include "arch/isa_traits.hh"
+#include "base/bitfield.hh"
+#include "base/misc.hh"
+#include "base/trace.hh"
+using namespace std;
+
+namespace ArmISA
+{
+
+template <class TC>
+inline unsigned
+getVirtProcNum(TC *tc)
+{
+    fatal("ARM is not setup for multithreaded ISA extensions");
+    return 0;
+}
+
+
+template <class TC>
+inline unsigned
+getTargetThread(TC *tc)
+{
+    fatal("ARM is not setup for multithreaded ISA extensions");
+    return 0;
+}
+
+}//namespace ArmISA
+
+#endif
diff -r 73116cbeacba -r 7b7e329a6acf src/cpu/inorder/inorder_dyn_inst.hh
--- a/src/cpu/inorder/inorder_dyn_inst.hh	Thu Jan 26 16:44:43 2012 -0500
+++ b/src/cpu/inorder/inorder_dyn_inst.hh	Fri Jan 27 03:54:56 2012 -0500
@@ -208,6 +208,9 @@
     /** How many source registers are ready. */
     unsigned readyRegs;
 
+    /** Did this instruction execute, or is it predicated false */
+    bool predicate;
+
     enum ResultType {
         None,
         Integer,
@@ -557,6 +560,20 @@
     // BRANCH PREDICTION
     //
     ////////////////////////////////////////////////////////////
+    bool readPredicate()
+    {
+        return predicate;
+    }
+
+    void setPredicate(bool val)
+    {
+        predicate = val;
+
+        if (traceData) {
+            traceData->setPredicate(val);
+        }
+    }
+
     /** Set the predicted target of this current instruction. */
     void setPredTarg(const TheISA::PCState &predictedPC)
     { predPC = predictedPC; }