diff -r bccdfbe0c933 -r c696d9974184 src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/arm/isa.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -559,7 +559,8 @@
                       panic("Security Extensions not implemented!");
               }
               warn("Translating via MISCREG in atomic mode! Fix Me!\n");
-              req->setVirt(0, val, 1, flags, tc->pcState().pc());
+              req->setVirt(0, val, 1, flags, tc->pcState().pc(),
+                      Request::funcReqId);
               fault = tc->getDTBPtr()->translateAtomic(req, tc, mode);
               if (fault == NoFault) {
                   miscRegs[MISCREG_PAR] =
diff -r bccdfbe0c933 -r c696d9974184 src/arch/arm/table_walker.hh
--- a/src/arch/arm/table_walker.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/arm/table_walker.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -341,6 +341,9 @@
     /** If a timing translation is currently in progress */
     bool pending;
 
+    /** Request id for requests generated by this walker */
+    uint32_t reqId;
+
   public:
     typedef ArmTableWalkerParams Params;
     TableWalker(const Params *p);
diff -r bccdfbe0c933 -r c696d9974184 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/arm/table_walker.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -52,6 +52,7 @@
 
 TableWalker::TableWalker(const Params *p)
     : MemObject(p), port(NULL), tlb(NULL), currState(NULL), pending(false),
+      reqId(p->sys->getReqId(name())),
       doL1DescEvent(this), doL2DescEvent(this), doProcessEvent(this)
 {
     sctlr = 0;
@@ -62,7 +63,6 @@
     ;
 }
 
-
 unsigned int
 TableWalker::drain(Event *de)
 {
@@ -239,7 +239,7 @@
         doL1Descriptor();
         f = currState->fault;
     } else {
-        RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag);
+        RequestPtr req = new Request(l1desc_addr, sizeof(uint32_t), flag, reqId);
         PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
         pkt->dataStatic((uint8_t*)&currState->l1Desc.data);
         port->sendFunctional(pkt);
@@ -583,7 +583,7 @@
                     currState->tc->getCpuPtr()->ticks(1));
             doL2Descriptor();
         } else {
-            RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0);
+            RequestPtr req = new Request(l2desc_addr, sizeof(uint32_t), 0, reqId);
             PacketPtr pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
             pkt->dataStatic((uint8_t*)&currState->l2Desc.data);
             port->sendFunctional(pkt);
diff -r bccdfbe0c933 -r c696d9974184 src/arch/x86/intmessage.hh
--- a/src/arch/x86/intmessage.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/x86/intmessage.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -80,7 +80,8 @@
     prepIntRequest(const uint8_t id, Addr offset, Addr size)
     {
         RequestPtr req = new Request(x86InterruptAddress(id, offset),
-                                     size, Request::UNCACHEABLE);
+                                     size, Request::UNCACHEABLE,
+                                     Request::intReqId);
         PacketPtr pkt = new Packet(req, MemCmd::MessageReq, Packet::Broadcast);
         pkt->allocate();
         return pkt;
diff -r bccdfbe0c933 -r c696d9974184 src/arch/x86/pagetable_walker.hh
--- a/src/arch/x86/pagetable_walker.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/x86/pagetable_walker.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -50,6 +50,7 @@
 #include "mem/packet.hh"
 #include "params/X86PagetableWalker.hh"
 #include "sim/faults.hh"
+#include "sim/system.hh"
 
 class ThreadContext;
 
@@ -67,7 +68,7 @@
             {}
 
           protected:
-            Walker * walker;
+            Walker *walker;
 
             bool recvTiming(PacketPtr pkt);
             Tick recvAtomic(PacketPtr pkt);
@@ -97,7 +98,7 @@
             };
 
           protected:
-            Walker * walker;
+            Walker *walker;
             ThreadContext *tc;
             RequestPtr req;
             State state;
@@ -115,7 +116,6 @@
             bool timing;
             bool retrying;
             bool started;
-
           public:
             WalkerState(Walker * _walker, BaseTLB::Translation *_translation,
                     RequestPtr _req, bool _isFunctional = false) :
@@ -172,6 +172,7 @@
         // The TLB we're supposed to load.
         TLB * tlb;
         System * sys;
+        uint32_t reqId;
 
         // Functions for dealing with packets.
         bool recvTiming(PacketPtr pkt);
@@ -187,9 +188,16 @@
 
         typedef X86PagetableWalkerParams Params;
 
+        const Params *
+        params() const
+        {
+            return dynamic_cast<const Params *>(_params);
+        }
+
         Walker(const Params *params) :
             MemObject(params), port(name() + ".port", this),
-            funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system)
+            funcState(this, NULL, NULL, true), tlb(NULL), sys(params->system),
+            reqId(sys->getReqId(name()))
         {
         }
     };
diff -r bccdfbe0c933 -r c696d9974184 src/arch/x86/pagetable_walker.cc
--- a/src/arch/x86/pagetable_walker.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/arch/x86/pagetable_walker.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -499,7 +499,7 @@
         Request::Flags flags = oldRead->req->getFlags();
         flags.set(Request::UNCACHEABLE, uncacheable);
         RequestPtr request =
-            new Request(nextRead, oldRead->getSize(), flags);
+            new Request(nextRead, oldRead->getSize(), flags, walker->reqId);
         read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
         read->allocate();
         // If we need to write, adjust the read packet to write the modified
@@ -569,7 +569,7 @@
     Request::Flags flags = Request::PHYSICAL;
     if (cr3.pcd)
         flags.set(Request::UNCACHEABLE);
-    RequestPtr request = new Request(topAddr, dataSize, flags);
+    RequestPtr request = new Request(topAddr, dataSize, flags, walker->reqId);
     read = new Packet(request, MemCmd::ReadReq, Packet::Broadcast);
     read->allocate();
 }
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/base.hh
--- a/src/cpu/base.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/base.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -104,6 +104,12 @@
     // therefore no setCpuId() method is provided
     int _cpuId;
 
+    /** instruction side request id that must be placed in all requests */
+    uint32_t _instReqId;
+
+    /** data side request id that must be placed in all requests */
+    uint32_t _dataReqId;
+
     /**
      * Define a base class for the CPU ports (instruction and data)
      * that is refined in the subclasses. This class handles the
@@ -144,6 +150,11 @@
     /** Reads this CPU's ID. */
     int cpuId() { return _cpuId; }
 
+    /** Reads this CPU's unique data requestor ID */
+    uint32_t dataReqId() { return _dataReqId; }
+    /** Reads this CPU's unique instruction requestor ID */
+    uint32_t instReqId() { return _instReqId; }
+
 //    Tick currentTick;
     inline Tick frequency() const { return SimClock::Frequency / clock; }
     inline Tick ticks(int numCycles) const { return clock * numCycles; }
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/base.cc
--- a/src/cpu/base.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/base.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -120,6 +120,8 @@
 
 BaseCPU::BaseCPU(Params *p)
     : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+      _instReqId(p->system->getReqId(name() + ".inst")),
+      _dataReqId(p->system->getReqId(name() + ".data")),
       interrupts(p->interrupts),
       numThreads(p->numThreads), system(p->system),
       phase(p->phase)
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/base_dyn_inst.hh
--- a/src/cpu/base_dyn_inst.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/base_dyn_inst.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -424,6 +424,9 @@
     /** Read this CPU's ID. */
     int cpuId() { return cpu->cpuId(); }
 
+    /** Read this CPU's data requestor ID */
+    uint32_t reqId() { return cpu->dataReqId(); }
+
     /** Read this context's system-wide ID **/
     int contextId() { return thread->contextId(); }
 
@@ -878,7 +881,7 @@
         sreqLow = savedSreqLow;
         sreqHigh = savedSreqHigh;
     } else {
-        req = new Request(asid, addr, size, flags, this->pc.instAddr(),
+        req = new Request(asid, addr, size, flags, reqId(), this->pc.instAddr(),
                           thread->contextId(), threadNumber);
 
         // Only split the request if the ISA supports unaligned accesses.
@@ -940,7 +943,7 @@
         sreqLow = savedSreqLow;
         sreqHigh = savedSreqHigh;
     } else {
-        req = new Request(asid, addr, size, flags, this->pc.instAddr(),
+        req = new Request(asid, addr, size, flags, reqId(), this->pc.instAddr(),
                           thread->contextId(), threadNumber);
 
         // Only split the request if the ISA supports unaligned accesses.
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/checker/cpu.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -93,6 +93,9 @@
     typedef TheISA::FloatReg FloatReg;
     typedef TheISA::FloatRegBits FloatRegBits;
     typedef TheISA::MiscReg MiscReg;
+
+    /** id attached to all issued requests */
+    uint32_t reqId;
   public:
     virtual void init();
 
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/checker/cpu.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -60,6 +60,7 @@
 void
 CheckerCPU::init()
 {
+    reqId = systemPtr->getReqId(name());
 }
 
 CheckerCPU::CheckerCPU(Params *p)
@@ -240,7 +241,7 @@
     // Need to account for a multiple access like Atomic and Timing CPUs
     while (1) {
         memReq = new Request();
-        memReq->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+        memReq->setVirt(0, addr, size, flags, reqId, thread->pcState().instAddr());
 
         // translate to physical address
         fault = dtb->translateFunctional(memReq, tc, BaseTLB::Write);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/checker/cpu_impl.hh
--- a/src/cpu/checker/cpu_impl.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/checker/cpu_impl.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -247,7 +247,7 @@
                                      fetch_PC, thread->contextId(),
                                      unverifiedInst->threadNumber);
                 memReq->setVirt(0, fetch_PC, sizeof(MachInst),
-                                Request::INST_FETCH, thread->instAddr());
+                                Request::INST_FETCH, reqId, thread->instAddr());
 
 
                 fault = itb->translateFunctional(memReq, tc, BaseTLB::Execute);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/inorder/resources/cache_unit.cc
--- a/src/cpu/inorder/resources/cache_unit.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/inorder/resources/cache_unit.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -367,6 +367,7 @@
         if (cache_req->memReq == NULL) {
             cache_req->memReq =
                 new Request(cpu->asid[tid], aligned_addr, acc_size, flags,
+                            cpu->dataReqId(),
                             inst->instAddr(),
                             cpu->readCpuId(), //@todo: use context id
                             tid);
@@ -379,6 +380,7 @@
                                             inst->split2ndAddr,
                                             acc_size, 
                                             flags, 
+                                            cpu->dataReqId(),
                                             inst->instAddr(),
                                             cpu->readCpuId(), 
                                             tid);
@@ -1070,6 +1072,7 @@
                                        inst->getMemAddr(),
                                        inst->totalSize,
                                        0,
+                                       cpu->dataReqId(),
                                        0);
 
             split_pkt = new Packet(cache_req->memReq, cache_req->pktCmd,
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/inorder/resources/fetch_unit.cc
--- a/src/cpu/inorder/resources/fetch_unit.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/inorder/resources/fetch_unit.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -159,7 +159,8 @@
     if (cache_req->memReq == NULL) {
         cache_req->memReq =
             new Request(tid, aligned_addr, acc_size, flags,
-                        inst->instAddr(), cpu->readCpuId(), tid);
+                        cpu->instReqId(), inst->instAddr(), cpu->readCpuId(),
+                        tid);
         DPRINTF(InOrderCachePort, "[sn:%i] Created memReq @%x, ->%x\n",
                 inst->seqNum, &cache_req->memReq, cache_req->memReq);
     }
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/inorder/resources/tlb_unit.hh
--- a/src/cpu/inorder/resources/tlb_unit.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/inorder/resources/tlb_unit.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -118,7 +118,9 @@
             req_size = sizeof(TheISA::MachInst);
             flags = 0;
             inst->fetchMemReq = new Request(inst->readTid(), aligned_addr,
-                                            req_size, flags, inst->instAddr(),
+                                            req_size, flags,
+                                            res->cpu->instReqId(),
+                                            inst->instAddr(),
                                             res->cpu->readCpuId(),
                                             inst->readTid());
             memReq = inst->fetchMemReq;
@@ -132,7 +134,9 @@
             }
 
             inst->dataMemReq = new Request(inst->readTid(), aligned_addr,
-                                           req_size, flags, inst->instAddr(),
+                                           req_size, flags,
+                                           res->cpu->dataReqId(),
+                                           inst->instAddr(),
                                            res->cpu->readCpuId(),
                                            inst->readTid());
             memReq = inst->dataMemReq;
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/o3/fetch_impl.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -565,7 +565,7 @@
     // Build request here.
     RequestPtr mem_req =
         new Request(tid, block_PC, cacheBlkSize, Request::INST_FETCH,
-                    pc, cpu->thread[tid]->contextId(), tid);
+                    cpu->instReqId(), pc, cpu->thread[tid]->contextId(), tid);
 
     memReq[tid] = mem_req;
 
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/simple/atomic.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -269,7 +269,7 @@
     dcache_latency = 0;
 
     while (1) {
-        req->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+        req->setVirt(0, addr, size, flags, dataReqId(), thread->pcState().instAddr());
 
         // translate to physical address
         Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Read);
@@ -357,7 +357,7 @@
     dcache_latency = 0;
 
     while(1) {
-        req->setVirt(0, addr, size, flags, thread->pcState().instAddr());
+        req->setVirt(0, addr, size, flags, dataReqId(), thread->pcState().instAddr());
 
         // translate to physical address
         Fault fault = thread->dtb->translateAtomic(req, tc, BaseTLB::Write);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/simple/base.cc
--- a/src/cpu/simple/base.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/simple/base.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -346,7 +346,8 @@
     DPRINTF(Fetch, "Fetch: PC:%08p\n", instAddr);
 
     Addr fetchPC = (instAddr & PCMask) + fetchOffset;
-    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instAddr);
+    req->setVirt(0, fetchPC, sizeof(MachInst), Request::INST_FETCH, instReqId(),
+            instAddr);
 }
 
 
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/simple/timing.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -385,7 +385,7 @@
     buildPacket(pkt1, req1, read);
     buildPacket(pkt2, req2, read);
 
-    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags());
+    req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataReqId());
     PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(),
                                Packet::Broadcast);
 
@@ -418,7 +418,7 @@
     }
 
     RequestPtr req  = new Request(asid, addr, size,
-                                  flags, pc, _cpuId, tid);
+                                  flags, dataReqId(), pc, _cpuId, tid);
 
     Addr split_addr = roundDown(addr + size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);
@@ -488,7 +488,7 @@
     }
 
     RequestPtr req = new Request(asid, addr, size,
-                                 flags, pc, _cpuId, tid);
+                                 flags, dataReqId(), pc, _cpuId, tid);
 
     Addr split_addr = roundDown(addr + size - 1, block_size);
     assert(split_addr <= addr || split_addr - addr < block_size);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/directedtest/DirectedGenerator.hh
--- a/src/cpu/testers/directedtest/DirectedGenerator.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/directedtest/DirectedGenerator.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -49,6 +49,7 @@
     
   protected:
     int m_num_cpus;
+    uint32_t reqId;
     RubyDirectedTester* m_directed_tester;
 };
 
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/directedtest/DirectedGenerator.cc
--- a/src/cpu/testers/directedtest/DirectedGenerator.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/directedtest/DirectedGenerator.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -28,9 +28,11 @@
  */
 
 #include "cpu/testers/directedtest/DirectedGenerator.hh"
+#include "sim/system.hh"
 
 DirectedGenerator::DirectedGenerator(const Params *p)
-    : SimObject(p)
+    : SimObject(p),
+      reqId(p->system->getReqId(name()))
 {
     m_num_cpus = p->num_cpus;
     m_directed_tester = NULL;
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/directedtest/InvalidateGenerator.cc
--- a/src/cpu/testers/directedtest/InvalidateGenerator.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/directedtest/InvalidateGenerator.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -58,7 +58,7 @@
     Packet::Command cmd;
 
     // For simplicity, requests are assumed to be 1 byte-sized
-    Request *req = new Request(m_address, 1, flags);
+    Request *req = new Request(m_address, 1, flags, reqId);
 
     //
     // Based on the current state, issue a load or a store
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/directedtest/RubyDirectedTester.py
--- a/src/cpu/testers/directedtest/RubyDirectedTester.py	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/directedtest/RubyDirectedTester.py	Sat Feb 04 13:16:43 2012 -0600
@@ -35,6 +35,7 @@
     type = 'DirectedGenerator'
     abstract = True
     num_cpus = Param.Int("num of cpus")
+    system = Param.System(Parent.any, "System we belong to")
 
 class SeriesRequestGenerator(DirectedGenerator):
     type = 'SeriesRequestGenerator'
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/directedtest/SeriesRequestGenerator.cc
--- a/src/cpu/testers/directedtest/SeriesRequestGenerator.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/directedtest/SeriesRequestGenerator.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -59,7 +59,7 @@
     Request::Flags flags;
 
     // For simplicity, requests are assumed to be 1 byte-sized
-    Request *req = new Request(m_address, 1, flags);
+    Request *req = new Request(m_address, 1, flags, reqId);
 
     Packet::Command cmd;
     if (m_issue_writes) {
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/memtest/MemTest.py
--- a/src/cpu/testers/memtest/MemTest.py	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/memtest/MemTest.py	Sat Feb 04 13:16:43 2012 -0600
@@ -52,3 +52,5 @@
     functional = Port("Port to the functional memory used for verification")
     suppress_func_warnings = Param.Bool(False,
         "suppress warnings when functional accesses fail.\n")
+    sys = Param.System(Parent.any, "System Parameter")
+
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/memtest/memtest.hh
--- a/src/cpu/testers/memtest/memtest.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/memtest/memtest.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -138,6 +138,9 @@
 
     bool issueDmas;
 
+    /** Request id for all generated traffic */
+    uint32_t reqId;
+
     int id;
 
     std::set<unsigned> outstandingAddrs;
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/memtest/memtest.cc
--- a/src/cpu/testers/memtest/memtest.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/memtest/memtest.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -46,6 +46,7 @@
 #include "mem/request.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "sim/system.hh"
 
 using namespace std;
 
@@ -132,6 +133,7 @@
       percentFunctional(p->percent_functional),
       percentUncacheable(p->percent_uncacheable),
       issueDmas(p->issue_dmas),
+      reqId(p->sys->getReqId(name())),
       progressInterval(p->progress_interval),
       nextProgressMessage(p->progress_interval),
       percentSourceUnaligned(p->percent_source_unaligned),
@@ -182,7 +184,7 @@
 }
 
 
-void
+    void
 MemTest::completeRequest(PacketPtr pkt)
 {
     Request *req = pkt->req;
@@ -321,11 +323,11 @@
 
     if (issueDmas) {
         paddr &= ~((1 << dma_access_size) - 1);
-        req->setPhys(paddr, 1 << dma_access_size, flags);
+        req->setPhys(paddr, 1 << dma_access_size, flags, reqId);
         req->setThreadContext(id,0);
     } else {
         paddr &= ~((1 << access_size) - 1);
-        req->setPhys(paddr, 1 << access_size, flags);
+        req->setPhys(paddr, 1 << access_size, flags, reqId);
         req->setThreadContext(id,0);
     }
     assert(req->getSize() == 1);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/networktest/NetworkTest.py
--- a/src/cpu/testers/networktest/NetworkTest.py	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/networktest/NetworkTest.py	Sat Feb 04 13:16:43 2012 -0600
@@ -28,6 +28,7 @@
 
 from MemObject import MemObject
 from m5.params import *
+from m5.proxy import *
 
 class NetworkTest(MemObject):
     type = 'NetworkTest'
@@ -41,3 +42,4 @@
     inj_rate = Param.Float(0.1, "Packet injection rate")
     precision = Param.Int(3, "Number of digits of precision after decimal point")
     test = Port("Port to the memory system to test")
+    system = Param.System(Parent.any, "System we belong to")
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/networktest/networktest.hh
--- a/src/cpu/testers/networktest/networktest.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/networktest/networktest.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -134,6 +134,8 @@
     double injRate;
     int precision;
 
+    uint32_t reqId;
+
     void completeRequest(PacketPtr pkt);
 
     void generatePkt();
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/networktest/networktest.cc
--- a/src/cpu/testers/networktest/networktest.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/networktest/networktest.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -44,6 +44,7 @@
 #include "mem/request.hh"
 #include "sim/sim_events.hh"
 #include "sim/stats.hh"
+#include "sim/system.hh"
 
 using namespace std;
 
@@ -113,7 +114,8 @@
       maxPackets(p->max_packets),
       trafficType(p->traffic_type),
       injRate(p->inj_rate),
-      precision(p->precision)
+      precision(p->precision),
+      reqId(p->system->getReqId(name()))
 {
     // set up counters
     noResponseCycles = 0;
@@ -263,17 +265,17 @@
     if (randomReqType == 0) {
         // generate packet for virtual network 0
         requestType = MemCmd::ReadReq;
-        req->setPhys(paddr, access_size, flags);
+        req->setPhys(paddr, access_size, flags, reqId);
     } else if (randomReqType == 1) {
         // generate packet for virtual network 1
         requestType = MemCmd::ReadReq;
         flags.set(Request::INST_FETCH);
-        req->setVirt(0, 0x0, access_size, flags, 0x0);
+        req->setVirt(0, 0x0, access_size, flags, 0x0, reqId);
         req->setPaddr(paddr);
     } else {  // if (randomReqType == 2)
         // generate packet for virtual network 2
         requestType = MemCmd::WriteReq;
-        req->setPhys(paddr, access_size, flags);
+        req->setPhys(paddr, access_size, flags, reqId);
     }
 
     req->setThreadContext(id,0);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/rubytest/Check.cc
--- a/src/cpu/testers/rubytest/Check.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/rubytest/Check.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -103,8 +103,8 @@
     }
 
     // Prefetches are assumed to be 0 sized
-    Request *req = new Request(m_address.getAddress(), 0, flags, curTick(),
-                               m_pc.getAddress());
+    Request *req = new Request(m_address.getAddress(), 0, flags, 0 /*fix me */, curTick(),
+            m_pc.getAddress());
     req->setThreadContext(index, 0);
 
     PacketPtr pkt = new Packet(req, cmd, port->idx);
@@ -129,7 +129,7 @@
     }
 }
 
-void
+    void
 Check::initiateFlush()
 {
 
@@ -141,8 +141,8 @@
 
     Request::Flags flags;
 
-    Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags, curTick(),
-                               m_pc.getAddress());
+    Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
+            m_tester_ptr->reqId(), curTick(), m_pc.getAddress());
 
     Packet::Command cmd;
 
@@ -176,7 +176,8 @@
     Address writeAddr(m_address.getAddress() + m_store_count);
 
     // Stores are assumed to be 1 byte-sized
-    Request *req = new Request(writeAddr.getAddress(), 1, flags, curTick(),
+    Request *req = new Request(writeAddr.getAddress(), 1, flags,
+            m_tester_ptr->reqId(), curTick(),
                                m_pc.getAddress());
 
     req->setThreadContext(index, 0);
@@ -243,7 +244,7 @@
 
     // Checks are sized depending on the number of bytes written
     Request *req = new Request(m_address.getAddress(), CHECK_SIZE, flags,
-                               curTick(), m_pc.getAddress());
+                               m_tester_ptr->reqId(), curTick(), m_pc.getAddress());
 
     req->setThreadContext(index, 0);
     PacketPtr pkt = new Packet(req, MemCmd::ReadReq, port->idx);
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/rubytest/RubyTester.hh
--- a/src/cpu/testers/rubytest/RubyTester.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/rubytest/RubyTester.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -101,6 +101,7 @@
     void print(std::ostream& out) const;
     bool getCheckFlush() { return m_check_flush; }
 
+    uint32_t reqId() { return _reqId; }
   protected:
     class CheckStartEvent : public Event
     {
@@ -117,6 +118,8 @@
 
     CheckStartEvent checkStartEvent;
 
+    uint32_t _reqId;
+
   private:
     void hitCallback(NodeID proc, SubBlock* data);
 
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/rubytest/RubyTester.cc
--- a/src/cpu/testers/rubytest/RubyTester.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/rubytest/RubyTester.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -36,9 +36,11 @@
 #include "mem/ruby/eventqueue/RubyEventQueue.hh"
 #include "mem/ruby/system/System.hh"
 #include "sim/sim_exit.hh"
+#include "sim/system.hh"
 
 RubyTester::RubyTester(const Params *p)
   : MemObject(p), checkStartEvent(this),
+    _reqId(p->system->getReqId(name())),
     m_checks_to_complete(p->checks_to_complete),
     m_deadlock_threshold(p->deadlock_threshold),
     m_wakeup_frequency(p->wakeup_frequency),
diff -r bccdfbe0c933 -r c696d9974184 src/cpu/testers/rubytest/RubyTester.py
--- a/src/cpu/testers/rubytest/RubyTester.py	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/cpu/testers/rubytest/RubyTester.py	Sat Feb 04 13:16:43 2012 -0600
@@ -37,3 +37,4 @@
     deadlock_threshold = Param.Int(50000, "how often to check for deadlock")
     wakeup_frequency = Param.Int(10, "number of cycles between wakeups")
     check_flush = Param.Bool(False, "check cache flushing")
+    system = Param.System(Parent.any, "System we belong to")
diff -r bccdfbe0c933 -r c696d9974184 src/dev/io_device.hh
--- a/src/dev/io_device.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/dev/io_device.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -104,6 +104,9 @@
      * we are currently operating in. */
     System *sys;
 
+    /** Id for all requests */
+    uint32_t reqId;
+
     /** Number of outstanding packets the dma port has. */
     int pendingCount;
 
diff -r bccdfbe0c933 -r c696d9974184 src/dev/io_device.cc
--- a/src/dev/io_device.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/dev/io_device.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -116,6 +116,7 @@
 DmaPort::DmaPort(MemObject *dev, System *s, Tick min_backoff, Tick max_backoff,
                  bool recv_snoops)
     : Port(dev->name() + "-dmaport", dev), device(dev), sys(s),
+      reqId(s->getReqId(dev->name())),
       pendingCount(0), actionInProgress(0), drainEvent(NULL),
       backoffTime(0), minBackoffDelay(min_backoff),
       maxBackoffDelay(max_backoff), inRetry(false), recvSnoops(recv_snoops),
@@ -187,7 +188,6 @@
     : PioDevice(p), dmaPort(NULL)
 { }
 
-
 unsigned int
 DmaDevice::drain(Event *de)
 {
@@ -254,7 +254,7 @@
             event ? event->scheduled() : -1 );
     for (ChunkGenerator gen(addr, size, peerBlockSize());
          !gen.done(); gen.next()) {
-            Request *req = new Request(gen.addr(), gen.size(), flag);
+            Request *req = new Request(gen.addr(), gen.size(), flag, reqId);
             PacketPtr pkt = new Packet(req, cmd, Packet::Broadcast);
 
             // Increment the data pointer on a write
diff -r bccdfbe0c933 -r c696d9974184 src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/cache/cache_impl.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -1006,7 +1006,8 @@
     writebacks[0/*pkt->req->threadId()*/]++;
 
     Request *writebackReq =
-        new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0);
+        new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0,
+                Request::wbReqId);
     PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback, -1);
     if (blk->isWritable()) {
         writeback->setSupplyExclusive();
diff -r bccdfbe0c933 -r c696d9974184 src/mem/cache/prefetch/Prefetcher.py
--- a/src/mem/cache/prefetch/Prefetcher.py	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/cache/prefetch/Prefetcher.py	Sat Feb 04 13:16:43 2012 -0600
@@ -1,5 +1,7 @@
 from m5.SimObject import SimObject
 from m5.params import *
+from m5.proxy import *
+
 class BasePrefetcher(SimObject):
     type = 'BasePrefetcher'
     abstract = True
@@ -17,6 +19,7 @@
          "Use the CPU ID to separate calculations of prefetches")
     prefetch_data_accesses_only = Param.Bool(False,
          "Only prefetch on data not on instruction accesses")
+    sys = Param.System(Parent.any, "System this device belongs to")
 
 class GHBPrefetcher(BasePrefetcher):
     type = 'GHBPrefetcher'
diff -r bccdfbe0c933 -r c696d9974184 src/mem/cache/prefetch/base.hh
--- a/src/mem/cache/prefetch/base.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/cache/prefetch/base.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -75,6 +75,12 @@
     /** Do we prefetch on only data reads, or on inst reads as well. */
     bool onlyData;
 
+    /** System we belong to */
+    System* system;
+
+    /** Request id for prefetches */
+    uint32_t reqId;
+
   public:
 
     Stats::Scalar pfIdentified;
diff -r bccdfbe0c933 -r c696d9974184 src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/cache/prefetch/base.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -42,11 +42,13 @@
 #include "mem/cache/prefetch/base.hh"
 #include "mem/cache/base.hh"
 #include "mem/request.hh"
+#include "sim/system.hh"
 
 BasePrefetcher::BasePrefetcher(const Params *p)
     : SimObject(p), size(p->prefetcher_size), pageStop(!p->prefetch_past_page),
       serialSquash(p->prefetch_serial_squash),
-      onlyData(p->prefetch_data_accesses_only)
+      onlyData(p->prefetch_data_accesses_only),
+      system(p->sys), reqId(system->getReqId(name())
 {
 }
 
@@ -230,7 +232,7 @@
             }
 
             // create a prefetch memreq
-            Request *prefetchReq = new Request(*addrIter, blkSize, 0);
+            Request *prefetchReq = new Request(*addrIter, blkSize, 0, reqId);
             PacketPtr prefetch =
                 new Packet(prefetchReq, MemCmd::HardPFReq, Packet::Broadcast);
             prefetch->allocate();
diff -r bccdfbe0c933 -r c696d9974184 src/mem/cache/tags/iic.cc
--- a/src/mem/cache/tags/iic.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/cache/tags/iic.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -369,7 +369,7 @@
                                   tag_ptr->size);
 */
             Request *writebackReq = new Request(regenerateBlkAddr(tag_ptr->tag, 0),
-                                           blkSize, 0);
+                                           blkSize, 0, Request::wbReqId);
             PacketPtr writeback = new Packet(writebackReq, MemCmd::Writeback,
                                              -1);
             writeback->allocate();
diff -r bccdfbe0c933 -r c696d9974184 src/mem/port.cc
--- a/src/mem/port.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/port.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -70,7 +70,7 @@
 
     for (ChunkGenerator gen(addr, size, peerBlockSize());
          !gen.done(); gen.next()) {
-        req.setPhys(gen.addr(), gen.size(), 0);
+        req.setPhys(gen.addr(), gen.size(), 0, Request::funcReqId);
         Packet pkt(&req, cmd, Packet::Broadcast);
         pkt.dataStatic(p);
         sendFunctional(&pkt);
@@ -106,7 +106,7 @@
 void
 Port::printAddr(Addr a)
 {
-    Request req(a, 1, 0);
+    Request req(a, 1, 0, Request::funcReqId);
     Packet pkt(&req, MemCmd::PrintReq, Packet::Broadcast);
     Packet::PrintReqState prs(std::cerr);
     pkt.senderState = &prs;
diff -r bccdfbe0c933 -r c696d9974184 src/mem/request.hh
--- a/src/mem/request.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/request.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -100,6 +100,12 @@
        (assigned a new address). */
     static const FlagsType STICKY_FLAGS = INST_FETCH;
 
+    /** Request Ids that are statically allocated */
+    static const uint32_t wbReqId = 0;
+    static const uint32_t funcReqId = 1;
+    static const uint32_t intReqId = 2;
+
+
   private:
     typedef uint8_t PrivateFlagsType;
     typedef ::Flags<PrivateFlagsType> PrivateFlags;
@@ -137,6 +143,11 @@
      */
     int _size;
 
+    /** The requestor ID which is unique in the system for all ports
+     * that are capable of issuing a transaction
+     */
+    uint32_t _rid;
+
     /** Flag structure for the request. */
     Flags _flags;
 
@@ -182,27 +193,27 @@
      * just physical address, size, flags, and timestamp (to curTick()).
      * These fields are adequate to perform a request. 
      */
-    Request(Addr paddr, int size, Flags flags)
+    Request(Addr paddr, int size, Flags flags, uint32_t rid)
     {
-        setPhys(paddr, size, flags);
+        setPhys(paddr, size, flags, rid);
     }
 
-    Request(Addr paddr, int size, Flags flags, Tick time)
+    Request(Addr paddr, int size, Flags flags, uint32_t rid, Tick time)
     {
-        setPhys(paddr, size, flags, time);
+        setPhys(paddr, size, flags, rid, time);
     }
 
-    Request(Addr paddr, int size, Flags flags, Tick time, Addr pc)
+    Request(Addr paddr, int size, Flags flags, uint32_t rid, Tick time, Addr pc)
     {
-        setPhys(paddr, size, flags, time);
+        setPhys(paddr, size, flags, rid, time);
         privateFlags.set(VALID_PC);
         _pc = pc;
     }
 
-    Request(int asid, Addr vaddr, int size, Flags flags, Addr pc,
+    Request(int asid, Addr vaddr, int size, Flags flags, uint32_t rid, Addr pc,
             int cid, ThreadID tid)
     {
-        setVirt(asid, vaddr, size, flags, pc);
+        setVirt(asid, vaddr, size, flags, rid, pc);
         setThreadContext(cid, tid);
     }
 
@@ -224,13 +235,13 @@
      * allocated Request object.
      */
     void
-    setPhys(Addr paddr, int size, Flags flags, Tick time)
+    setPhys(Addr paddr, int size, Flags flags, uint32_t rid, Tick time)
     {
         assert(size >= 0);
         _paddr = paddr;
         _size = size;
         _time = time;
-
+        _rid = rid;
         _flags.clear(~STICKY_FLAGS);
         _flags.set(flags);
         privateFlags.clear(~STICKY_PRIVATE_FLAGS);
@@ -238,9 +249,9 @@
     }
 
     void
-    setPhys(Addr paddr, int size, Flags flags)
+    setPhys(Addr paddr, int size, Flags flags, uint32_t rid)
     {
-        setPhys(paddr, size, flags, curTick());
+        setPhys(paddr, size, flags, rid, curTick());
     }
 
     /**
@@ -248,12 +259,13 @@
      * allocated Request object.
      */
     void
-    setVirt(int asid, Addr vaddr, int size, Flags flags, Addr pc)
+    setVirt(int asid, Addr vaddr, int size, Flags flags, uint32_t rid, Addr pc)
     {
         assert(size >= 0);
         _asid = asid;
         _vaddr = vaddr;
         _size = size;
+        _rid = rid;
         _pc = pc;
         _time = curTick();
 
@@ -369,6 +381,13 @@
         return _vaddr;
     }
 
+    /** Accesssor for the requestor id. */
+    uint32_t
+    reqId()
+    {
+        return _rid;
+    }
+
     /** Accessor function for asid.*/
     int
     getAsid()
diff -r bccdfbe0c933 -r c696d9974184 src/mem/ruby/recorder/CacheRecorder.cc
--- a/src/mem/ruby/recorder/CacheRecorder.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/mem/ruby/recorder/CacheRecorder.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -74,7 +74,8 @@
         TraceRecord* rec = m_records[m_records_flushed];
         m_records_flushed++;
         Request* req = new Request(rec->m_data_address,
-                                   RubySystem::getBlockSizeBytes(),0);
+                                   RubySystem::getBlockSizeBytes(),0,
+                                   Request::funcReqId);
         MemCmd::Command requestType = MemCmd::FlushReq;
         Packet *pkt = new Packet(req, requestType, -1);
 
@@ -100,16 +101,16 @@
         if (traceRecord->m_type == RubyRequestType_LD) {
             requestType = MemCmd::ReadReq;
             req->setPhys(traceRecord->m_data_address,
-                    RubySystem::getBlockSizeBytes(),0);
+                    RubySystem::getBlockSizeBytes(),0, Request::funcReqId);
         }   else if (traceRecord->m_type == RubyRequestType_IFETCH) {
             requestType = MemCmd::ReadReq;
             req->setPhys(traceRecord->m_data_address,
                     RubySystem::getBlockSizeBytes(),
-                    Request::INST_FETCH);
+                    Request::INST_FETCH, Request::funcReqId);
         }   else {
             requestType = MemCmd::WriteReq;
             req->setPhys(traceRecord->m_data_address,
-                    RubySystem::getBlockSizeBytes(),0);
+                    RubySystem::getBlockSizeBytes(),0, Request::funcReqId);
         }
 
         Packet *pkt = new Packet(req, requestType, -1);
diff -r bccdfbe0c933 -r c696d9974184 src/sim/system.hh
--- a/src/sim/system.hh	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/sim/system.hh	Sat Feb 04 13:16:43 2012 -0600
@@ -229,7 +229,35 @@
     uint32_t numWorkIds;
     std::vector<bool> activeCpus;
 
+    /** This array is a per-sytem list of all devices capable of issuing a
+     * memory system request and an associated string for each requestor id.
+     * It's used to uniquely id any requestor in the system by name for things
+     * like cache statistics.
+     */
+    std::vector<std::string> reqIds;
+
   public:
+
+    /** Request an id used to create a request object in the system. All objects
+     * that intend to issues requests into the memory system must request an id
+     * in the init() phase of startup. All requestor ids must be fixed by the
+     * regStats() phase that immediately preceeds it. This allows objects in the
+     * memory system to understand how many requestors may exist and
+     * appropriately name the bins of their per-requestor stats before the stats
+     * are finalized
+     */
+    uint32_t getReqId(std::string req_name);
+
+    /** Get the name of an object for a given request id.
+     */
+    std::string getReqName(uint32_t req_id);
+
+    /** Get the number of requestors registered in the system */
+    uint32_t maxRequestors()
+    {
+        return reqIds.size();
+    }
+
     virtual void regStats();
     /**
      * Called by pseudo_inst to track the number of work items started by this
diff -r bccdfbe0c933 -r c696d9974184 src/sim/system.cc
--- a/src/sim/system.cc	Fri Feb 03 19:41:23 2012 -0600
+++ b/src/sim/system.cc	Sat Feb 04 13:16:43 2012 -0600
@@ -271,6 +271,15 @@
 
     activeCpus.clear();
 
+    // Get the generic system  request IDs
+    uint32_t tmp_id M5_VAR_USED;
+    tmp_id = getReqId("writebacks");
+    assert(tmp_id == Request::wbReqId);
+    tmp_id = getReqId("functional");
+    assert(tmp_id == Request::funcReqId);
+    tmp_id = getReqId("interrupt");
+    assert(tmp_id == Request::intReqId);
+
     if (!FullSystem)
         return;
 
@@ -398,6 +407,37 @@
     System::printSystems();
 }
 
+uint32_t
+System::getReqId(std::string req_name)
+{
+    // requestors in switch_cpus ask for ids again after switching
+    for (int i = 0; i < reqIds.size(); i++) {
+        if (reqIds[i] == req_name) {
+            return i;
+        }
+    }
+
+    // todo: Check if stats are enabled yet
+    // I just don't know a good way to do it
+
+    if (false)
+        fatal("Can't request a reqId after regStats(). \
+                You must do so in init().\n");
+
+    reqIds.push_back(req_name);
+
+    return reqIds.size() - 1;
+}
+
+std::string
+System::getReqName(uint32_t req_id)
+{
+    if (req_id >= reqIds.size())
+        fatal("Invalid req_id passed to getReqName()\n");
+
+    return reqIds[req_id];
+}
+
 const char *System::MemoryModeStrings[3] = {"invalid", "atomic",
     "timing"};