diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/BaseCache.py --- a/src/mem/cache/BaseCache.py Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/BaseCache.py Sat Feb 04 14:26:18 2012 -0600 @@ -27,7 +27,7 @@ # Authors: Nathan Binkert from m5.params import * -from m5.proxy import Self +from m5.proxy import * from MemObject import MemObject from Prefetcher import BasePrefetcher @@ -44,7 +44,6 @@ prioritizeRequests = Param.Bool(False, "always service demand misses first") repl = Param.Repl(NULL, "replacement policy") - num_cpus = Param.Int(1, "number of cpus sharing this cache") size = Param.MemorySize("capacity in bytes") forward_snoops = Param.Bool(True, "forward snoops from mem side to cpu side") @@ -62,3 +61,4 @@ cpu_side = Port("Port on side closer to CPU") mem_side = Port("Port on side closer to MEM") addr_range = Param.AddrRange(AllMemory, "The address range for the CPU-side port") + system = Param.System(Parent.any, "System we belong to") diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/base.hh --- a/src/mem/cache/base.hh Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/base.hh Sat Feb 04 14:26:18 2012 -0600 @@ -58,6 +58,7 @@ #include "sim/eventq.hh" #include "sim/full_system.hh" #include "sim/sim_exit.hh" +#include "sim/system.hh" class MSHR; /** @@ -220,11 +221,10 @@ * Normally this is all possible memory addresses. */ Range addrRange; - /** number of cpus sharing this cache - from config file */ - int _numCpus; + public: + /** System we are currently operating in. */ + System *system; - public: - int numCpus() { return _numCpus; } // Statistics /** * @addtogroup CacheStatistics @@ -488,23 +488,10 @@ virtual bool inMissQueue(Addr addr) = 0; - void incMissCount(PacketPtr pkt, int id) + void incMissCount(PacketPtr pkt) { - - if (pkt->cmd == MemCmd::Writeback) { - assert(id == -1); - misses[pkt->cmdToIndex()][0]++; - /* same thing for writeback hits as misses - no context id - * available, meanwhile writeback hit/miss stats are not used - * in any aggregate hit/miss calculations, so just lump them all - * in bucket 0 */ - } else if (FullSystem && id == -1) { - // Device accesses have id -1 - // lump device accesses into their own bucket - misses[pkt->cmdToIndex()][_numCpus]++; - } else { - misses[pkt->cmdToIndex()][id % _numCpus]++; - } + assert(pkt->req->reqId() < system->maxRequestors()); + misses[pkt->cmdToIndex()][pkt->req->reqId()]++; if (missCount) { --missCount; @@ -512,26 +499,11 @@ exitSimLoop("A cache reached the maximum miss count"); } } - void incHitCount(PacketPtr pkt, int id) + void incHitCount(PacketPtr pkt) { + assert(pkt->req->reqId() < system->maxRequestors()); + hits[pkt->cmdToIndex()][pkt->req->reqId()]++; - /* Writeback requests don't have a context id associated with - * them, so attributing a hit to a -1 context id is obviously a - * problem. I've noticed in the stats that hits are split into - * demand and non-demand hits - neither of which include writeback - * hits, so here, I'll just put the writeback hits into bucket 0 - * since it won't mess with any other stats -hsul */ - if (pkt->cmd == MemCmd::Writeback) { - assert(id == -1); - hits[pkt->cmdToIndex()][0]++; - } else if (FullSystem && id == -1) { - // Device accesses have id -1 - // lump device accesses into their own bucket - hits[pkt->cmdToIndex()][_numCpus]++; - } else { - /* the % is necessary in case there are switch cpus */ - hits[pkt->cmdToIndex()][id % _numCpus]++; - } } }; diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/base.cc --- a/src/mem/cache/base.cc Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/base.cc Sat Feb 04 14:26:18 2012 -0600 @@ -65,7 +65,7 @@ missCount(p->max_miss_count), drainEvent(NULL), addrRange(p->addr_range), - _numCpus(p->num_cpus) + system(p->system) { } @@ -143,11 +143,14 @@ const string &cstr = cmd.toString(); hits[access_idx] - .init(FullSystem ? (_numCpus + 1) : _numCpus) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_hits") .desc("number of " + cstr + " hits") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + hits[access_idx].subname(i, system->getReqName(i)); + } } // These macros make it easier to sum the right subset of commands and @@ -163,16 +166,22 @@ demandHits .name(name() + ".demand_hits") .desc("number of demand (read+write) hits") - .flags(total) + .flags(total | nozero | nonan) ; demandHits = SUM_DEMAND(hits); + for (int i = 0; i < system->maxRequestors(); i++) { + demandHits.subname(i, system->getReqName(i)); + } overallHits .name(name() + ".overall_hits") .desc("number of overall hits") - .flags(total) + .flags(total | nozero | nonan) ; overallHits = demandHits + SUM_NON_DEMAND(hits); + for (int i = 0; i < system->maxRequestors(); i++) { + overallHits.subname(i, system->getReqName(i)); + } // Miss statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -180,26 +189,35 @@ const string &cstr = cmd.toString(); misses[access_idx] - .init(FullSystem ? (_numCpus + 1) : _numCpus) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_misses") .desc("number of " + cstr + " misses") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + misses[access_idx].subname(i, system->getReqName(i)); + } } demandMisses .name(name() + ".demand_misses") .desc("number of demand (read+write) misses") - .flags(total) + .flags(total | nozero | nonan) ; demandMisses = SUM_DEMAND(misses); + for (int i = 0; i < system->maxRequestors(); i++) { + demandMisses.subname(i, system->getReqName(i)); + } overallMisses .name(name() + ".overall_misses") .desc("number of overall misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMisses = demandMisses + SUM_NON_DEMAND(misses); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMisses.subname(i, system->getReqName(i)); + } // Miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -207,26 +225,35 @@ const string &cstr = cmd.toString(); missLatency[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_miss_latency") .desc("number of " + cstr + " miss cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + missLatency[access_idx].subname(i, system->getReqName(i)); + } } demandMissLatency .name(name() + ".demand_miss_latency") .desc("number of demand (read+write) miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; demandMissLatency = SUM_DEMAND(missLatency); + for (int i = 0; i < system->maxRequestors(); i++) { + demandMissLatency.subname(i, system->getReqName(i)); + } overallMissLatency .name(name() + ".overall_miss_latency") .desc("number of overall miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMissLatency = demandMissLatency + SUM_NON_DEMAND(missLatency); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMissLatency.subname(i, system->getReqName(i)); + } // access formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -238,23 +265,32 @@ .desc("number of " + cstr + " accesses(hits+misses)") .flags(total | nozero | nonan) ; + accesses[access_idx] = hits[access_idx] + misses[access_idx]; - accesses[access_idx] = hits[access_idx] + misses[access_idx]; + for (int i = 0; i < system->maxRequestors(); i++) { + accesses[access_idx].subname(i, system->getReqName(i)); + } } demandAccesses .name(name() + ".demand_accesses") .desc("number of demand (read+write) accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandAccesses = demandHits + demandMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + demandAccesses.subname(i, system->getReqName(i)); + } overallAccesses .name(name() + ".overall_accesses") .desc("number of overall (read+write) accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallAccesses = overallHits + overallMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + overallAccesses.subname(i, system->getReqName(i)); + } // miss rate formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -266,23 +302,32 @@ .desc("miss rate for " + cstr + " accesses") .flags(total | nozero | nonan) ; + missRate[access_idx] = misses[access_idx] / accesses[access_idx]; - missRate[access_idx] = misses[access_idx] / accesses[access_idx]; + for (int i = 0; i < system->maxRequestors(); i++) { + missRate[access_idx].subname(i, system->getReqName(i)); + } } demandMissRate .name(name() + ".demand_miss_rate") .desc("miss rate for demand accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandMissRate = demandMisses / demandAccesses; + for (int i = 0; i < system->maxRequestors(); i++) { + demandMissRate.subname(i, system->getReqName(i)); + } overallMissRate .name(name() + ".overall_miss_rate") .desc("miss rate for overall accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallMissRate = overallMisses / overallAccesses; + for (int i = 0; i < system->maxRequestors(); i++) { + overallMissRate.subname(i, system->getReqName(i)); + } // miss latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -294,24 +339,33 @@ .desc("average " + cstr + " miss latency") .flags(total | nozero | nonan) ; - avgMissLatency[access_idx] = missLatency[access_idx] / misses[access_idx]; + + for (int i = 0; i < system->maxRequestors(); i++) { + avgMissLatency[access_idx].subname(i, system->getReqName(i)); + } } demandAvgMissLatency .name(name() + ".demand_avg_miss_latency") .desc("average overall miss latency") - .flags(total) + .flags(total | nozero | nonan) ; demandAvgMissLatency = demandMissLatency / demandMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + demandAvgMissLatency.subname(i, system->getReqName(i)); + } overallAvgMissLatency .name(name() + ".overall_avg_miss_latency") .desc("average overall miss latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMissLatency = overallMissLatency / overallMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + overallAvgMissLatency.subname(i, system->getReqName(i)); + } blocked_cycles.init(NUM_BLOCKED_CAUSES); blocked_cycles @@ -350,11 +404,14 @@ ; writebacks - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + ".writebacks") .desc("number of writebacks") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + writebacks.subname(i, system->getReqName(i)); + } // MSHR statistics // MSHR hit statistics @@ -363,26 +420,35 @@ const string &cstr = cmd.toString(); mshr_hits[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_mshr_hits") .desc("number of " + cstr + " MSHR hits") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_hits[access_idx].subname(i, system->getReqName(i)); + } } demandMshrHits .name(name() + ".demand_mshr_hits") .desc("number of demand (read+write) MSHR hits") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrHits = SUM_DEMAND(mshr_hits); + for (int i = 0; i < system->maxRequestors(); i++) { + demandMshrHits.subname(i, system->getReqName(i)); + } overallMshrHits .name(name() + ".overall_mshr_hits") .desc("number of overall MSHR hits") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrHits = demandMshrHits + SUM_NON_DEMAND(mshr_hits); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrHits.subname(i, system->getReqName(i)); + } // MSHR miss statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -390,26 +456,35 @@ const string &cstr = cmd.toString(); mshr_misses[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_mshr_misses") .desc("number of " + cstr + " MSHR misses") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_misses[access_idx].subname(i, system->getReqName(i)); + } } demandMshrMisses .name(name() + ".demand_mshr_misses") .desc("number of demand (read+write) MSHR misses") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMisses = SUM_DEMAND(mshr_misses); + for (int i = 0; i < system->maxRequestors(); i++) { + demandMshrMisses.subname(i, system->getReqName(i)); + } overallMshrMisses .name(name() + ".overall_mshr_misses") .desc("number of overall MSHR misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMisses = demandMshrMisses + SUM_NON_DEMAND(mshr_misses); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrMisses.subname(i, system->getReqName(i)); + } // MSHR miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -417,27 +492,36 @@ const string &cstr = cmd.toString(); mshr_miss_latency[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_mshr_miss_latency") .desc("number of " + cstr + " MSHR miss cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_miss_latency[access_idx].subname(i, system->getReqName(i)); + } } demandMshrMissLatency .name(name() + ".demand_mshr_miss_latency") .desc("number of demand (read+write) MSHR miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMissLatency = SUM_DEMAND(mshr_miss_latency); + for (int i = 0; i < system->maxRequestors(); i++) { + demandMshrMissLatency.subname(i, system->getReqName(i)); + } overallMshrMissLatency .name(name() + ".overall_mshr_miss_latency") .desc("number of overall MSHR miss cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMissLatency = demandMshrMissLatency + SUM_NON_DEMAND(mshr_miss_latency); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrMissLatency.subname(i, system->getReqName(i)); + } // MSHR uncacheable statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -445,20 +529,26 @@ const string &cstr = cmd.toString(); mshr_uncacheable[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_mshr_uncacheable") .desc("number of " + cstr + " MSHR uncacheable") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_uncacheable[access_idx].subname(i, system->getReqName(i)); + } } overallMshrUncacheable .name(name() + ".overall_mshr_uncacheable_misses") .desc("number of overall MSHR uncacheable misses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrUncacheable = SUM_DEMAND(mshr_uncacheable) + SUM_NON_DEMAND(mshr_uncacheable); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrUncacheable.subname(i, system->getReqName(i)); + } // MSHR miss latency statistics for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -466,21 +556,27 @@ const string &cstr = cmd.toString(); mshr_uncacheable_lat[access_idx] - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + "." + cstr + "_mshr_uncacheable_latency") .desc("number of " + cstr + " MSHR uncacheable cycles") .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_uncacheable_lat[access_idx].subname(i, system->getReqName(i)); + } } overallMshrUncacheableLatency .name(name() + ".overall_mshr_uncacheable_latency") .desc("number of overall MSHR uncacheable cycles") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrUncacheableLatency = SUM_DEMAND(mshr_uncacheable_lat) + SUM_NON_DEMAND(mshr_uncacheable_lat); + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrUncacheableLatency.subname(i, system->getReqName(i)); + } #if 0 // MSHR access formulas @@ -524,24 +620,33 @@ .desc("mshr miss rate for " + cstr + " accesses") .flags(total | nozero | nonan) ; - mshrMissRate[access_idx] = mshr_misses[access_idx] / accesses[access_idx]; + + for (int i = 0; i < system->maxRequestors(); i++) { + mshrMissRate[access_idx].subname(i, system->getReqName(i)); + } } demandMshrMissRate .name(name() + ".demand_mshr_miss_rate") .desc("mshr miss rate for demand accesses") - .flags(total) + .flags(total | nozero | nonan) ; demandMshrMissRate = demandMshrMisses / demandAccesses; + for (int i = 0; i < system->maxRequestors(); i++) { + demandMshrMissRate.subname(i, system->getReqName(i)); + } overallMshrMissRate .name(name() + ".overall_mshr_miss_rate") .desc("mshr miss rate for overall accesses") - .flags(total) + .flags(total | nozero | nonan) ; overallMshrMissRate = overallMshrMisses / overallAccesses; + for (int i = 0; i < system->maxRequestors(); i++) { + overallMshrMissRate.subname(i, system->getReqName(i)); + } // mshrMiss latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -553,24 +658,33 @@ .desc("average " + cstr + " mshr miss latency") .flags(total | nozero | nonan) ; - avgMshrMissLatency[access_idx] = mshr_miss_latency[access_idx] / mshr_misses[access_idx]; + + for (int i = 0; i < system->maxRequestors(); i++) { + avgMshrMissLatency[access_idx].subname(i, system->getReqName(i)); + } } demandAvgMshrMissLatency .name(name() + ".demand_avg_mshr_miss_latency") .desc("average overall mshr miss latency") - .flags(total) + .flags(total | nozero | nonan) ; demandAvgMshrMissLatency = demandMshrMissLatency / demandMshrMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + demandAvgMshrMissLatency.subname(i, system->getReqName(i)); + } overallAvgMshrMissLatency .name(name() + ".overall_avg_mshr_miss_latency") .desc("average overall mshr miss latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMshrMissLatency = overallMshrMissLatency / overallMshrMisses; + for (int i = 0; i < system->maxRequestors(); i++) { + overallAvgMshrMissLatency.subname(i, system->getReqName(i)); + } // mshrUncacheable latency formulas for (int access_idx = 0; access_idx < MemCmd::NUM_MEM_CMDS; ++access_idx) { @@ -582,32 +696,44 @@ .desc("average " + cstr + " mshr uncacheable latency") .flags(total | nozero | nonan) ; - avgMshrUncacheableLatency[access_idx] = mshr_uncacheable_lat[access_idx] / mshr_uncacheable[access_idx]; + + for (int i = 0; i < system->maxRequestors(); i++) { + avgMshrUncacheableLatency[access_idx].subname(i, system->getReqName(i)); + } } overallAvgMshrUncacheableLatency .name(name() + ".overall_avg_mshr_uncacheable_latency") .desc("average overall mshr uncacheable latency") - .flags(total) + .flags(total | nozero | nonan) ; overallAvgMshrUncacheableLatency = overallMshrUncacheableLatency / overallMshrUncacheable; + for (int i = 0; i < system->maxRequestors(); i++) { + overallAvgMshrUncacheableLatency.subname(i, system->getReqName(i)); + } mshr_cap_events - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + ".mshr_cap_events") .desc("number of times MSHR cap was activated") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + mshr_cap_events.subname(i, system->getReqName(i)); + } //software prefetching stats soft_prefetch_mshr_full - .init(maxThreadsPerCPU) + .init(system->maxRequestors()) .name(name() + ".soft_prefetch_mshr_full") .desc("number of mshr full events for SW prefetching instrutions") - .flags(total) + .flags(total | nozero | nonan) ; + for (int i = 0; i < system->maxRequestors(); i++) { + soft_prefetch_mshr_full.subname(i, system->getReqName(i)); + } mshr_no_allocate_misses .name(name() +".no_allocate_misses") diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/blk.hh --- a/src/mem/cache/blk.hh Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/blk.hh Sat Feb 04 14:26:18 2012 -0600 @@ -103,8 +103,8 @@ /** Number of references to this block since it was brought in. */ int refCount; - /** holds the context source ID of the requestor for this block. */ - int contextSrc; + /** holds the source requestor ID for this block. */ + int srcReqId; protected: /** @@ -135,7 +135,7 @@ CacheBlk() : asid(-1), tag(0), data(0) ,size(0), status(0), whenReady(0), - set(-1), isTouched(false), refCount(0), contextSrc(-1) + set(-1), isTouched(false), refCount(0), srcReqId(-1) {} /** diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/cache_impl.hh Sat Feb 04 14:26:18 2012 -0600 @@ -312,7 +312,7 @@ if (pkt->needsExclusive() ? blk->isWritable() : blk->isReadable()) { // OK to satisfy access - incHitCount(pkt, id); + incHitCount(pkt); satisfyCpuSideRequest(pkt, blk); return true; } @@ -332,10 +332,10 @@ if (blk == NULL) { // no replaceable block available, give up. // writeback will be forwarded to next level. - incMissCount(pkt, id); + incMissCount(pkt); return false; } - int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + int id = pkt->req->reqId(); tags->insertBlock(pkt->getAddr(), blk, id); blk->status = BlkValid | BlkReadable; } @@ -346,11 +346,11 @@ } // nothing else to do; writeback doesn't expect response assert(!pkt->needsResponse()); - incHitCount(pkt, id); + incHitCount(pkt); return true; } - incMissCount(pkt, id); + incMissCount(pkt); if (blk == NULL && pkt->isLLSC() && pkt->isWrite()) { // complete miss on store conditional... just give up now @@ -514,7 +514,8 @@ if (mshr) { // MSHR hit //@todo remove hw_pf here - mshr_hits[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; + assert(pkt->req->reqId() < system->maxRequestors()); + mshr_hits[pkt->cmdToIndex()][pkt->req->reqId()]++; if (mshr->threadNum != 0/*pkt->req->threadId()*/) { mshr->threadNum = -1; } @@ -529,7 +530,8 @@ } } else { // no MSHR - mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; + assert(pkt->req->reqId() < system->maxRequestors()); + mshr_misses[pkt->cmdToIndex()][pkt->req->reqId()]++; // always mark as cache fill for now... if we implement // no-write-allocate or bypass accesses this will have to // be changed. @@ -849,10 +851,12 @@ PacketList writebacks; if (pkt->req->isUncacheable()) { - mshr_uncacheable_lat[stats_cmd_idx][0/*pkt->req->threadId()*/] += + assert(pkt->req->reqId() < system->maxRequestors()); + mshr_uncacheable_lat[stats_cmd_idx][pkt->req->reqId()] += miss_latency; } else { - mshr_miss_latency[stats_cmd_idx][0/*pkt->req->threadId()*/] += + assert(pkt->req->reqId() < system->maxRequestors()); + mshr_miss_latency[stats_cmd_idx][pkt->req->reqId()] += miss_latency; } @@ -898,7 +902,9 @@ (transfer_offset ? pkt->finishTime : pkt->firstWordTime); assert(!target->pkt->req->isUncacheable()); - missLatency[target->pkt->cmdToIndex()][0/*pkt->req->threadId()*/] += + + assert(pkt->req->reqId() < system->maxRequestors()); + missLatency[target->pkt->cmdToIndex()][target->pkt->req->reqId()] += completion_time - target->recvTime; } else if (pkt->cmd == MemCmd::UpgradeFailResp) { // failed StoreCond upgrade @@ -1003,7 +1009,7 @@ { assert(blk && blk->isValid() && blk->isDirty()); - writebacks[0/*pkt->req->threadId()*/]++; + writebacks[Request::wbReqId]++; Request *writebackReq = new Request(tags->regenerateBlkAddr(blk->tag, blk->set), blkSize, 0, @@ -1082,7 +1088,7 @@ tempBlock->tag = tags->extractTag(addr); DPRINTF(Cache, "using temp block for %x\n", addr); } else { - int id = pkt->req->hasContextId() ? pkt->req->contextId() : -1; + int id = pkt->req->reqId(); tags->insertBlock(pkt->getAddr(), blk, id); } @@ -1427,7 +1433,8 @@ !writeBuffer.findMatch(pf_addr)) { // Update statistic on number of prefetches issued // (hwpf_mshr_misses) - mshr_misses[pkt->cmdToIndex()][0/*pkt->req->threadId()*/]++; + assert(pkt->req->reqId() < system->maxRequestors()); + mshr_misses[pkt->cmdToIndex()][pkt->req->reqId()]++; // Don't request bus, since we already have it return allocateMissBuffer(pkt, curTick(), false); } else { diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/tags/base.hh --- a/src/mem/cache/tags/base.hh Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/tags/base.hh Sat Feb 04 14:26:18 2012 -0600 @@ -97,10 +97,10 @@ /** The cycle that the warmup percentage was hit. */ Stats::Scalar warmupCycle; - /** Average occupancy of each context/cpu using the cache */ + /** Average occupancy of each requestor using the cache */ Stats::AverageVector occupancies; - /** Average occ % of each context/cpu using the cache */ + /** Average occ % of each requestor using the cache */ Stats::Formula avgOccs; /** diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/tags/base.cc --- a/src/mem/cache/tags/base.cc Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/tags/base.cc Sat Feb 04 14:26:18 2012 -0600 @@ -87,17 +87,23 @@ ; occupancies - .init(cache->numCpus() + 1) + .init(cache->system->maxRequestors()) .name(name + ".occ_blocks") - .desc("Average occupied blocks per context") + .desc("Average occupied blocks per requestor") .flags(nozero | nonan) ; + for (int i = 0; i < cache->system->maxRequestors(); i++) { + occupancies.subname(i, cache->system->getReqName(i)); + } avgOccs .name(name + ".occ_percent") .desc("Average percentage of cache occupancy") - .flags(nozero) + .flags(nozero | total) ; + for (int i = 0; i < cache->system->maxRequestors(); i++) { + avgOccs.subname(i, cache->system->getReqName(i)); + } avgOccs = occupancies / Stats::constant(numBlocks); diff -r c696d9974184 -r dcfa7c7145fd src/mem/cache/tags/lru.cc --- a/src/mem/cache/tags/lru.cc Sat Feb 04 13:16:43 2012 -0600 +++ b/src/mem/cache/tags/lru.cc Sat Feb 04 14:26:18 2012 -0600 @@ -160,12 +160,10 @@ blk->refCount = 0; // deal with evicted block - if (blk->contextSrc != -1) { - occupancies[blk->contextSrc % cache->numCpus()]--; - blk->contextSrc = -1; - } else { - occupancies[cache->numCpus()]--; - } + assert(blk->srcReqId >= 0 && + blk->srcReqId < cache->system->maxRequestors()); + occupancies[blk->srcReqId]--; + blk->srcReqId = -1; DPRINTF(CacheRepl, "set %x: selecting blk %x for replacement\n", set, regenerateBlkAddr(blk->tag, set)); @@ -189,12 +187,10 @@ blk->tag = extractTag(addr); // deal with what we are bringing in - if (context_src != -1) { - occupancies[context_src % cache->numCpus()]++; - } else { - occupancies[cache->numCpus()]++; - } - blk->contextSrc = context_src; + assert(context_src >= 0 && + context_src < cache->system->maxRequestors()); + occupancies[context_src]++; + blk->srcReqId = context_src; unsigned set = extractSet(addr); sets[set].moveToHead(blk); @@ -208,12 +204,10 @@ blk->isTouched = false; blk->clearLoadLocks(); tagsInUse--; - if (blk->contextSrc != -1) { - occupancies[blk->contextSrc % cache->numCpus()]--; - blk->contextSrc = -1; - } else { - occupancies[cache->numCpus()]--; - } + assert(blk->srcReqId >= 0 && + blk->srcReqId < cache->system->maxRequestors()); + occupancies[blk->srcReqId]--; + blk->srcReqId = -1; } } diff -r c696d9974184 -r dcfa7c7145fd tests/configs/memtest.py --- a/tests/configs/memtest.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/memtest.py Sat Feb 04 14:26:18 2012 -0600 @@ -64,7 +64,6 @@ system.toL2Bus = Bus(clock="500GHz", width=16) system.l2c = L2(size='64kB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port -system.l2c.num_cpus = nb_cores # connect l2c to membus system.l2c.mem_side = system.membus.port diff -r c696d9974184 -r dcfa7c7145fd tests/configs/o3-timing-mp.py --- a/tests/configs/o3-timing-mp.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/o3-timing-mp.py Sat Feb 04 14:26:18 2012 -0600 @@ -63,7 +63,6 @@ system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port -system.l2c.num_cpus = nb_cores # connect l2c to membus system.l2c.mem_side = system.membus.port diff -r c696d9974184 -r dcfa7c7145fd tests/configs/realview-o3-dual.py --- a/tests/configs/realview-o3-dual.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/realview-o3-dual.py Sat Feb 04 14:26:18 2012 -0600 @@ -83,7 +83,6 @@ system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: diff -r c696d9974184 -r dcfa7c7145fd tests/configs/realview-simple-timing-dual.py --- a/tests/configs/realview-simple-timing-dual.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/realview-simple-timing-dual.py Sat Feb 04 14:26:18 2012 -0600 @@ -83,7 +83,6 @@ system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: diff -r c696d9974184 -r dcfa7c7145fd tests/configs/simple-atomic-mp.py --- a/tests/configs/simple-atomic-mp.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/simple-atomic-mp.py Sat Feb 04 14:26:18 2012 -0600 @@ -62,7 +62,6 @@ system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port -system.l2c.num_cpus = nb_cores # connect l2c to membus system.l2c.mem_side = system.membus.port diff -r c696d9974184 -r dcfa7c7145fd tests/configs/simple-timing-mp.py --- a/tests/configs/simple-timing-mp.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/simple-timing-mp.py Sat Feb 04 14:26:18 2012 -0600 @@ -62,7 +62,6 @@ system.toL2Bus = Bus() system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port -system.l2c.num_cpus = nb_cores # connect l2c to membus system.l2c.mem_side = system.membus.port diff -r c696d9974184 -r dcfa7c7145fd tests/configs/tsunami-o3-dual.py --- a/tests/configs/tsunami-o3-dual.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/tsunami-o3-dual.py Sat Feb 04 14:26:18 2012 -0600 @@ -85,7 +85,6 @@ system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: diff -r c696d9974184 -r dcfa7c7145fd tests/configs/tsunami-simple-atomic-dual.py --- a/tests/configs/tsunami-simple-atomic-dual.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/tsunami-simple-atomic-dual.py Sat Feb 04 14:26:18 2012 -0600 @@ -83,7 +83,6 @@ system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: diff -r c696d9974184 -r dcfa7c7145fd tests/configs/tsunami-simple-timing-dual.py --- a/tests/configs/tsunami-simple-timing-dual.py Sat Feb 04 13:16:43 2012 -0600 +++ b/tests/configs/tsunami-simple-timing-dual.py Sat Feb 04 14:26:18 2012 -0600 @@ -83,7 +83,6 @@ system.l2c = L2(size='4MB', assoc=8) system.l2c.cpu_side = system.toL2Bus.port system.l2c.mem_side = system.membus.port -system.l2c.num_cpus = 2 #connect up the cpu and l1s for c in cpus: