diff -r a451e4eda591 -r 65a176ece9d6 configs/example/fs.py
--- a/configs/example/fs.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/fs.py	Mon Feb 13 19:06:41 2012 +0000
@@ -195,8 +195,8 @@
         drive_sys.kernel = binary(options.kernel)
     drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
                                ranges = [AddrRange(bm[1].mem())])
-    drive_sys.iobridge.slave = drive_sys.iobus.port
-    drive_sys.iobridge.master = drive_sys.membus.port
+    drive_sys.iobridge.slave = drive_sys.iobus.master
+    drive_sys.iobridge.master = drive_sys.membus.slave
 
     drive_sys.init_param = options.init_param
     root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/ruby_direct_test.py
--- a/configs/example/ruby_direct_test.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_direct_test.py	Mon Feb 13 19:06:41 2012 +0000
@@ -102,7 +102,7 @@
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
-    system.tester.cpuPort = ruby_port.port
+    system.tester.cpuPort = ruby_port.slave
 
 # -----------------------
 # run simulation
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/ruby_fs.py
--- a/configs/example/ruby_fs.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_fs.py	Mon Feb 13 19:06:41 2012 +0000
@@ -125,11 +125,11 @@
     #
     # Tie the cpu ports to the correct ruby system ports
     #
-    cpu.icache_port = system.ruby._cpu_ruby_ports[i].port
-    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].port
+    cpu.icache_port = system.ruby._cpu_ruby_ports[i].slave
+    cpu.dcache_port = system.ruby._cpu_ruby_ports[i].slave
     if buildEnv['TARGET_ISA'] == "x86":
-        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].port
-        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].port
+        cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave
+        cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave
         cpu.interrupts.pio = system.piobus.master
         cpu.interrupts.int_master = system.piobus.slave
         cpu.interrupts.int_slave = system.piobus.master
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_mem_test.py	Mon Feb 13 19:06:41 2012 +0000
@@ -133,7 +133,7 @@
     #
     # Tie the cpu memtester ports to the correct system ports
     #
-    cpu.test = system.ruby._cpu_ruby_ports[i].port
+    cpu.test = system.ruby._cpu_ruby_ports[i].slave
     cpu.functional = system.funcmem.port
 
     #
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/ruby_network_test.py
--- a/configs/example/ruby_network_test.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_network_test.py	Mon Feb 13 19:06:41 2012 +0000
@@ -109,7 +109,7 @@
      #
      # Tie the cpu test ports to the ruby cpu port
      #
-     cpus[i].test = ruby_port.port
+     cpus[i].test = ruby_port.slave
      ruby_port.access_phys_mem = False
 
      i += 1
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/ruby_random_test.py
--- a/configs/example/ruby_random_test.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/ruby_random_test.py	Mon Feb 13 19:06:41 2012 +0000
@@ -110,7 +110,7 @@
     #
     # Tie the ruby tester ports to the ruby cpu ports
     #
-    tester.cpuPort = ruby_port.port
+    tester.cpuPort = ruby_port.slave
 
     #
     # Tell each sequencer this is the ruby tester so that it
diff -r a451e4eda591 -r 65a176ece9d6 configs/example/se.py
--- a/configs/example/se.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/example/se.py	Mon Feb 13 19:06:41 2012 +0000
@@ -190,8 +190,8 @@
     system.cpu[i].workload = multiprocesses[i]
 
     if options.ruby:
-        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].port
-        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].port
+        system.cpu[i].icache_port = system.ruby._cpu_ruby_ports[i].slave
+        system.cpu[i].dcache_port = system.ruby._cpu_ruby_ports[i].slave
 
     if options.fastmem:
         system.cpu[0].physmem_port = system.physmem.port
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/MESI_CMP_directory.py
--- a/configs/ruby/MESI_CMP_directory.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MESI_CMP_directory.py	Mon Feb 13 19:06:41 2012 +0000
@@ -103,7 +103,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         
@@ -180,9 +180,9 @@
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/MI_example.py
--- a/configs/ruby/MI_example.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MI_example.py	Mon Feb 13 19:06:41 2012 +0000
@@ -95,7 +95,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -153,10 +153,10 @@
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
-        dma_cntrl.dma_sequencer.port = dma_device.dma
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
+        dma_cntrl.dma_sequencer.slave = dma_device.dma
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/MOESI_CMP_directory.py
--- a/configs/ruby/MOESI_CMP_directory.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_CMP_directory.py	Mon Feb 13 19:06:41 2012 +0000
@@ -103,7 +103,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -177,9 +177,9 @@
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/MOESI_CMP_token.py
--- a/configs/ruby/MOESI_CMP_token.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_CMP_token.py	Mon Feb 13 19:06:41 2012 +0000
@@ -125,7 +125,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #
@@ -201,9 +201,9 @@
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         cntrl_count += 1
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/MOESI_hammer.py
--- a/configs/ruby/MOESI_hammer.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/MOESI_hammer.py	Mon Feb 13 19:06:41 2012 +0000
@@ -118,7 +118,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         if options.recycle_latency:
             l1_cntrl.recycle_latency = options.recycle_latency
@@ -213,9 +213,9 @@
 
         exec("system.dma_cntrl%d = dma_cntrl" % i)
         if dma_device.type == 'MemTest':
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.test" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.test" % i)
         else:
-            exec("system.dma_cntrl%d.dma_sequencer.port = dma_device.dma" % i)
+            exec("system.dma_cntrl%d.dma_sequencer.slave = dma_device.dma" % i)
         dma_cntrl_nodes.append(dma_cntrl)
 
         if options.recycle_latency:
diff -r a451e4eda591 -r 65a176ece9d6 configs/ruby/Network_test.py
--- a/configs/ruby/Network_test.py	Mon Feb 13 12:30:30 2012 -0600
+++ b/configs/ruby/Network_test.py	Mon Feb 13 19:06:41 2012 +0000
@@ -96,7 +96,7 @@
         l1_cntrl.sequencer = cpu_seq
 
         if piobus != None:
-            cpu_seq.pio_port = piobus.port
+            cpu_seq.pio_port = piobus.slave
 
         exec("system.l1_cntrl%d = l1_cntrl" % i)
         #