diff -r e2fe2a299f40 -r 3c033ec380b5 configs/common/Benchmarks.py --- a/configs/common/Benchmarks.py Wed Feb 15 16:00:35 2012 -0600 +++ b/configs/common/Benchmarks.py Wed Feb 15 17:07:15 2012 -0600 @@ -46,7 +46,7 @@ if self.memsize: return self.memsize else: - return '128MB' + return '8GB' def disk(self): if self.diskname: diff -r e2fe2a299f40 -r 3c033ec380b5 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Wed Feb 15 16:00:35 2012 -0600 +++ b/configs/common/FSConfig.py Wed Feb 15 17:07:15 2012 -0600 @@ -423,7 +423,18 @@ self.mem_mode = mem_mode # Physical memory - self.physmem = PhysicalMemory(range = AddrRange(mdesc.mem())) + addr_range = AddrRange(mdesc.mem()) + str_addr_range = "%s" % addr_range + [addr_begin, addr_end] = str_addr_range.split(':'); + addr_begin = int(addr_begin) + addr_end = int(addr_end) + + if(addr_end < 3221225472): + self.physmem = PhysicalMemory(ranges = [AddrRange(mdesc.mem())]) + else: + self.physmem = PhysicalMemory(ranges = [ + AddrRange('3GB'), + AddrRange(0x100000000, 0x100000000 + (addr_end - 3221225472))]) # Platform self.pc = Pc() @@ -534,7 +545,7 @@ # We assume below that there's at least 1MB of memory. We'll require 2 # just to avoid corner cases. - assert(self.physmem.range.second.getValue() >= 0x200000) + assert(self.physmem.ranges[0].second.getValue() >= 0x200000) self.e820_table.entries = \ [ @@ -542,7 +553,10 @@ X86E820Entry(addr = 0, size = '1MB', range_type = 2), # Mark the rest as available X86E820Entry(addr = 0x100000, - size = '%dB' % (self.physmem.range.second - 0x100000 + 1), + size = '%dB' % (self.physmem.ranges[0].second - 0x100000 + 1), + range_type = 1), + X86E820Entry(addr = 0x100000000, + size = '%dB' % (self.physmem.ranges[1].second - 0x100000000 + 1), range_type = 1) ] diff -r e2fe2a299f40 -r 3c033ec380b5 configs/ruby/MESI_CMP_directory.py --- a/configs/ruby/MESI_CMP_directory.py Wed Feb 15 16:00:35 2012 -0600 +++ b/configs/ruby/MESI_CMP_directory.py Wed Feb 15 17:07:15 2012 -0600 @@ -135,8 +135,8 @@ cntrl_count += 1 - phys_mem_size = long(system.physmem.range.second) - \ - long(system.physmem.range.first) + 1 + phys_mem_size = long(system.physmem.ranges[1].second) - \ + long(system.physmem.ranges[0].first) + 1 mem_module_size = phys_mem_size / options.num_dirs for i in xrange(options.num_dirs): diff -r e2fe2a299f40 -r 3c033ec380b5 configs/ruby/Ruby.py --- a/configs/ruby/Ruby.py Wed Feb 15 16:00:35 2012 -0600 +++ b/configs/ruby/Ruby.py Wed Feb 15 17:07:15 2012 -0600 @@ -176,8 +176,9 @@ total_mem_size.value += dir_cntrl.directory.size.value dir_cntrl.directory.numa_high_bit = numa_bit - physmem_size = long(system.physmem.range.second) - \ - long(system.physmem.range.first) + 1 + physmem_size = long(system.physmem.ranges[1].second) - \ + long(system.physmem.ranges[0].first) + 1 + print "%s" % total_mem_size assert(total_mem_size.value == physmem_size) ruby_profiler = RubyProfiler(ruby_system = ruby, diff -r e2fe2a299f40 -r 3c033ec380b5 src/mem/PhysicalMemory.py --- a/src/mem/PhysicalMemory.py Wed Feb 15 16:00:35 2012 -0600 +++ b/src/mem/PhysicalMemory.py Wed Feb 15 17:07:15 2012 -0600 @@ -33,7 +33,7 @@ class PhysicalMemory(MemObject): type = 'PhysicalMemory' port = VectorSlavePort("the access port") - range = Param.AddrRange(AddrRange('128MB'), "Device Address") + ranges = VectorParam.AddrRange([AddrRange('128MB')], "Device Address") file = Param.String('', "memory mapped file") latency = Param.Latency('30ns', "latency of an access") latency_var = Param.Latency('0ns', "access variablity") diff -r e2fe2a299f40 -r 3c033ec380b5 src/mem/dram.cc --- a/src/mem/dram.cc Wed Feb 15 16:00:35 2012 -0600 +++ b/src/mem/dram.cc Wed Feb 15 17:07:15 2012 -0600 @@ -196,7 +196,7 @@ memctrlpipe_enable(false), time_last_access(0) { warn("This DRAM module has not been tested with the new memory system at all!"); - bank_size = (p->range.size() + 1) / num_banks; + bank_size = (_size + 1) / num_banks; num_rows = bank_size / SD_ROW_SIZE; /* 0x1000 size of row 4Kbtye */ active_row = new int[num_banks]; last_bank = num_banks+1; diff -r e2fe2a299f40 -r 3c033ec380b5 src/mem/physical.hh --- a/src/mem/physical.hh Wed Feb 15 16:00:35 2012 -0600 +++ b/src/mem/physical.hh Wed Feb 15 17:07:15 2012 -0600 @@ -37,7 +37,6 @@ #include #include -#include "base/range.hh" #include "base/statistics.hh" #include "mem/mem_object.hh" #include "mem/packet.hh" @@ -74,9 +73,6 @@ virtual unsigned deviceBlockSize() const; }; - int numPorts; - - private: // prevent copying of a MainMemory object PhysicalMemory(const PhysicalMemory &specmem); @@ -157,6 +153,9 @@ uint64_t _size; uint64_t _start; + /** Address ranges to pass through the bridge */ + AddrRangeList ranges; + /** Number of total bytes read from this memory */ Stats::Scalar bytesRead; /** Number of instruction bytes read from this memory */ diff -r e2fe2a299f40 -r 3c033ec380b5 src/mem/physical.cc --- a/src/mem/physical.cc Wed Feb 15 16:00:35 2012 -0600 +++ b/src/mem/physical.cc Wed Feb 15 17:07:15 2012 -0600 @@ -71,10 +71,19 @@ PhysicalMemory::PhysicalMemory(const Params *p) : MemObject(p), pmemAddr(NULL), lat(p->latency), lat_var(p->latency_var), - _size(params()->range.size()), _start(params()->range.start) + ranges(params()->ranges.begin(), params()->ranges.end()) { + // Assuming ranges is sorted + Addr lowerLimit = ranges.front().start; + Addr upperLimit = 0; + for (AddrRangeIter it = ranges.begin(); it != ranges.end(); ++it) { + upperLimit = (*it).end; + } + _size = upperLimit - lowerLimit + 1; + _start = lowerLimit; + if (size() % TheISA::PageBytes != 0) - panic("Memory Size not divisible by page size\n"); + panic("Memory Size (%lld) not divisible by page size \n", _size); if (params()->null) return; @@ -477,8 +486,6 @@ AddrRangeList PhysicalMemory::getAddrRanges() { - AddrRangeList ranges; - ranges.push_back(RangeSize(start(), size())); return ranges; } @@ -608,9 +615,9 @@ munmap((char*)pmemAddr, size()); UNSERIALIZE_SCALAR(_size); - if (size() > params()->range.size()) - fatal("Memory size has changed! size %lld, param size %lld\n", - size(), params()->range.size()); + //if (size() > params()->range.size()) + // fatal("Memory size has changed! size %lld, param size %lld\n", + // size(), params()->range.size()); pmemAddr = (uint8_t *)mmap(NULL, size(), PROT_READ | PROT_WRITE, MAP_ANON | MAP_PRIVATE, -1, 0);