diff -r 9f1c4729d89d -r 4d1564cccd17 src/cpu/base.hh
--- a/src/cpu/base.hh	Thu Mar 01 22:43:23 2012 -0600
+++ b/src/cpu/base.hh	Fri Mar 02 12:47:22 2012 +0000
@@ -302,7 +302,7 @@
     typedef BaseCPUParams Params;
     const Params *params() const
     { return reinterpret_cast<const Params *>(_params); }
-    BaseCPU(Params *params);
+    BaseCPU(Params *params, bool is_checker = false);
     virtual ~BaseCPU();
 
     virtual void init();
diff -r 9f1c4729d89d -r 4d1564cccd17 src/cpu/base.cc
--- a/src/cpu/base.cc	Thu Mar 01 22:43:23 2012 -0600
+++ b/src/cpu/base.cc	Fri Mar 02 12:47:22 2012 +0000
@@ -118,7 +118,7 @@
     return "CPU Progress";
 }
 
-BaseCPU::BaseCPU(Params *p)
+BaseCPU::BaseCPU(Params *p, bool is_checker)
     : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
       _instMasterId(p->system->getMasterId(name() + ".inst")),
       _dataMasterId(p->system->getMasterId(name() + ".data")),
@@ -219,10 +219,17 @@
             schedule(event, p->function_trace_start);
         }
     }
-    // Check if CPU model has interrupts connected. The CheckerCPU
-    // cannot take interrupts directly for example.
-    if (interrupts)
-        interrupts->setCPU(this);
+
+    // The interrupts should always be present unless this CPU is
+    // switched in later or in case it is a checker CPU
+    if (!params()->defer_registration && !is_checker) {
+        if (interrupts) {
+            interrupts->setCPU(this);
+        } else {
+            fatal("CPU %s has no interrupt controller.\n"
+                  "Ensure createInterruptController() is called.\n", name());
+        }
+    }
 
     if (FullSystem) {
         profileEvent = NULL;
diff -r 9f1c4729d89d -r 4d1564cccd17 src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc	Thu Mar 01 22:43:23 2012 -0600
+++ b/src/cpu/checker/cpu.cc	Fri Mar 02 12:47:22 2012 +0000
@@ -64,7 +64,7 @@
 }
 
 CheckerCPU::CheckerCPU(Params *p)
-    : BaseCPU(p), thread(NULL), tc(NULL)
+    : BaseCPU(p, true), thread(NULL), tc(NULL)
 {
     memReq = NULL;
     curStaticInst = NULL;
diff -r 9f1c4729d89d -r 4d1564cccd17 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc	Thu Mar 01 22:43:23 2012 -0600
+++ b/src/cpu/inorder/cpu.cc	Fri Mar 02 12:47:22 2012 +0000
@@ -387,6 +387,12 @@
 
     }
 
+    // InOrderCPU always requires an interrupt controller.
+    if (!params->defer_registration && !interrupts) {
+        fatal("InOrderCPU %s has no interrupt controller.\n"
+              "Ensure createInterruptController() is called.\n", name());
+    }
+
     dummyReqInst = new InOrderDynInst(this, NULL, 0, 0, 0);
     dummyReqInst->setSquashed();
     dummyReqInst->resetInstCount();
diff -r 9f1c4729d89d -r 4d1564cccd17 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Thu Mar 01 22:43:23 2012 -0600
+++ b/src/cpu/o3/cpu.cc	Fri Mar 02 12:47:22 2012 +0000
@@ -460,6 +460,12 @@
         this->threadContexts.push_back(tc);
     }
 
+    // FullO3CPU always requires an interrupt controller.
+    if (!params->defer_registration && !interrupts) {
+        fatal("FullO3CPU %s has no interrupt controller.\n"
+              "Ensure createInterruptController() is called.\n", name());
+    }
+
     for (ThreadID tid = 0; tid < this->numThreads; tid++)
         this->thread[tid]->setFuncExeInst(0);
 
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/inorder-timing.py
--- a/tests/configs/inorder-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/inorder-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -52,6 +52,8 @@
                 membus = Bus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
 root = Root(full_system = False, system = system)
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/o3-timing-mp-ruby.py
--- a/tests/configs/o3-timing-mp-ruby.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/o3-timing-mp-ruby.py	Fri Mar 02 12:47:22 2012 +0000
@@ -40,6 +40,8 @@
 system = System(cpu = cpus, physmem = ruby_memory, membus = Bus())
 
 for cpu in cpus:
+    # create the interrupt controller
+    cpu.createInterruptController()
     cpu.connectAllPorts(system.membus)
     cpu.clock = '2GHz'
 
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/o3-timing-mp.py
--- a/tests/configs/o3-timing-mp.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/o3-timing-mp.py	Fri Mar 02 12:47:22 2012 +0000
@@ -71,6 +71,8 @@
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/o3-timing-ruby.py
--- a/tests/configs/o3-timing-ruby.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/o3-timing-ruby.py	Fri Mar 02 12:47:22 2012 +0000
@@ -41,6 +41,8 @@
                 physmem = ruby_memory,
                 membus = Bus())
 system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
 # Connect the system port for loading of binaries etc
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/o3-timing.py
--- a/tests/configs/o3-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/o3-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -52,6 +52,8 @@
                 membus = Bus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 
 root = Root(full_system = False, system = system)
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/pc-o3-timing.py
--- a/tests/configs/pc-o3-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/pc-o3-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -104,6 +104,8 @@
                             L1(size = '32kB', assoc = 4),
                             PageTableWalkerCache(),
                             PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/pc-simple-atomic.py
--- a/tests/configs/pc-simple-atomic.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/pc-simple-atomic.py	Fri Mar 02 12:47:22 2012 +0000
@@ -106,6 +106,8 @@
                             L1(size = '32kB', assoc = 4),
                             PageTableWalkerCache(),
                             PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/pc-simple-timing.py
--- a/tests/configs/pc-simple-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/pc-simple-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -106,6 +106,8 @@
                             L1(size = '32kB', assoc = 4),
                             PageTableWalkerCache(),
                             PageTableWalkerCache())
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-o3-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-o3.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-simple-atomic-dual.py
--- a/tests/configs/realview-simple-atomic-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-simple-atomic-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-simple-atomic.py
--- a/tests/configs/realview-simple-atomic.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-simple-atomic.py	Fri Mar 02 12:47:22 2012 +0000
@@ -86,6 +86,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-simple-timing-dual.py
--- a/tests/configs/realview-simple-timing-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-simple-timing-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/realview-simple-timing.py
--- a/tests/configs/realview-simple-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/realview-simple-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/simple-atomic-mp.py
--- a/tests/configs/simple-atomic-mp.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/simple-atomic-mp.py	Fri Mar 02 12:47:22 2012 +0000
@@ -70,6 +70,8 @@
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/simple-atomic.py
--- a/tests/configs/simple-atomic.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/simple-atomic.py	Fri Mar 02 12:47:22 2012 +0000
@@ -34,6 +34,8 @@
                 membus = Bus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
+# create the interrupt controller
+system.cpu.createInterruptController()
 system.cpu.connectAllPorts(system.membus)
 system.cpu.clock = '2GHz'
 
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/simple-timing-mp.py
--- a/tests/configs/simple-timing-mp.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/simple-timing-mp.py	Fri Mar 02 12:47:22 2012 +0000
@@ -70,6 +70,8 @@
 for cpu in cpus:
     cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    cpu.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     cpu.connectAllPorts(system.toL2Bus, system.membus)
     cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/simple-timing-ruby.py
--- a/tests/configs/simple-timing-ruby.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/simple-timing-ruby.py	Fri Mar 02 12:47:22 2012 +0000
@@ -75,6 +75,9 @@
 
 assert(len(system.ruby._cpu_ruby_ports) == 1)
 
+# create the interrupt controller
+cpu.createInterruptController()
+
 #
 # Tie the cpu cache ports to the ruby cpu ports and
 # physmem, respectively
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/simple-timing.py
--- a/tests/configs/simple-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/simple-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -48,6 +48,8 @@
                 membus = Bus())
 system.system_port = system.membus.slave
 system.physmem.port = system.membus.master
+# create the interrupt controller
+cpu.createInterruptController()
 cpu.connectAllPorts(system.membus)
 cpu.clock = '2GHz'
 
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-o3-dual.py
--- a/tests/configs/tsunami-o3-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-o3-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -90,6 +90,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-o3.py
--- a/tests/configs/tsunami-o3.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-o3.py	Fri Mar 02 12:47:22 2012 +0000
@@ -89,6 +89,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-simple-atomic-dual.py
--- a/tests/configs/tsunami-simple-atomic-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-simple-atomic-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-simple-atomic.py
--- a/tests/configs/tsunami-simple-atomic.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-simple-atomic.py	Fri Mar 02 12:47:22 2012 +0000
@@ -87,6 +87,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-simple-timing-dual.py
--- a/tests/configs/tsunami-simple-timing-dual.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-simple-timing-dual.py	Fri Mar 02 12:47:22 2012 +0000
@@ -88,6 +88,8 @@
 for c in cpus:
     c.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                                 L1(size = '32kB', assoc = 4))
+    # create the interrupt controller
+    c.createInterruptController()
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/tsunami-simple-timing.py
--- a/tests/configs/tsunami-simple-timing.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/tsunami-simple-timing.py	Fri Mar 02 12:47:22 2012 +0000
@@ -89,6 +89,8 @@
 #connect up the cpu and l1s
 cpu.addPrivateSplitL1Caches(L1(size = '32kB', assoc = 1),
                             L1(size = '32kB', assoc = 4))
+# create the interrupt controller
+cpu.createInterruptController()
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
diff -r 9f1c4729d89d -r 4d1564cccd17 tests/configs/twosys-tsunami-simple-atomic.py
--- a/tests/configs/twosys-tsunami-simple-atomic.py	Thu Mar 01 22:43:23 2012 -0600
+++ b/tests/configs/twosys-tsunami-simple-atomic.py	Fri Mar 02 12:47:22 2012 +0000
@@ -35,6 +35,8 @@
 test_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-stream-client.rcS'))
 test_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+test_sys.cpu.createInterruptController()
 test_sys.cpu.connectAllPorts(test_sys.membus)
 # In contrast to the other (one-system) Tsunami configurations we do
 # not have an IO cache but instead rely on an IO bridge for accesses
@@ -47,6 +49,8 @@
 drive_sys = makeLinuxAlphaSystem('atomic',
                                  SysConfig('netperf-server.rcS'))
 drive_sys.cpu = AtomicSimpleCPU(cpu_id=0)
+# create the interrupt controller
+drive_sys.cpu.createInterruptController()
 drive_sys.cpu.connectAllPorts(drive_sys.membus)
 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
                             ranges = [AddrRange(0, '8GB')])