diff --git a/src/cpu/base.cc b/src/cpu/base.cc
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -385,7 +385,9 @@
     CpuPort &dc = getDataPort();
     assert(threadContexts.size() == oldCPU->threadContexts.size());
 
+    int tmpId = _cpuId;
     _cpuId = oldCPU->cpuId();
+    oldCPU->_cpuId = tmpId;
 
     ThreadID size = threadContexts.size();
     for (ThreadID i = 0; i < size; ++i) {
@@ -474,12 +476,16 @@
         Port *peer = oldCPU->getInstPort().getPeer();
         ic.setPeer(peer);
         peer->setPeer(&ic);
+
+        oldCPU->getInstPort().setPeer(NULL);
     }
 
     if (!dc.isConnected()) {
         Port *peer = oldCPU->getDataPort().getPeer();
         dc.setPeer(peer);
         peer->setPeer(&dc);
+
+        oldCPU->getDataPort().setPeer(NULL);
     }
 }
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -631,7 +631,8 @@
     wroteToTimeBuffer = false;
     _nextStatus = Inactive;
 
-    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
+    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB() &&
+            !iewStage->hasWbOutstanding() ) {
         cpu->signalDrained();
         drainPending = false;
         return;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -256,7 +256,7 @@
     if (!deferRegistration) {
         _status = Running;
     } else {
-        _status = Idle;
+        _status = SwitchedOut;
     }
 
     if (params->checker) {
@@ -1114,7 +1114,7 @@
     DPRINTF(O3CPU, "Switching out\n");
 
     // If the CPU isn't doing anything, then return immediately.
-    if (_status == Idle || _status == SwitchedOut) {
+    if ( _status == SwitchedOut) {
         return 0;
     }
 
@@ -1155,7 +1155,7 @@
 
     changeState(SimObject::Running);
 
-    if (_status == SwitchedOut || _status == Idle)
+    if (_status == SwitchedOut )
         return;
 
     assert(system->getMemoryMode() == Enums::timing);
@@ -1232,6 +1232,11 @@
 
     assert(!tickEvent.scheduled() || tickEvent.squashed());
 
+    //only copy over seqNum if the core has one
+    FullO3CPU<O3CPUImpl>* oldO3CPU = dynamic_cast<FullO3CPU<O3CPUImpl>*>(oldCPU);
+    if (oldO3CPU != NULL)
+        globalSeqNum = oldO3CPU->globalSeqNum;
+
     // @todo: Figure out how to properly select the tid to put onto
     // the active threads list.
     ThreadID tid = 0;
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -217,6 +217,9 @@
     /** Returns if the LSQ has any stores to writeback. */
     bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 
+    /** returns if the LSQ has any outstanding writebacks */
+    bool hasWbOutstanding() { return wbOutstanding != 0; }
+
     void incrWb(InstSeqNum &sn)
     {
         if (++wbOutstanding == wbMax)
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -335,6 +335,11 @@
         {
             std::memset(data, 0, sizeof(data));
         }
+        ~SQEntry()
+        {
+            //needed to clear RefCounted Insts
+            inst = NULL;
+        }
 
         /** Constructs a store queue entry for a given instruction. */
         SQEntry(DynInstPtr &_inst)