diff --git a/src/cpu/base.cc b/src/cpu/base.cc
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -385,7 +385,9 @@
     CpuPort &dc = getDataPort();
     assert(threadContexts.size() == oldCPU->threadContexts.size());
 
+    int tmpId = _cpuId;
     _cpuId = oldCPU->cpuId();
+    oldCPU->_cpuId = tmpId;
 
     ThreadID size = threadContexts.size();
     for (ThreadID i = 0; i < size; ++i) {
@@ -419,12 +421,16 @@
             Port *peer = old_itb_port->getPeer();;
             new_itb_port->setPeer(peer);
             peer->setPeer(new_itb_port);
+
+            old_itb_port->setPeer(NULL);
         }
         if (new_dtb_port && !new_dtb_port->isConnected()) {
             assert(old_dtb_port);
             Port *peer = old_dtb_port->getPeer();;
             new_dtb_port->setPeer(peer);
             peer->setPeer(new_dtb_port);
+
+            old_dtb_port->setPeer(NULL);
         }
 
         // Checker whether or not we have to transfer CheckerCPU
@@ -446,12 +452,16 @@
                 Port *peer = old_checker_itb_port->getPeer();;
                 new_checker_itb_port->setPeer(peer);
                 peer->setPeer(new_checker_itb_port);
+
+                old_itb_port->setPeer(NULL);
             }
             if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) {
                 assert(old_checker_dtb_port);
                 Port *peer = old_checker_dtb_port->getPeer();;
                 new_checker_dtb_port->setPeer(peer);
                 peer->setPeer(new_checker_dtb_port);
+
+                old_dtb_port->setPeer(NULL);
             }
         }
     }
@@ -474,12 +484,16 @@
         Port *peer = oldCPU->getInstPort().getPeer();
         ic.setPeer(peer);
         peer->setPeer(&ic);
+
+        oldCPU->getInstPort().setPeer(NULL);
     }
 
     if (!dc.isConnected()) {
         Port *peer = oldCPU->getDataPort().getPeer();
         dc.setPeer(peer);
         peer->setPeer(&dc);
+
+        oldCPU->getDataPort().setPeer(NULL);
     }
 }
 
diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh
+++ b/src/cpu/o3/commit_impl.hh
@@ -510,6 +510,7 @@
     TrapEvent *trap = new TrapEvent(this, tid);
 
     cpu->schedule(trap, curTick() + trapLatency);
+
     trapInFlight[tid] = true;
     thread[tid]->trapPending = true;
 }
@@ -631,11 +632,26 @@
     wroteToTimeBuffer = false;
     _nextStatus = Inactive;
 
-    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB()) {
-        cpu->signalDrained();
-        drainPending = false;
-        return;
-    }
+    if (drainPending && rob->isEmpty() && !iewStage->hasStoresToWB() &&
+            !iewStage->hasWbOutstanding() ) {
+
+        //make sure none of the treads have a pending trap
+        bool trapPending = false;
+        for (ThreadID tid = 0; tid < numThreads; tid++) {
+            if (trapInFlight[tid] == true ||  thread[tid]->trapPending == true ){
+                DPRINTF( Commit, "syscall pending for [tid:%u], can't switch out\n", tid);
+                trapPending = true;
+            }
+        }
+
+        if (!trapPending){
+            DPRINTF( Commit, "signal drained\n");
+            cpu->signalDrained();
+            drainPending = false;
+            return;
+        }
+        //else wait until trap done
+    }//drainPending
 
     if (activeThreads->empty())
         return;
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -256,7 +256,7 @@
     if (!deferRegistration) {
         _status = Running;
     } else {
-        _status = Idle;
+        _status = SwitchedOut;
     }
 
     if (params->checker) {
@@ -1114,16 +1114,17 @@
     DPRINTF(O3CPU, "Switching out\n");
 
     // If the CPU isn't doing anything, then return immediately.
-    if (_status == Idle || _status == SwitchedOut) {
+    if ( _status == SwitchedOut) {
         return 0;
     }
 
+    //only drain commit initially
+    // this allows commit to handle
+    // Faults while core is still
+    // running
     drainCount = 0;
-    fetch.drain();
-    decode.drain();
-    rename.drain();
-    iew.drain();
     commit.drain();
+    //other components will get drained within signalDrained
 
     // Wake the CPU and record activity so everything can drain out if
     // the CPU was not able to immediately drain.
@@ -1155,7 +1156,7 @@
 
     changeState(SimObject::Running);
 
-    if (_status == SwitchedOut || _status == Idle)
+    if (_status == SwitchedOut )
         return;
 
     assert(system->getMemoryMode() == Enums::timing);
@@ -1169,7 +1170,16 @@
 void
 FullO3CPU<Impl>::signalDrained()
 {
-    if (++drainCount == NumStages) {
+    //if commit has drained
+    if (++drainCount == 1 ) {
+        //its safe to drain the other stages
+        fetch.drain();
+        decode.drain();
+        rename.drain();
+        iew.drain();
+    }
+
+    if (drainCount == NumStages) {
         if (tickEvent.scheduled())
             tickEvent.squash();
 
@@ -1211,6 +1221,9 @@
 void
 FullO3CPU<Impl>::takeOverFrom(BaseCPU *oldCPU)
 {
+
+    DPRINTF( O3CPU, "taking over for cpu:%s", oldCPU->name());
+
     // Flush out any old data from the time buffers.
     for (int i = 0; i < timeBuffer.getSize(); ++i) {
         timeBuffer.advance();
@@ -1232,6 +1245,15 @@
 
     assert(!tickEvent.scheduled() || tickEvent.squashed());
 
+    //only copy over O3 specific things if the core is O3
+    FullO3CPU<O3CPUImpl>* oldO3CPU = dynamic_cast<FullO3CPU<O3CPUImpl>*>(oldCPU);
+    if (oldO3CPU != NULL){
+        globalSeqNum = oldO3CPU->globalSeqNum;
+    } else {
+        panic("can only takeOverFrom an O3 cpu for now\n");
+    }
+
+
     // @todo: Figure out how to properly select the tid to put onto
     // the active threads list.
     ThreadID tid = 0;
diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh
--- a/src/cpu/o3/iew.hh
+++ b/src/cpu/o3/iew.hh
@@ -217,6 +217,9 @@
     /** Returns if the LSQ has any stores to writeback. */
     bool hasStoresToWB(ThreadID tid) { return ldstQueue.hasStoresToWB(tid); }
 
+    /** returns if the LSQ has any outstanding writebacks */
+    bool hasWbOutstanding() { return wbOutstanding != 0; }
+
     void incrWb(InstSeqNum &sn)
     {
         if (++wbOutstanding == wbMax)
diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh
+++ b/src/cpu/o3/lsq_unit.hh
@@ -335,6 +335,11 @@
         {
             std::memset(data, 0, sizeof(data));
         }
+        ~SQEntry()
+        {
+            //needed to clear RefCounted Insts
+            inst = NULL;
+        }
 
         /** Constructs a store queue entry for a given instruction. */
         SQEntry(DynInstPtr &_inst)