diff -r 9c632c3bfc8e -r 5b5f24bb9faf src/arch/power/isa/bitfields.isa
--- a/src/arch/power/isa/bitfields.isa	Wed Mar 21 23:26:29 2012 +0000
+++ b/src/arch/power/isa/bitfields.isa	Wed Mar 21 23:34:59 2012 +0000
@@ -75,8 +75,10 @@
 
 // Fields for FPSCR manipulation instructions
 def bitfield FLM           <24:17>;
-def bitfield L             <25>;
-def bitfield W             <16>;
+// Named so to avoid conflicts with potential template typenames
+def bitfield L_FIELD       <25>;
+// Named so to avoid conflicts with range_map.hh
+def bitfield W_FIELD       <16>;
 // Named so to avoid conflicts with range.hh
 def bitfield U_FIELD       <15:12>;
 
diff -r 9c632c3bfc8e -r 5b5f24bb9faf src/arch/power/isa/decoder.isa
--- a/src/arch/power/isa/decoder.isa	Wed Mar 21 23:26:29 2012 +0000
+++ b/src/arch/power/isa/decoder.isa	Wed Mar 21 23:34:59 2012 +0000
@@ -571,14 +571,15 @@
                 }});
                 583: mffs({{ Ft_uq = FPSCR; }});
                 134: mtfsfi({{
-                    FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W)), U_FIELD);
+                    FPSCR = insertCRField(FPSCR, BF + (8 * (1 - W_FIELD)),
+                                          U_FIELD);
                 }});
                 711: mtfsf({{
-                    if (L == 1) { FPSCR = Fb_uq; }
+                    if (L_FIELD == 1) { FPSCR = Fb_uq; }
                     else {
                         for (int i = 0; i < 8; ++i) {
                             if (bits(FLM, i) == 1) {
-                                int k = 4 * (i + (8 * (1 - W)));
+                                int k = 4 * (i + (8 * (1 - W_FIELD)));
                                 FPSCR = insertBits(FPSCR, k, k + 3,
                                                    bits(Fb_uq, k, k + 3));
                             }