diff -r d062cc7a8bdf -r 31d20d9ac126 src/arch/x86/isa/microops/regop.isa
--- a/src/arch/x86/isa/microops/regop.isa	Thu Apr 12 08:35:56 2012 -0400
+++ b/src/arch/x86/isa/microops/regop.isa	Thu Apr 12 19:36:51 2012 -0500
@@ -229,7 +229,7 @@
 
     class RegOpMeta(type):
         def buildCppClasses(self, name, Name, suffix, code, big_code, \
-                flag_code, cond_check, else_code, cond_control_flag_init):
+                flag_code, all_flags, cond_check, else_code, cond_control_flag_init):
 
             # Globals to stick the output in
             global header_output
@@ -255,6 +255,7 @@
                         matcher.sub(src2_name, code),
                         matcher.sub(src2_name, big_code),
                         matcher.sub(src2_name, flag_code),
+                        matcher.sub(src2_name, all_flags),
                         matcher.sub(src2_name, cond_check),
                         matcher.sub(src2_name, else_code),
                         matcher.sub(src2_name, cond_control_flag_init))
@@ -263,6 +264,7 @@
                         matcher.sub(imm_name, code),
                         matcher.sub(imm_name, big_code),
                         matcher.sub(imm_name, flag_code),
+                        matcher.sub(imm_name, all_flags),
                         matcher.sub(imm_name, cond_check),
                         matcher.sub(imm_name, else_code),
                         matcher.sub(imm_name, cond_control_flag_init))
@@ -270,9 +272,9 @@
 
             # If there's something optional to do with flags, generate
             # a version without it and fix up this version to use it.
-            if flag_code != "" or cond_check != "true":
+            if (flag_code != "" and all_flags != "true") or cond_check != "true":
                 self.buildCppClasses(name, Name, suffix,
-                        code, big_code, "", "true", else_code, "")
+                        code, big_code, "", "false", "true", else_code, "")
                 suffix = "Flags" + suffix
 
             # If psrc1 or psrc2 is used, we need to actually insert code to
@@ -346,13 +348,14 @@
                 code = cls.code
                 big_code = cls.big_code
                 flag_code = cls.flag_code
+                all_flags = cls.all_flags
                 cond_check = cls.cond_check
                 else_code = cls.else_code
                 cond_control_flag_init = cls.cond_control_flag_init
 
                 # Set up the C++ classes
                 mcls.buildCppClasses(cls, name, Name, "", code, big_code,
-                        flag_code, cond_check, else_code,
+                        flag_code, all_flags, cond_check, else_code,
                         cond_control_flag_init)
 
                 # Hook into the microassembler dict
@@ -381,6 +384,7 @@
         cond_check = "true"
         else_code = ";"
         cond_control_flag_init = ""
+        all_flags = "false"
 
         def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"):
             self.dest = dest
@@ -394,7 +398,12 @@
                 if not isinstance(flags, (list, tuple)):
                     raise Exception, "flags must be a list or tuple of flags"
                 self.ext = " | ".join(flags)
-                self.className += "Flags"
+                if len(flags) == 6:
+                    self.className += "AllFlags"
+                    self.all_flags = "true"
+                else:
+                    self.className += "Flags"
+                    self.all_flags = "false"
 
         def getAllocator(self, microFlags):
             if self.big_code != "":
@@ -450,11 +459,23 @@
         flag_code = \
             "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);"
 
+    class AllFlagRegOp(RegOp):
+        abstract = True
+        all_flags = "true"
+        flag_code = \
+            "ccFlagBits = genFlags(0, ext, result, psrc1, op2);"
+
     class SubRegOp(RegOp):
         abstract = True
         flag_code = \
             "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);"
 
+    class SubAllFlagsRegOp(RegOp):
+        abstract = True
+        all_flags = "true"
+        flag_code = \
+            "ccFlagBits = genFlags(0, ext, result, psrc1, ~op2, true);"
+
     class CondRegOp(RegOp):
         abstract = True
         cond_check = "checkCondition(ccFlagBits, ext)"
@@ -478,6 +499,10 @@
         code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
         big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
 
+    class AddAllFlags(AllFlagRegOp):
+        code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);'
+        big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);'
+
     class Or(LogicRegOp):
         code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);'
         big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);'
@@ -492,6 +517,16 @@
             DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
             '''
 
+    class AdcAllFlags(AllFlagRegOp):
+        code = '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize);
+            '''
+        big_code = '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8);
+            '''
+
     class Sbb(SubRegOp):
         code = '''
             CCFlagBits flags = ccFlagBits;
@@ -502,6 +537,16 @@
             DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
             '''
 
+    class SbbAllFlags(SubAllFlagsRegOp):
+        code = '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize);
+            '''
+        big_code = '''
+            CCFlagBits flags = ccFlagBits;
+            DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8);
+            '''
+
     class And(LogicRegOp):
         code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)'
         big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)'
@@ -510,6 +555,10 @@
         code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
         big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
 
+    class SubAllFlags(SubAllFlagsRegOp):
+        code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)'
+        big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)'
+
     class Xor(LogicRegOp):
         code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)'
         big_code = 'DestReg = result = (psrc1 ^ op2) & mask(dataSize * 8)'