diff -r 0bba1c59b4d1 -r 450fb40600bb src/arch/isa_parser.py --- a/src/arch/isa_parser.py Tue Apr 17 16:12:41 2012 -0500 +++ b/src/arch/isa_parser.py Sat Apr 21 15:05:24 2012 -0500 @@ -192,6 +192,8 @@ if operands.readPC: myDict['op_rd'] = '__parserAutoPCState = xc->pcState();\n' + \ myDict['op_rd'] + myDict['op_rd'] = 'uint32_t M5_VAR_USED srcRegIndex = 0;\n' + \ + myDict['op_rd'] # Compose the op_wb string. If we're going to write back the # PC state because we changed some of its elements, we'll need to @@ -413,11 +415,10 @@ subst_dict = {"name": self.base_name, "func": func, "reg_idx": self.reg_spec, - "ctype": self.ctype} - if hasattr(self, 'src_reg_idx'): - subst_dict['op_idx'] = self.src_reg_idx + "ctype": self.ctype, + "op_idx": "srcRegIndex"} code = self.read_code % subst_dict - return '%s = %s;\n' % (self.base_name, code) + return '%s = %s;\nsrcRegIndex++;\n' % (self.base_name, code) def buildWriteCode(self, func = None): subst_dict = {"name": self.base_name, @@ -519,8 +520,7 @@ def makeConstructor(self): c = '' if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s;' % \ - (self.src_reg_idx, self.reg_spec) + c += '\n\t_srcRegIdx[_numSrcRegs++] = %s;'% (self.reg_spec) if self.is_dest: c += '\n\t_destRegIdx[%d] = %s;' % \ (self.dest_reg_idx, self.reg_spec) @@ -531,7 +531,7 @@ error('Attempt to read integer register as FP') if self.read_code != None: return self.buildReadCode('readIntRegOperand') - int_reg_val = 'xc->readIntRegOperand(this, %d)' % self.src_reg_idx + int_reg_val = 'xc->readIntRegOperand(this, srcRegIndex++)' return '%s = %s;\n' % (self.base_name, int_reg_val) def makeWrite(self): @@ -557,8 +557,8 @@ def makeConstructor(self): c = '' if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s + FP_Base_DepTag;' % \ - (self.src_reg_idx, self.reg_spec) + c += '\n\t_srcRegIdx[_numSrcRegs++] = %s + FP_Base_DepTag;'% \ + (self.reg_spec) if self.is_dest: c += '\n\t_destRegIdx[%d] = %s + FP_Base_DepTag;' % \ (self.dest_reg_idx, self.reg_spec) @@ -572,8 +572,8 @@ func = 'readFloatRegOperandBits' if self.read_code != None: return self.buildReadCode(func) - return '%s = xc->%s(this, %d);\n' % \ - (self.base_name, func, self.src_reg_idx) + return '%s = xc->%s(this, srcRegIndex++);\n' % \ + (self.base_name, func) def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): @@ -600,8 +600,8 @@ def makeConstructor(self): c = '' if self.is_src: - c += '\n\t_srcRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ - (self.src_reg_idx, self.reg_spec) + c += '\n\t_srcRegIdx[_numSrcRegs++] = %s + Ctrl_Base_DepTag;'% \ + (self.reg_spec) if self.is_dest: c += '\n\t_destRegIdx[%d] = %s + Ctrl_Base_DepTag;' % \ (self.dest_reg_idx, self.reg_spec) @@ -613,8 +613,8 @@ error('Attempt to read control register as FP') if self.read_code != None: return self.buildReadCode('readMiscRegOperand') - return '%s = xc->readMiscRegOperand(this, %s);\n' % \ - (self.base_name, self.src_reg_idx) + return '%s = xc->readMiscRegOperand(this, srcRegIndex++);\n' % \ + (self.base_name) def makeWrite(self): if (self.ctype == 'float' or self.ctype == 'double'): @@ -902,9 +902,8 @@ self.snippets = snippets self.operands = OperandList(parser, compositeCode) - self.constructor = self.operands.concatAttrStrings('constructor') - self.constructor += \ - '\n\t_numSrcRegs = %d;' % self.operands.numSrcRegs + self.constructor = '\n\t_numSrcRegs = 0;' + self.constructor += self.operands.concatAttrStrings('constructor') self.constructor += \ '\n\t_numDestRegs = %d;' % self.operands.numDestRegs self.constructor += \