diff -r b1ebc06b7fe4 -r eb9b72c1c919 src/arch/x86/isa/microops/fpop.isa --- a/src/arch/x86/isa/microops/fpop.isa Sat Apr 21 15:27:09 2012 -0500 +++ b/src/arch/x86/isa/microops/fpop.isa Sun Apr 22 10:31:57 2012 -0500 @@ -186,14 +186,14 @@ else_code = ";" def __init__(self, dest, src1, src2, spm=0, \ - SetStatus=False, dataSize="env.dataSize"): + SetStatus=False, dataSize="env.dataSize", cc=0, ext=0): self.dest = dest self.src1 = src1 self.src2 = src2 self.spm = spm self.dataSize = dataSize - self.cc = 0 - self.ext = 0 + self.cc = cc + self.ext = ext if SetStatus: self.className += "Flags" if spm: @@ -214,7 +214,7 @@ def __init__(self, dest, src1, spm=0, \ SetStatus=False, dataSize="env.dataSize"): super(Movfp, self).__init__(dest, src1, "InstRegIndex(0)", \ - spm, SetStatus, dataSize) + spm, SetStatus, dataSize,1) code = 'FpDestReg_uqw = FpSrcReg1_uqw;' else_code = 'FpDestReg_uqw = FpDestReg_uqw;' cond_check = "checkCondition(ccFlagBits, src2)" @@ -274,8 +274,9 @@ class Compfp(FpOp): def __init__(self, src1, src2, spm=0, setStatus=False, \ dataSize="env.dataSize"): + ext = "OFBit | SFBit | AFBit |ZFBit | PFBit | CFBit" super(Compfp, self).__init__("InstRegIndex(FLOATREG_MICROFP0)", \ - src1, src2, spm, setStatus, dataSize) + src1, src2, spm, setStatus, dataSize, 0, ext) # This class sets the condition codes in rflags according to the # rules for comparing floating point. code = ''' diff -r b1ebc06b7fe4 -r eb9b72c1c919 src/arch/x86/isa/microops/regop.isa --- a/src/arch/x86/isa/microops/regop.isa Sat Apr 21 15:27:09 2012 -0500 +++ b/src/arch/x86/isa/microops/regop.isa Sun Apr 22 10:31:57 2012 -0500 @@ -369,8 +369,7 @@ microopClasses[name + 'i'] = cls return cls - - class RegOp(X86Microop): + class RegOp2(X86Microop): __metaclass__ = RegOpMeta # This class itself doesn't act as a microop abstract = True @@ -382,19 +381,29 @@ else_code = ";" cond_control_flag_init = "" - def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + def __init__(self, dest, src1, op2, RdFlags = None, WrFlags = None, dataSize = "env.dataSize"): self.dest = dest self.src1 = src1 self.op2 = op2 - self.flags = flags + self.RdFlags = RdFlags + self.WrFlags = WrFlags self.dataSize = dataSize - self.cc = 0 - if flags is None: - self.ext = 0 + + if RdFlags is None: + self.cc = "0" else: - if not isinstance(flags, (list, tuple)): - raise Exception, "flags must be a list or tuple of flags" - self.ext = " | ".join(flags) + if not isinstance(RdFlags, (list, tuple)): + raise Exception, "Read flags must be a list or tuple of flags" + self.cc = " | ".join(RdFlags) + + if WrFlags is None: + self.ext = "0" + else: + if not isinstance(WrFlags, (list, tuple)): + raise Exception, "WrFlags must be a list or tuple of flags" + self.ext = " | ".join(WrFlags) + + if self.ext != "0" or self.cc != "0": self.className += "Flags" def getAllocator(self, microFlags): @@ -434,7 +443,17 @@ "cc" : self.cc, "ext" : self.ext} return allocator - class LogicRegOp(RegOp): + class RegOp3(RegOp2): + abstract = True + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(RegOp3, self).__init__(dest, src1, op2, None, flags, dataSize) + + class RegOp4(RegOp2): + abstract = True + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(RegOp4, self).__init__(dest, src1, op2, flags, None, dataSize) + + class LogicRegOp(RegOp3): abstract = True flag_code = ''' //Don't have genFlags handle the OF or CF bits @@ -446,44 +465,36 @@ ccFlagBits &= ~(OFBit & ext); ''' - class FlagRegOp(RegOp): + class CondRegOp(RegOp4): abstract = True - flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" - - class SubRegOp(RegOp): - abstract = True - flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" - - class CondRegOp(RegOp): - abstract = True - cond_check = "checkCondition(ccFlagBits, ext)" + cond_check = "checkCondition(ccFlagBits, cc)" cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" - class RdRegOp(RegOp): + class RdRegOp(RegOp2): abstract = True def __init__(self, dest, src1=None, dataSize="env.dataSize"): if not src1: src1 = dest super(RdRegOp, self).__init__(dest, src1, \ - "InstRegIndex(NUM_INTREGS)", None, dataSize) + "InstRegIndex(NUM_INTREGS)", None, None, dataSize) - class WrRegOp(RegOp): + class WrRegOp(RegOp3): abstract = True def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): super(WrRegOp, self).__init__("InstRegIndex(NUM_INTREGS)", \ src1, src2, flags, dataSize) - class Add(FlagRegOp): + class Add(RegOp3): code = 'DestReg = merge(DestReg, result = (psrc1 + op2), dataSize);' big_code = 'DestReg = result = (psrc1 + op2) & mask(dataSize * 8);' + flag_code = \ + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" class Or(LogicRegOp): code = 'DestReg = merge(DestReg, result = (psrc1 | op2), dataSize);' big_code = 'DestReg = result = (psrc1 | op2) & mask(dataSize * 8);' - class Adc(FlagRegOp): + class Adc(RegOp2): code = ''' CCFlagBits flags = ccFlagBits; DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); @@ -492,8 +503,12 @@ CCFlagBits flags = ccFlagBits; DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); ''' + flag_code = \ + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(Adc, self).__init__(dest, src1, op2, ["CFBit"], flags, dataSize) - class Sbb(SubRegOp): + class Sbb(RegOp2): code = ''' CCFlagBits flags = ccFlagBits; DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); @@ -502,14 +517,22 @@ CCFlagBits flags = ccFlagBits; DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); ''' + flag_code = \ + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(Sbb, self).__init__(dest, src1, op2, ["CFBit"], flags, dataSize) + class And(LogicRegOp): code = 'DestReg = merge(DestReg, result = (psrc1 & op2), dataSize)' big_code = 'DestReg = result = (psrc1 & op2) & mask(dataSize * 8)' - class Sub(SubRegOp): + class Sub(RegOp3): code = 'DestReg = merge(DestReg, result = (psrc1 - op2), dataSize)' big_code = 'DestReg = result = (psrc1 - op2) & mask(dataSize * 8)' + flag_code = \ + "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" + class Xor(LogicRegOp): code = 'DestReg = merge(DestReg, result = (psrc1 ^ op2), dataSize)' @@ -569,11 +592,6 @@ big_code = 'DestReg = ProdLow & mask(dataSize * 8);' class Muleh(RdRegOp): - def __init__(self, dest, src1=None, flags=None, dataSize="env.dataSize"): - if not src1: - src1 = dest - super(RdRegOp, self).__init__(dest, src1, \ - "InstRegIndex(NUM_INTREGS)", flags, dataSize) code = 'DestReg = merge(SrcReg1, ProdHi, dataSize);' big_code = 'DestReg = ProdHi & mask(dataSize * 8);' @@ -602,7 +620,7 @@ ''' # Step divide - class Div2(RegOp): + class Div2(RegOp3): divCode = ''' uint64_t dividend = Remainder; uint64_t divisor = Divisor; @@ -678,7 +696,7 @@ # Shift instructions - class Sll(RegOp): + class Sll(RegOp3): code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); DestReg = merge(DestReg, psrc1 << shiftAmt, dataSize); @@ -711,7 +729,7 @@ } ''' - class Srl(RegOp): + class Srl(RegOp3): # Because what happens to the bits shift -in- on a right shift # is not defined in the C/C++ standard, we have to mask them out # to be sure they're zero. @@ -746,7 +764,7 @@ } ''' - class Sra(RegOp): + class Sra(RegOp3): # Because what happens to the bits shift -in- on a right shift # is not defined in the C/C++ standard, we have to sign extend # them manually to be sure. @@ -781,7 +799,7 @@ } ''' - class Ror(RegOp): + class Ror(RegOp3): code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); @@ -814,7 +832,7 @@ } ''' - class Rcr(RegOp): + class Rcr(RegOp2): code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); @@ -852,8 +870,10 @@ DestReg, psrc1, op2); } ''' + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(Rcr, self).__init__(dest, src1, op2, ["CFBit"], flags, dataSize) - class Rol(RegOp): + class Rol(RegOp3): code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); @@ -887,7 +907,7 @@ } ''' - class Rcl(RegOp): + class Rcl(RegOp2): code = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); @@ -925,8 +945,10 @@ DestReg, psrc1, op2); } ''' + def __init__(self, dest, src1, op2, flags = None, dataSize = "env.dataSize"): + super(Rcl, self).__init__(dest, src1, op2, ["CFBit"], flags, dataSize) - class Sld(RegOp): + class Sld(RegOp3): sldCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; @@ -974,7 +996,7 @@ } ''' - class Srd(RegOp): + class Srd(RegOp3): srdCode = ''' uint8_t shiftAmt = (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t dataBits = dataSize * 8; @@ -1031,15 +1053,23 @@ class Mdb(WrRegOp): code = 'DoubleBits = psrc1 ^ op2;' - class Wrip(WrRegOp, CondRegOp): + class Wrip(CondRegOp): code = 'NRIP = psrc1 + sop2 + CSBase;' else_code = "NRIP = NRIP;" + def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): + super(Wrip, self).__init__("InstRegIndex(NUM_INTREGS)", \ + src1, src2, flags, dataSize) - class Wruflags(WrRegOp): - code = 'ccFlagBits = psrc1 ^ op2' + class Wruflags(RegOp3): + code = '' + flag_code = 'ccFlagBits = psrc1 ^ op2' + def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): + super(Wruflags, self).__init__("InstRegIndex(NUM_INTREGS)", \ + src1, src2, ["CFBit"], dataSize) - class Wrflags(WrRegOp): - code = ''' + class Wrflags(RegOp3): + code = '' + flag_code = ''' MiscReg newFlags = psrc1 ^ op2; MiscReg userFlagMask = 0xDD5; // Get only the user flags @@ -1047,57 +1077,72 @@ // Get everything else nccFlagBits = newFlags & ~userFlagMask; ''' + def __init__(self, src1, src2, flags=None, dataSize="env.dataSize"): + super(Wrflags, self).__init__("InstRegIndex(NUM_INTREGS)", \ + src1, src2, ["CFBit"], dataSize) class Rdip(RdRegOp): code = 'DestReg = NRIP - CSBase;' - class Ruflags(RdRegOp): - code = 'DestReg = ccFlagBits' + class Ruflags(RegOp4): + code = '' + flag_code = 'DestReg = ccFlagBits' + def __init__(self, dest, src1=None, dataSize="env.dataSize"): + if not src1: + src1 = dest + super(Ruflags, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", ["CFBit"], dataSize) - class Rflags(RdRegOp): - code = 'DestReg = ccFlagBits | nccFlagBits' + class Rflags(RegOp4): + code = '' + flag_code = 'DestReg = ccFlagBits | nccFlagBits' + def __init__(self, dest, src1=None, dataSize="env.dataSize"): + if not src1: + src1 = dest + super(Rflags, self).__init__(dest, src1, \ + "InstRegIndex(NUM_INTREGS)", ["CFBit"], dataSize) - class Ruflag(RegOp): + class Ruflag(RegOp2): code = ''' int flag = bits(ccFlagBits, imm8); DestReg = merge(DestReg, flag, dataSize); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); ''' big_code = ''' int flag = bits(ccFlagBits, imm8); DestReg = flag & mask(dataSize * 8); + ''' + flag_code = ''' ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Ruflag, self).__init__(dest, \ - "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) + "InstRegIndex(NUM_INTREGS)", imm, ["CFBit"], flags, dataSize) - class Rflag(RegOp): + class Rflag(RegOp2): code = ''' MiscReg flagMask = 0x3F7FDD5; MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; int flag = bits(flags, imm8); DestReg = merge(DestReg, flag, dataSize); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); ''' big_code = ''' MiscReg flagMask = 0x3F7FDD5; MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; int flag = bits(flags, imm8); DestReg = flag & mask(dataSize * 8); + ''' + flag_code = ''' ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : (ccFlagBits & ~EZFBit); ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): super(Rflag, self).__init__(dest, \ - "InstRegIndex(NUM_INTREGS)", imm, flags, dataSize) + "InstRegIndex(NUM_INTREGS)", imm, ["CFBit"], flags, dataSize) - class Sext(RegOp): + class Sext(RegOp3): code = ''' IntReg val = psrc1; // Mask the bit position so that it wraps. @@ -1125,11 +1170,11 @@ (ext & (CFBit | ECFBit | ZFBit | EZFBit)); ''' - class Zext(RegOp): + class Zext(RegOp3): code = 'DestReg = merge(DestReg, bits(psrc1, op2, 0), dataSize);' big_code = 'DestReg = bits(psrc1, op2, 0) & mask(dataSize * 8);' - class Rddr(RegOp): + class Rddr(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rddr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1147,7 +1192,7 @@ code = rdrCode % "DestReg = merge(DestReg, DebugSrc1, dataSize);" big_code = rdrCode % "DestReg = DebugSrc1 & mask(dataSize * 8);" - class Wrdr(RegOp): + class Wrdr(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Wrdr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1166,7 +1211,7 @@ } ''' - class Rdcr(RegOp): + class Rdcr(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rdcr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1180,7 +1225,7 @@ code = rdcrCode % "DestReg = merge(DestReg, ControlSrc1, dataSize);" big_code = rdcrCode % "DestReg = ControlSrc1 & mask(dataSize * 8);" - class Wrcr(RegOp): + class Wrcr(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Wrcr, self).__init__(dest, \ src1, "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1276,7 +1321,7 @@ code = 'DestReg = merge(DestReg, SegSelSrc1, dataSize);' big_code = 'DestReg = SegSelSrc1 & mask(dataSize * 8);' - class Rdval(RegOp): + class Rdval(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Rdval, self).__init__(dest, src1, \ "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1284,7 +1329,7 @@ DestReg = MiscRegSrc1; ''' - class Wrval(RegOp): + class Wrval(RegOp3): def __init__(self, dest, src1, flags=None, dataSize="env.dataSize"): super(Wrval, self).__init__(dest, src1, \ "InstRegIndex(NUM_INTREGS)", flags, dataSize) @@ -1292,7 +1337,7 @@ MiscRegDest = SrcReg1; ''' - class Chks(RegOp): + class Chks(RegOp3): def __init__(self, dest, src1, src2=0, flags=None, dataSize="env.dataSize"): super(Chks, self).__init__(dest, @@ -1409,7 +1454,7 @@ ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); ''' - class Wrdh(RegOp): + class Wrdh(RegOp3): code = ''' SegDescriptor desc = SrcReg1; @@ -1449,7 +1494,7 @@ DestReg = M5Reg; ''' - class Wrdl(RegOp): + class Wrdl(RegOp3): code = ''' SegDescriptor desc = SrcReg1; SegSelector selector = SrcReg2;