diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/debug.isa --- a/src/arch/x86/isa/microops/debug.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/debug.isa Fri May 18 13:52:36 2012 -0500 @@ -141,7 +141,8 @@ {"code": "", "func": func, "func_num": "GenericISA::M5DebugFault::%s" % func_num, - "cond_test": "checkCondition(ccFlagBits, cc)"}) + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + uccFlagBits, cc)"}) exec_output += MicroDebugExecute.subst(iop) header_output += MicroDebugDeclare.subst(iop) decoder_output += MicroDebugConstructor.subst(iop) diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/fpop.isa --- a/src/arch/x86/isa/microops/fpop.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/fpop.isa Fri May 18 13:52:36 2012 -0500 @@ -215,7 +215,8 @@ spm, SetStatus, dataSize) code = 'FpDestReg_uqw = FpSrcReg1_uqw;' else_code = 'FpDestReg_uqw = FpDestReg_uqw;' - cond_check = "checkCondition(ccFlagBits, src2)" + cond_check = "checkCondition(ccFlagBits | cfofBits | uccFlagBits, \ + src2)" class Xorfp(FpOp): code = 'FpDestReg_uqw = FpSrcReg1_uqw ^ FpSrcReg2_uqw;' @@ -283,12 +284,15 @@ // Less than 0 0 1 // Equal 1 0 0 // OF = SF = AF = 0 - ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | - ZFBit | PFBit | CFBit); - if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2)) - ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); + ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit); + cfofBits = cfofBits & ~(OFBit | CFBit); + + if (std::isnan(FpSrcReg1) || std::isnan(FpSrcReg2)) { + ccFlagBits = ccFlagBits | (ZFBit | PFBit); + cfofBits = cfofBits | (CFBit); + } else if(FpSrcReg1 < FpSrcReg2) - ccFlagBits = ccFlagBits | CFBit; + cfofBits = cfofBits | CFBit; else if(FpSrcReg1 == FpSrcReg2) ccFlagBits = ccFlagBits | ZFBit; ''' diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/mediaop.isa --- a/src/arch/x86/isa/microops/mediaop.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/mediaop.isa Fri May 18 13:52:36 2012 -0500 @@ -1490,12 +1490,15 @@ // Less than 0 0 1 // Equal 1 0 0 // OF = SF = AF = 0 - ccFlagBits = ccFlagBits & ~(OFBit | SFBit | AFBit | - ZFBit | PFBit | CFBit); - if (std::isnan(arg1) || std::isnan(arg2)) - ccFlagBits = ccFlagBits | (ZFBit | PFBit | CFBit); + ccFlagBits = ccFlagBits & ~(SFBit | AFBit | ZFBit | PFBit); + cfofBits = cfofBits & ~(OFBit | CFBit); + + if (std::isnan(arg1) || std::isnan(arg2)) { + ccFlagBits = ccFlagBits | (ZFBit | PFBit); + cfofBits = cfofBits | (CFBit); + } else if(arg1 < arg2) - ccFlagBits = ccFlagBits | CFBit; + cfofBits = cfofBits | CFBit; else if(arg1 == arg2) ccFlagBits = ccFlagBits | ZFBit; ''' diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/regop.isa --- a/src/arch/x86/isa/microops/regop.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/regop.isa Fri May 18 13:52:36 2012 -0500 @@ -438,26 +438,39 @@ flag_code = ''' //Don't have genFlags handle the OF or CF bits uint64_t mask = CFBit | ECFBit | OFBit; - ccFlagBits = genFlags(ccFlagBits, ext & ~mask, result, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, ext & ~mask, + result, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; + //If a logic microop wants to set these, it wants to set them to 0. - ccFlagBits &= ~(CFBit & ext); - ccFlagBits &= ~(ECFBit & ext); - ccFlagBits &= ~(OFBit & ext); + cfofBits = cfofBits & ~((CFBit | OFBit) & ext); + uccFlagBits = uccFlagBits & ~(ECFBit & ext); ''' class FlagRegOp(RegOp): abstract = True - flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, op2);" + flag_code = ''' + ccFlagBits = genFlags(ccFlagBits | cfofBits | uccFlagBits, ext, + result, psrc1, op2); + cfofBits = ccFlagBits & cfofMask; + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; + ''' class SubRegOp(RegOp): abstract = True - flag_code = \ - "ccFlagBits = genFlags(ccFlagBits, ext, result, psrc1, ~op2, true);" + flag_code = ''' + ccFlagBits = genFlags(ccFlagBits | cfofBits | uccFlagBits, ext, + result, psrc1, ~op2, true); + cfofBits = ccFlagBits & cfofMask; + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; + ''' class CondRegOp(RegOp): abstract = True - cond_check = "checkCondition(ccFlagBits, ext)" + cond_check = "checkCondition(ccFlagBits | cfofBits | uccFlagBits, ext)" cond_control_flag_init = "flags[IsCondControl] = flags[IsControl];" class RdRegOp(RegOp): @@ -484,21 +497,21 @@ class Adc(FlagRegOp): code = ''' - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; DestReg = merge(DestReg, result = (psrc1 + op2 + flags.cf), dataSize); ''' big_code = ''' - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; DestReg = result = (psrc1 + op2 + flags.cf) & mask(dataSize * 8); ''' class Sbb(SubRegOp): code = ''' - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; DestReg = merge(DestReg, result = (psrc1 - op2 - flags.cf), dataSize); ''' big_code = ''' - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; DestReg = result = (psrc1 - op2 - flags.cf) & mask(dataSize * 8); ''' @@ -536,9 +549,11 @@ flag_code = ''' if ((-ProdHi & mask(dataSize * 8)) != bits(ProdLow, dataSize * 8 - 1)) { - ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); + cfofBits = cfofBits | (ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); } else { - ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); } ''' @@ -557,9 +572,11 @@ ''' flag_code = ''' if (ProdHi) { - ccFlagBits = ccFlagBits | (ext & (CFBit | OFBit | ECFBit)); + cfofBits = cfofBits | (ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); } else { - ccFlagBits = ccFlagBits & ~(ext & (CFBit | OFBit | ECFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); } ''' @@ -658,9 +675,9 @@ big_code = divCode % "DestReg = remaining & mask(dataSize * 8);" flag_code = ''' if (remaining == 0) - ccFlagBits = ccFlagBits | (ext & EZFBit); + uccFlagBits = uccFlagBits | (ext & EZFBit); else - ccFlagBits = ccFlagBits & ~(ext & EZFBit); + uccFlagBits = uccFlagBits & ~(ext & EZFBit); ''' class Divq(RdRegOp): @@ -691,7 +708,8 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); int CFBits = 0; //Figure out if we -would- set the CF bits if requested. if (shiftAmt <= dataSize * 8 && @@ -699,14 +717,18 @@ CFBits = 1; } //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && CFBits) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + if ((ext & (CFBit | ECFBit)) && CFBits) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (CFBits ^ bits(DestReg, dataSize * 8 - 1))) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -729,19 +751,23 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); //If some combination of the CF bits need to be set, set them. if ((ext & (CFBit | ECFBit)) && shiftAmt <= dataSize * 8 && bits(SrcReg1, shiftAmt - 1)) { - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); } //Figure out what the OF bit should be. if ((ext & OFBit) && bits(SrcReg1, dataSize * 8 - 1)) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -766,17 +792,21 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); //If some combination of the CF bits need to be set, set them. uint8_t effectiveShift = (shiftAmt <= dataSize * 8) ? shiftAmt : (dataSize * 8); if ((ext & (CFBit | ECFBit)) && bits(SrcReg1, effectiveShift - 1)) { - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); } //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -797,19 +827,24 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); //Find the most and second most significant bits of the result. int msb = bits(DestReg, dataSize * 8 - 1); int smsb = bits(DestReg, dataSize * 8 - 2); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && msb) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + if ((ext & (CFBit | ECFBit)) && msb) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (msb ^ smsb)) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -819,7 +854,7 @@ (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); if (realShiftAmt) { - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; uint64_t top = flags.cf << (dataSize * 8 - realShiftAmt); if (realShiftAmt > 1) top |= psrc1 << (dataSize * 8 - realShiftAmt + 1); @@ -831,24 +866,28 @@ flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { - int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; + int origCFBit = (cfofBits & CFBit) ? 1 : 0; //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); //Figure out what the OF bit should be. if ((ext & OFBit) && (origCFBit ^ bits(SrcReg1, dataSize * 8 - 1))) { - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; } //If some combination of the CF bits need to be set, set them. if ((ext & (CFBit | ECFBit)) && (realShiftAmt == 0) ? origCFBit : bits(SrcReg1, realShiftAmt - 1)) { - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); } //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -870,19 +909,24 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); //The CF bits, if set, would be set to the lsb of the result. int lsb = DestReg & 0x1; int msb = bits(DestReg, dataSize * 8 - 1); //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && lsb) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + if ((ext & (CFBit | ECFBit)) && lsb) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (msb ^ lsb)) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -892,7 +936,7 @@ (op2 & ((dataSize == 8) ? mask(6) : mask(5))); uint8_t realShiftAmt = shiftAmt % (dataSize * 8 + 1); if (realShiftAmt) { - CCFlagBits flags = ccFlagBits; + CCFlagBits flags = cfofBits; uint64_t top = psrc1 << realShiftAmt; uint64_t bottom = flags.cf << (realShiftAmt - 1); if(shiftAmt > 1) @@ -906,22 +950,27 @@ flag_code = ''' // If the shift amount is zero, no flags should be modified. if (shiftAmt) { - int origCFBit = (ccFlagBits & CFBit) ? 1 : 0; + int origCFBit = (cfofBits & CFBit) ? 1 : 0; //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); int msb = bits(DestReg, dataSize * 8 - 1); int CFBits = bits(SrcReg1, dataSize * 8 - realShiftAmt); //If some combination of the CF bits need to be set, set them. if ((ext & (CFBit | ECFBit)) && - (realShiftAmt == 0) ? origCFBit : CFBits) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + (realShiftAmt == 0) ? origCFBit : CFBits) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (msb ^ CFBits)) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -949,7 +998,8 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); int CFBits = 0; //Figure out if we -would- set the CF bits if requested. if ((realShiftAmt == 0 && @@ -961,15 +1011,19 @@ CFBits = 1; } //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && CFBits) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + if ((ext & (CFBit | ECFBit)) && CFBits) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ bits(result, dataBits - 1))) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -1003,7 +1057,8 @@ if (shiftAmt) { //Zero out any flags we might modify. This way we only have to //worry about setting them. - ccFlagBits = ccFlagBits & ~(ext & (CFBit | ECFBit | OFBit)); + cfofBits = cfofBits & ~(ext & (CFBit | OFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit)); int CFBits = 0; //If some combination of the CF bits need to be set, set them. if ((realShiftAmt == 0 && @@ -1015,15 +1070,19 @@ CFBits = 1; } //If some combination of the CF bits need to be set, set them. - if ((ext & (CFBit | ECFBit)) && CFBits) - ccFlagBits = ccFlagBits | (ext & (CFBit | ECFBit)); + if ((ext & (CFBit | ECFBit)) && CFBits) { + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit)); + } //Figure out what the OF bit should be. if ((ext & OFBit) && (bits(SrcReg1, dataBits - 1) ^ bits(result, dataBits - 1))) - ccFlagBits = ccFlagBits | OFBit; + cfofBits = cfofBits | OFBit; //Use the regular mechanisms to calculate the other flags. - ccFlagBits = genFlags(ccFlagBits, ext & ~(CFBit | ECFBit | OFBit), - DestReg, psrc1, op2); + ccFlagBits = genFlags(ccFlagBits | uccFlagBits, + ext & ~(CFBit | ECFBit | OFBit), DestReg, psrc1, op2); + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; } ''' @@ -1035,14 +1094,23 @@ else_code = "NRIP = NRIP;" class Wruflags(WrRegOp): - code = 'ccFlagBits = psrc1 ^ op2' + code = ''' + ccFlagBits = psrc1 ^ op2; + cfofBits = ccFlagBits & cfofMask; + uccFlagBits = ccFlagBits & uccFlagMask; + ccFlagBits = ccFlagBits & ccFlagMask; + ''' class Wrflags(WrRegOp): code = ''' MiscReg newFlags = psrc1 ^ op2; MiscReg userFlagMask = 0xDD5; + // Get only the user flags - ccFlagBits = newFlags & userFlagMask; + ccFlagBits = newFlags & ccFlagMask; + cfofBits = newFlags & cfofMask; + uccFlagBits = 0; + // Get everything else nccFlagBits = newFlags & ~userFlagMask; ''' @@ -1051,23 +1119,23 @@ code = 'DestReg = NRIP - CSBase;' class Ruflags(RdRegOp): - code = 'DestReg = ccFlagBits' + code = 'DestReg = ccFlagBits | cfofBits | uccFlagBits;' class Rflags(RdRegOp): - code = 'DestReg = ccFlagBits | nccFlagBits' + code = 'DestReg = ccFlagBits | cfofBits | uccFlagBits | nccFlagBits' class Ruflag(RegOp): code = ''' - int flag = bits(ccFlagBits, imm8); + int flag = bits(ccFlagBits | cfofBits | uccFlagBits, imm8); DestReg = merge(DestReg, flag, dataSize); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); + uccFlagBits = (flag == 0) ? (uccFlagBits | EZFBit) : + (uccFlagBits & ~EZFBit); ''' big_code = ''' - int flag = bits(ccFlagBits, imm8); + int flag = bits(ccFlagBits | cfofBits | uccFlagBits, imm8); DestReg = flag & mask(dataSize * 8); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); + uccFlagBits = (flag == 0) ? (uccFlagBits | EZFBit) : + (uccFlagBits & ~EZFBit); ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): @@ -1077,19 +1145,23 @@ class Rflag(RegOp): code = ''' MiscReg flagMask = 0x3F7FDD5; - MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; + MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | + uccFlagBits) & flagMask; + int flag = bits(flags, imm8); DestReg = merge(DestReg, flag, dataSize); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); + uccFlagBits = (flag == 0) ? (uccFlagBits | EZFBit) : + (uccFlagBits & ~EZFBit); ''' big_code = ''' MiscReg flagMask = 0x3F7FDD5; - MiscReg flags = (nccFlagBits | ccFlagBits) & flagMask; + MiscReg flags = (nccFlagBits | ccFlagBits | cfofBits | + uccFlagBits) & flagMask; + int flag = bits(flags, imm8); DestReg = flag & mask(dataSize * 8); - ccFlagBits = (flag == 0) ? (ccFlagBits | EZFBit) : - (ccFlagBits & ~EZFBit); + uccFlagBits = (flag == 0) ? (uccFlagBits | EZFBit) : + (uccFlagBits & ~EZFBit); ''' def __init__(self, dest, imm, flags=None, \ dataSize="env.dataSize"): @@ -1116,12 +1188,16 @@ DestReg = val & mask(dataSize * 8); ''' flag_code = ''' - if (!sign_bit) - ccFlagBits = ccFlagBits & - ~(ext & (CFBit | ECFBit | ZFBit | EZFBit)); - else - ccFlagBits = ccFlagBits | - (ext & (CFBit | ECFBit | ZFBit | EZFBit)); + if (!sign_bit) { + ccFlagBits = ccFlagBits & ~(ext & (ZFBit)); + cfofBits = cfofBits & ~(ext & (CFBit)); + uccFlagBits = uccFlagBits & ~(ext & (ECFBit | EZFBit)); + } + else { + ccFlagBits = ccFlagBits | (ext & (ZFBit)); + cfofBits = cfofBits | (ext & (CFBit)); + uccFlagBits = uccFlagBits | (ext & (ECFBit | EZFBit)); + } ''' class Zext(RegOp): @@ -1403,9 +1479,12 @@ ''' flag_code = ''' // Check for a NULL selector and set ZF,EZF appropriately. - ccFlagBits = ccFlagBits & ~(ext & (ZFBit | EZFBit)); - if (!selector.si && !selector.ti) - ccFlagBits = ccFlagBits | (ext & (ZFBit | EZFBit)); + ccFlagBits = ccFlagBits & ~(ext & (ZFBit)); + uccFlagBits = uccFlagBits & ~(ext & (EZFBit)); + if (!selector.si && !selector.ti) { + ccFlagBits = ccFlagBits | (ext & (ZFBit)); + uccFlagBits = uccFlagBits | (ext & (EZFBit)); + } ''' class Wrdh(RegOp): diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/seqop.isa --- a/src/arch/x86/isa/microops/seqop.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/seqop.isa Fri May 18 13:52:36 2012 -0500 @@ -172,7 +172,8 @@ iop = InstObjParams("br", "MicroBranchFlags", "SeqOpBase", {"code": "nuIP = target;", "else_code": "nuIP = nuIP;", - "cond_test": "checkCondition(ccFlagBits, cc)", + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + uccFlagBits, cc)", "cond_control_flag_init": "flags[IsCondControl] = true"}) exec_output += SeqOpExecute.subst(iop) header_output += SeqOpDeclare.subst(iop) @@ -189,7 +190,8 @@ iop = InstObjParams("eret", "EretFlags", "SeqOpBase", {"code": "", "else_code": "", - "cond_test": "checkCondition(ccFlagBits, cc)", + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + uccFlagBits, cc)", "cond_control_flag_init": ""}) exec_output += SeqOpExecute.subst(iop) header_output += SeqOpDeclare.subst(iop) diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/microops/specop.isa --- a/src/arch/x86/isa/microops/specop.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/microops/specop.isa Fri May 18 13:52:36 2012 -0500 @@ -181,7 +181,8 @@ iop = InstObjParams("fault", "MicroFaultFlags", "MicroFaultBase", {"code": "", - "cond_test": "checkCondition(ccFlagBits, cc)"}) + "cond_test": "checkCondition(ccFlagBits | cfofBits | \ + uccFlagBits, cc)"}) exec_output = MicroFaultExecute.subst(iop) header_output = MicroFaultDeclare.subst(iop) decoder_output = MicroFaultConstructor.subst(iop) diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/isa/operands.isa --- a/src/arch/x86/isa/operands.isa Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/isa/operands.isa Fri May 18 13:52:36 2012 -0500 @@ -119,10 +119,12 @@ # This holds the condition code portion of the flag register. The # nccFlagBits version holds the rest. 'ccFlagBits': intReg('INTREG_PSEUDO(0)', 60), + 'cfofBits': intReg('INTREG_PSEUDO(1)', 61), + 'uccFlagBits': intReg('INTREG_PSEUDO(2)', 62), # These register should needs to be more protected so that later # instructions don't map their indexes with an old value. - 'nccFlagBits': controlReg('MISCREG_RFLAGS', 61), - 'TOP': controlReg('MISCREG_X87_TOP', 62, ctype='ub'), + 'nccFlagBits': controlReg('MISCREG_RFLAGS', 63), + 'TOP': controlReg('MISCREG_X87_TOP', 64, ctype='ub'), # The segment base as used by memory instructions. 'SegBase': controlReg('MISCREG_SEG_EFF_BASE(segment)', 70), diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/regs/misc.hh --- a/src/arch/x86/regs/misc.hh Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/regs/misc.hh Fri May 18 13:52:36 2012 -0500 @@ -64,6 +64,10 @@ OFBit = 1 << 11 }; + const uint32_t uccFlagMask = ECFBit | EZFBit; + const uint32_t cfofMask = CFBit | OFBit; + const uint32_t ccFlagMask = PFBit | AFBit | ZFBit | SFBit | DFBit; + enum RFLAGBit { TFBit = 1 << 8, IFBit = 1 << 9, diff -r 7100059f7bfd -r eeef71e38de5 src/arch/x86/x86_traits.hh --- a/src/arch/x86/x86_traits.hh Mon May 14 20:31:33 2012 -0500 +++ b/src/arch/x86/x86_traits.hh Fri May 18 13:52:36 2012 -0500 @@ -46,7 +46,7 @@ { const int NumMicroIntRegs = 16; - const int NumPseudoIntRegs = 1; + const int NumPseudoIntRegs = 3; //1. The condition code bits of the rflags register. const int NumImplicitIntRegs = 6; //1. The lower part of the result of multiplication.