diff -r 44a7c9a33484 -r 5119c5ee2bea src/arch/arm/miscregs.cc
--- a/src/arch/arm/miscregs.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/arch/arm/miscregs.cc	Wed May 02 16:08:14 2012 -0400
@@ -392,6 +392,7 @@
                   case 7:
                     return MISCREG_PMCEID1;
                 }
+                break;
               case 13:
                 switch (opc2) {
                   case 0:
@@ -401,6 +402,7 @@
                   case 2:
                     return MISCREG_PMXEVCNTR;
                 }
+                break;
               case 14:
                 switch (opc2) {
                   case 0:
@@ -410,6 +412,7 @@
                   case 2:
                     return MISCREG_PMINTENCLR;
                 }
+                break;
             }
         } else if (opc1 == 1) {
             switch (crm) {
@@ -422,6 +425,7 @@
                          crn,crm, opc1,opc2);
                     break;
                 }
+                break;
               default:
                 return MISCREG_L2LATENCY;
             }
diff -r 44a7c9a33484 -r 5119c5ee2bea src/base/output.cc
--- a/src/base/output.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/base/output.cc	Wed May 02 16:08:14 2012 -0400
@@ -160,7 +160,7 @@
 
     string filename = resolve(name);
     ios_base::openmode mode =
-        ios::trunc | binary ?  ios::binary : (ios::openmode)0;
+        ios::trunc | (binary ? ios::binary : (ios::openmode)0);
     file = openFile(filename, mode);
 
     return file;
diff -r 44a7c9a33484 -r 5119c5ee2bea src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/cpu/checker/cpu.cc	Wed May 02 16:08:14 2012 -0400
@@ -166,6 +166,8 @@
             checked_flags = true;
         }
 
+        bool was_prefetch = false;
+
         // Now do the access
         if (fault == NoFault &&
             !memReq->getFlags().isSet(Request::NO_ACCESS)) {
@@ -184,13 +186,15 @@
                 memcpy(data, unverifiedMemData, size);
             }
 
+            was_prefetch = memReq->isPrefetch();
+
             delete memReq;
             memReq = NULL;
             delete pkt;
         }
 
         if (fault != NoFault) {
-            if (memReq->isPrefetch()) {
+            if (was_prefetch) {
                 fault = NoFault;
             }
             delete memReq;
@@ -264,13 +268,14 @@
          * enabled.  This is left as future work for the Checker: LSQ snooping
          * and memory validation after stores have committed.
          */
+        bool was_prefetch = memReq->isPrefetch();
 
         delete memReq;
 
         //If we don't need to access a second cache line, stop now.
         if (fault != NoFault || secondAddr <= addr)
         {
-            if (fault != NoFault && memReq->isPrefetch()) {
+            if (fault != NoFault && was_prefetch) {
               fault = NoFault;
             }
             break;
diff -r 44a7c9a33484 -r 5119c5ee2bea src/cpu/pc_event.cc
--- a/src/cpu/pc_event.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/cpu/pc_event.cc	Wed May 02 16:08:14 2012 -0400
@@ -56,13 +56,17 @@
 {
     int removed = 0;
     range_t range = equal_range(event);
-    for (iterator i = range.first; i != range.second; ++i) {
+    iterator i = range.first;
+    while (i != range.second) {
         if (*i == event) {
             DPRINTF(PCEvent, "PC based event removed at %#x: %s\n",
                     event->pc(), event->descr());
-            pc_map.erase(i);
+            i = pc_map.erase(i);
             ++removed;
+        } else {
+            i++;
         }
+
     }
 
     return removed > 0;
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/arm/gic.cc
--- a/src/dev/arm/gic.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/arm/gic.cc	Wed May 02 16:08:14 2012 -0400
@@ -193,10 +193,12 @@
             pkt->set<uint8_t>(int_p[int_num]);
             break;
           case 2:
+            assert((int_num + 1) < (SGI_MAX + PPI_MAX));
             pkt->set<uint16_t>(int_p[int_num] |
                                int_p[int_num+1] << 8);
             break;
           case 4:
+            assert((int_num + 3) < (SGI_MAX + PPI_MAX));
             pkt->set<uint32_t>(int_p[int_num] |
                                int_p[int_num+1] << 8 |
                                int_p[int_num+2] << 16 |
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/arm/rtc_pl031.cc
--- a/src/dev/arm/rtc_pl031.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/arm/rtc_pl031.cc	Wed May 02 16:08:14 2012 -0400
@@ -191,7 +191,7 @@
     rawInt = true;
     bool old_pending = pendingInt;
     pendingInt = maskInt & rawInt;
-    if (pendingInt && ~old_pending) {
+    if (pendingInt && !old_pending) {
         DPRINTF(Timer, "-- Causing interrupt\n");
         gic->sendInt(intNum);
     }
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/arm/rv_ctrl.cc
--- a/src/dev/arm/rv_ctrl.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/arm/rv_ctrl.cc	Wed May 02 16:08:14 2012 -0400
@@ -105,6 +105,7 @@
         break;
       case CfgStat:
         pkt->set<uint32_t>(1);
+        break;
       default:
         warn("Tried to read RealView I/O at offset %#x that doesn't exist\n",
              daddr);
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/arm/timer_cpulocal.cc
--- a/src/dev/arm/timer_cpulocal.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/arm/timer_cpulocal.cc	Wed May 02 16:08:14 2012 -0400
@@ -291,7 +291,7 @@
     bool old_pending = pendingIntTimer;
     if (timerControl.intEnable)
         pendingIntTimer = true;
-    if (pendingIntTimer && ~old_pending) {
+    if (pendingIntTimer && !old_pending) {
         DPRINTF(Timer, "-- Causing interrupt\n");
         parent->gic->sendPPInt(intNumTimer, cpuNum);
     }
@@ -322,7 +322,7 @@
         //XXX: Should we ever support a true watchdog reset?
     }
 
-    if (pendingIntWatchdog && ~old_pending) {
+    if (pendingIntWatchdog && !old_pending) {
         DPRINTF(Timer, "-- Causing interrupt\n");
         parent->gic->sendPPInt(intNumWatchdog, cpuNum);
     }
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/arm/timer_sp804.cc
--- a/src/dev/arm/timer_sp804.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/arm/timer_sp804.cc	Wed May 02 16:08:14 2012 -0400
@@ -205,7 +205,7 @@
     bool old_pending = pendingInt;
     if (control.intEnable)
         pendingInt = true;
-    if (pendingInt && ~old_pending) {
+    if (pendingInt && !old_pending) {
         DPRINTF(Timer, "-- Causing interrupt\n");
         parent->gic->sendInt(intNum);
     }
diff -r 44a7c9a33484 -r 5119c5ee2bea src/dev/simple_disk.cc
--- a/src/dev/simple_disk.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/dev/simple_disk.cc	Wed May 02 16:08:14 2012 -0400
@@ -75,7 +75,7 @@
     DPRINTF(SimpleDisk, "read  block=%#x len=%d\n", (uint64_t)block, count);
     DDUMP(SimpleDiskData, data, count);
 
-    delete data;
+    delete [] data;
 }
 
 void
diff -r 44a7c9a33484 -r 5119c5ee2bea src/mem/abstract_mem.cc
--- a/src/mem/abstract_mem.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/mem/abstract_mem.cc	Wed May 02 16:08:14 2012 -0400
@@ -390,6 +390,7 @@
     } else if (pkt->isPrint()) {
         Packet::PrintReqState *prs =
             dynamic_cast<Packet::PrintReqState*>(pkt->senderState);
+        assert(prs);
         // Need to call printLabels() explicitly since we're not going
         // through printObj().
         prs->printLabels();
diff -r 44a7c9a33484 -r 5119c5ee2bea src/mem/cache/cache_impl.hh
--- a/src/mem/cache/cache_impl.hh	Wed May 02 16:07:35 2012 -0400
+++ b/src/mem/cache/cache_impl.hh	Wed May 02 16:08:14 2012 -0400
@@ -1294,8 +1294,10 @@
                 pkt->getAddr());
 
         //Look through writebacks for any non-uncachable writes, use that
-        for (int i = 0; i < writebacks.size(); i++) {
-            mshr = writebacks[i];
+        if (writebacks.size()) {
+            // We should only ever find a single match
+            assert(writebacks.size() == 1);
+            mshr = writebacks[0];
             assert(!mshr->isUncacheable());
             assert(mshr->getNumTargets() == 1);
             PacketPtr wb_pkt = mshr->getTarget()->pkt;
@@ -1321,16 +1323,14 @@
                 markInService(mshr);
                 delete wb_pkt;
             }
-
-            // If this was a shared writeback, there may still be
-            // other shared copies above that require invalidation.
-            // We could be more selective and return here if the
-            // request is non-exclusive or if the writeback is
-            // exclusive.
-            break;
-        }
+        } // writebacks.size()
     }
 
+    // If this was a shared writeback, there may still be
+    // other shared copies above that require invalidation.
+    // We could be more selective and return here if the
+    // request is non-exclusive or if the writeback is
+    // exclusive.
     handleSnoop(pkt, blk, true, false, false);
 }
 
diff -r 44a7c9a33484 -r 5119c5ee2bea src/mem/cache/mshr.cc
--- a/src/mem/cache/mshr.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/mem/cache/mshr.cc	Wed May 02 16:08:14 2012 -0400
@@ -161,10 +161,18 @@
     for (ConstIterator i = begin(); i != end_i; ++i) {
         const char *s;
         switch (i->source) {
-          case Target::FromCPU: s = "FromCPU";
-          case Target::FromSnoop: s = "FromSnoop";
-          case Target::FromPrefetcher: s = "FromPrefetcher";
-          default: s = "";
+          case Target::FromCPU:
+            s = "FromCPU";
+            break;
+          case Target::FromSnoop:
+            s = "FromSnoop";
+            break;
+          case Target::FromPrefetcher:
+            s = "FromPrefetcher";
+            break;
+          default:
+            s = "";
+            break;
         }
         ccprintf(os, "%s%s: ", prefix, s);
         i->pkt->print(os, verbosity, "");
diff -r 44a7c9a33484 -r 5119c5ee2bea src/mem/cache/prefetch/base.cc
--- a/src/mem/cache/prefetch/base.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/mem/cache/prefetch/base.cc	Wed May 02 16:08:14 2012 -0400
@@ -182,7 +182,7 @@
             pfRemovedMSHR++;
             delete (*iter)->req;
             delete (*iter);
-            pf.erase(iter);
+            iter = pf.erase(iter);
             if (pf.empty())
                 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
         }
@@ -194,15 +194,17 @@
         // Needed for serial calculators like GHB
         if (serialSquash) {
             iter = pf.end();
-            iter--;
+            if (iter != pf.begin())
+                iter--;
             while (!pf.empty() && ((*iter)->time >= time)) {
                 pfSquashed++;
                 DPRINTF(HWPrefetch, "Squashing old prefetch addr: 0x%x\n",
                         (*iter)->getAddr());
                 delete (*iter)->req;
                 delete (*iter);
-                pf.erase(iter);
-                iter--;
+                iter = pf.erase(iter);
+                if (iter != pf.begin())
+                    iter--;
             }
             if (pf.empty())
                 cache->deassertMemSideBusRequest(BaseCache::Request_PF);
diff -r 44a7c9a33484 -r 5119c5ee2bea src/mem/fs_translating_port_proxy.cc
--- a/src/mem/fs_translating_port_proxy.cc	Wed May 02 16:07:35 2012 -0400
+++ b/src/mem/fs_translating_port_proxy.cc	Wed May 02 16:08:14 2012 -0400
@@ -140,7 +140,7 @@
     bool foundNull = false;
     while ((dst - start + 1) < maxlen && !foundNull) {
         vp.readBlob(vaddr++, (uint8_t*)dst, 1);
-        if (dst == '\0')
+        if (*dst == '\0')
             foundNull = true;
         dst++;
     }
diff -r 44a7c9a33484 -r 5119c5ee2bea src/sim/eventq.hh
--- a/src/sim/eventq.hh	Wed May 02 16:07:35 2012 -0400
+++ b/src/sim/eventq.hh	Wed May 02 16:08:14 2012 -0400
@@ -516,11 +516,11 @@
     event->flags.clear(Event::Squashed);
     event->flags.clear(Event::Scheduled);
 
+    if (DTRACE(Event))
+        event->trace("descheduled");
+
     if (event->flags.isSet(Event::AutoDelete))
         delete event;
-
-    if (DTRACE(Event))
-        event->trace("descheduled");
 }
 
 inline void