diff -r 0bc82be9c82f -r 7a8f4a18013d tests/configs/memtest-ruby.py --- a/tests/configs/memtest-ruby.py Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/configs/memtest-ruby.py Wed Aug 11 14:38:35 2010 -0700 @@ -42,28 +42,33 @@ m5_root = os.path.dirname(config_root) addToPath(config_root+'/configs/common') addToPath(config_root+'/configs/ruby') -addToPath(config_root+'/configs/ruby/protocols') -addToPath(config_root+'/configs/ruby/topologies') import Ruby parser = optparse.OptionParser() # -# Set the default cache size and associativity to be very small to encourage -# races between requests and writebacks. +# Add the ruby specific and protocol specific options # -parser.add_option("--l1d_size", type="string", default="256B") -parser.add_option("--l1i_size", type="string", default="256B") -parser.add_option("--l2_size", type="string", default="512B") -parser.add_option("--l1d_assoc", type="int", default=2) -parser.add_option("--l1i_assoc", type="int", default=2) -parser.add_option("--l2_assoc", type="int", default=2) +Ruby.define_options(parser) execfile(os.path.join(config_root, "configs/common", "Options.py")) (options, args) = parser.parse_args() +# +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +# +options.l1d_size="256B" +options.l1i_size="256B" +options.l2_size="512B" +options.l3_size="1kB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 + #MAX CORES IS 8 with the fals sharing method nb_cores = 8 @@ -80,7 +85,7 @@ funcmem = PhysicalMemory(), physmem = PhysicalMemory()) -system.ruby = Ruby.create_system(options, system.physmem) +system.ruby = Ruby.create_system(options, system) assert(len(cpus) == len(system.ruby.cpu_ruby_ports)) diff -r 0bc82be9c82f -r 7a8f4a18013d tests/configs/rubytest-ruby.py --- a/tests/configs/rubytest-ruby.py Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/configs/rubytest-ruby.py Wed Aug 11 14:38:35 2010 -0700 @@ -43,36 +43,41 @@ m5_root = os.path.dirname(config_root) addToPath(config_root+'/configs/common') addToPath(config_root+'/configs/ruby') -addToPath(config_root+'/configs/ruby/protocols') -addToPath(config_root+'/configs/ruby/topologies') import Ruby parser = optparse.OptionParser() # -# Set the default cache size and associativity to be very small to encourage -# races between requests and writebacks. +# Add the ruby specific and protocol specific options # -parser.add_option("--l1d_size", type="string", default="256B") -parser.add_option("--l1i_size", type="string", default="256B") -parser.add_option("--l2_size", type="string", default="512B") -parser.add_option("--l1d_assoc", type="int", default=2) -parser.add_option("--l1i_assoc", type="int", default=2) -parser.add_option("--l2_assoc", type="int", default=2) +Ruby.define_options(parser) execfile(os.path.join(config_root, "configs/common", "Options.py")) (options, args) = parser.parse_args() # +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +# +options.l1d_size="256B" +options.l1i_size="256B" +options.l2_size="512B" +options.l3_size="1kB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 + +# # create the tester and system, including ruby # tester = RubyTester(checks_to_complete = 100, wakeup_frequency = 10) system = System(physmem = PhysicalMemory()) -system.ruby = Ruby.create_system(options, system.physmem) +system.ruby = Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) diff -r 0bc82be9c82f -r 7a8f4a18013d tests/configs/simple-timing-mp-ruby.py --- a/tests/configs/simple-timing-mp-ruby.py Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/configs/simple-timing-mp-ruby.py Wed Aug 11 14:38:35 2010 -0700 @@ -41,28 +41,33 @@ m5_root = os.path.dirname(config_root) addToPath(config_root+'/configs/common') addToPath(config_root+'/configs/ruby') -addToPath(config_root+'/configs/ruby/protocols') -addToPath(config_root+'/configs/ruby/topologies') import Ruby parser = optparse.OptionParser() # -# Set the default cache size and associativity to be very small to encourage -# races between requests and writebacks. +# Add the ruby specific and protocol specific options # -parser.add_option("--l1d_size", type="string", default="256B") -parser.add_option("--l1i_size", type="string", default="256B") -parser.add_option("--l2_size", type="string", default="512B") -parser.add_option("--l1d_assoc", type="int", default=2) -parser.add_option("--l1i_assoc", type="int", default=2) -parser.add_option("--l2_assoc", type="int", default=2) +Ruby.define_options(parser) execfile(os.path.join(config_root, "configs/common", "Options.py")) (options, args) = parser.parse_args() +# +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +# +options.l1d_size="256B" +options.l1i_size="256B" +options.l2_size="512B" +options.l3_size="1kB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 + nb_cores = 4 cpus = [ TimingSimpleCPU(cpu_id=i) for i in xrange(nb_cores) ] @@ -70,10 +75,9 @@ options.num_cpus = nb_cores # system simulated -system = System(cpu = cpus, - physmem = PhysicalMemory()) +system = System(cpu = cpus, physmem = PhysicalMemory()) -system.ruby = Ruby.create_system(options, system.physmem) +system.ruby = Ruby.create_system(options, system) assert(options.num_cpus == len(system.ruby.cpu_ruby_ports)) diff -r 0bc82be9c82f -r 7a8f4a18013d tests/configs/simple-timing-ruby.py --- a/tests/configs/simple-timing-ruby.py Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/configs/simple-timing-ruby.py Wed Aug 11 14:38:35 2010 -0700 @@ -41,36 +41,40 @@ m5_root = os.path.dirname(config_root) addToPath(config_root+'/configs/common') addToPath(config_root+'/configs/ruby') -addToPath(config_root+'/configs/ruby/protocols') -addToPath(config_root+'/configs/ruby/topologies') import Ruby parser = optparse.OptionParser() # -# Set the default cache size and associativity to be very small to encourage -# races between requests and writebacks. +# Add the ruby specific and protocol specific options # -parser.add_option("--l1d_size", type="string", default="256B") -parser.add_option("--l1i_size", type="string", default="256B") -parser.add_option("--l2_size", type="string", default="512B") -parser.add_option("--l1d_assoc", type="int", default=2) -parser.add_option("--l1i_assoc", type="int", default=2) -parser.add_option("--l2_assoc", type="int", default=2) +Ruby.define_options(parser) execfile(os.path.join(config_root, "configs/common", "Options.py")) (options, args) = parser.parse_args() +# +# Set the default cache size and associativity to be very small to encourage +# races between requests and writebacks. +# +options.l1d_size="256B" +options.l1i_size="256B" +options.l2_size="512B" +options.l3_size="1kB" +options.l1d_assoc=2 +options.l1i_assoc=2 +options.l2_assoc=2 +options.l3_assoc=2 + # this is a uniprocessor only test options.num_cpus = 1 cpu = TimingSimpleCPU(cpu_id=0) -system = System(cpu = cpu, - physmem = PhysicalMemory()) +system = System(cpu = cpu, physmem = PhysicalMemory()) -system.ruby = Ruby.create_system(options, system.physmem) +system.ruby = Ruby.create_system(options, system) assert(len(system.ruby.cpu_ruby_ports) == 1) diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,166 +65,28 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.dir_cntrl0] type=Directory_Controller children=directory memBuffer buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory=system.dir_cntrl0.directory directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 to_mem_ctrl_latency=1 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -245,6 +107,149 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 13:57:44 +Real time: Aug/05/2010 10:23:43 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 0.95 -Virtual_time_in_minutes: 0.0158333 -Virtual_time_in_hours: 0.000263889 -Virtual_time_in_days: 1.09954e-05 +Virtual_time_in_seconds: 0.32 +Virtual_time_in_minutes: 0.00533333 +Virtual_time_in_hours: 8.88889e-05 +Virtual_time_in_days: 3.7037e-06 Ruby_current_time: 275313 Ruby_start_time: 0 Ruby_cycles: 275313 -mbytes_resident: 34.4609 -mbytes_total: 34.4688 +mbytes_resident: 34.8867 +mbytes_total: 34.8945 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 275314 [ 275314 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 275314 ] Busy Controller Counts: L1Cache-0:0 @@ -82,9 +71,23 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 281 count: 8464 average: 31.5275 | standard deviation: 62.4195 | 0 6974 0 0 0 0 0 0 0 30 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 156 439 246 330 220 8 7 9 11 3 2 9 4 5 1 0 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 269 count: 6414 average: 20.6784 | standard deviation: 51.1007 | 0 5723 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 59 203 95 191 106 4 5 4 6 2 1 1 1 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 281 count: 1185 average: 82.5848 | standard deviation: 82.5677 | 0 602 0 0 0 0 0 0 0 13 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 64 191 73 123 92 4 2 3 3 1 1 7 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 215 count: 865 average: 42.0289 | standard deviation: 69.8546 | 0 649 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 33 45 78 16 22 0 0 2 2 0 0 1 1 1 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7392 -page_faults: 2212 +page_reclaims: 7576 +page_faults: 2166 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ Network Stats ------------- +total_msg_count_Control: 8850 70800 +total_msg_count_Request_Control: 3123 24984 +total_msg_count_Response_Data: 9681 697032 +total_msg_count_Response_Control: 14286 114288 +total_msg_count_Writeback_Data: 864 62208 +total_msg_count_Writeback_Control: 867 6936 +total_msgs: 37671 total_bytes: 976248 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.0889147 @@ -186,352 +197,346 @@ outgoing_messages_switch_3_link_2_Response_Data: 277 19944 [ 0 277 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 1175 9400 [ 0 1175 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -Inv 1041 -L1_Replacement 1354 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 583 -DataS_fromL1 0 -Data_all_Acks 907 -Ack 0 -Ack_all 0 -WB_Ack 436 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Inv [1041 ] 1041 +L1_Replacement [1354 ] 1354 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [583 ] 583 +DataS_fromL1 [0 ] 0 +Data_all_Acks [907 ] 907 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [436 ] 436 - Transitions - -NP Load 525 -NP Ifetch 646 -NP Store 191 -NP Inv 356 -NP L1_Replacement 0 <-- +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Inv [356 ] 356 +NP L1_Replacement [0 ] 0 -I Load 58 -I Ifetch 45 -I Store 25 -I Inv 0 <-- -I L1_Replacement 556 +I Load [58 ] 58 +I Ifetch [45 ] 45 +I Store [25 ] 25 +I Inv [0 ] 0 +I L1_Replacement [556 ] 556 -S Load 0 <-- -S Ifetch 5723 -S Store 0 <-- -S Inv 325 -S L1_Replacement 362 +S Load [0 ] 0 +S Ifetch [5723 ] 5723 +S Store [0 ] 0 +S Inv [325 ] 325 +S L1_Replacement [362 ] 362 -E Load 454 -E Ifetch 0 <-- -E Store 71 -E Inv 219 -E L1_Replacement 291 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- +E Load [454 ] 454 +E Ifetch [0 ] 0 +E Store [71 ] 71 +E Inv [219 ] 219 +E L1_Replacement [291 ] 291 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 -M Load 148 -M Ifetch 0 <-- -M Store 578 -M Inv 141 -M L1_Replacement 145 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- +M Load [148 ] 148 +M Ifetch [0 ] 0 +M Store [578 ] 578 +M Inv [141 ] 141 +M L1_Replacement [145 ] 145 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 0 <-- -IS Data_Exclusive 583 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 691 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [583 ] 583 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [691 ] 691 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 0 <-- -IM Data_all_Acks 216 -IM Ack 0 <-- +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [216 ] 216 +IM Ack [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 436 +M_I Load [0 ] 0 +M_I Ifetch [0 ] 0 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [436 ] 436 -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GET_INSTR 691 -L1_GETS 592 -L1_GETX 220 -L1_UPGRADE 0 -L1_PUTX 436 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 142 -L2_Replacement_clean 1310 -Mem_Data 1460 -Mem_Ack 1452 -WB_Data 141 -WB_Data_clean 0 -Ack 0 -Ack_all 900 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 799 -MEM_Inv 0 +L1_GET_INSTR [691 ] 691 +L1_GETS [592 ] 592 +L1_GETX [220 ] 220 +L1_UPGRADE [0 ] 0 +L1_PUTX [436 ] 436 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [142 ] 142 +L2_Replacement_clean [1310 ] 1310 +Mem_Data [1460 ] 1460 +Mem_Ack [1452 ] 1452 +WB_Data [141 ] 141 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [900 ] 900 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [799 ] 799 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 686 -NP L1_GETS 570 -NP L1_GETX 204 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- +NP L1_GET_INSTR [686 ] 686 +NP L1_GETS [570 ] 570 +NP L1_GETX [204 ] 204 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 -SS L1_GET_INSTR 5 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 681 -SS MEM_Inv 0 <-- +SS L1_GET_INSTR [5 ] 5 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [681 ] 681 +SS MEM_Inv [0 ] 0 -M L1_GET_INSTR 0 <-- -M L1_GETS 13 -M L1_GETX 12 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 134 -M L2_Replacement_clean 277 -M MEM_Inv 0 <-- +M L1_GET_INSTR [0 ] 0 +M L1_GETS [13 ] 13 +M L1_GETX [12 ] 12 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [134 ] 134 +M L2_Replacement_clean [277 ] 277 +M MEM_Inv [0 ] 0 -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 436 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 8 -MT L2_Replacement_clean 352 -MT MEM_Inv 0 <-- +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [436 ] 436 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [8 ] 8 +MT L2_Replacement_clean [352 ] 352 +MT MEM_Inv [0 ] 0 -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 9 -M_I L1_GETX 4 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 1452 -M_I MEM_Inv 0 <-- +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [9 ] 9 +M_I L1_GETX [4 ] 4 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [1452 ] 1452 +M_I MEM_Inv [0 ] 0 -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 6 -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 2 -MT_I MEM_Inv 0 <-- +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [6 ] 6 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [2 ] 2 +MT_I MEM_Inv [0 ] 0 -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 135 -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 217 +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [135 ] 135 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [217 ] 217 -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 681 +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [681 ] 681 -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 570 -ISS MEM_Inv 0 <-- +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [570 ] 570 +ISS MEM_Inv [0 ] 0 -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 686 -IS MEM_Inv 0 <-- +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [686 ] 686 +IS MEM_Inv [0 ] 0 -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 204 -IM MEM_Inv 0 <-- +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [204 ] 204 +IM MEM_Inv [0 ] 0 -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [0 ] 0 +SS_MB MEM_Inv [0 ] 0 -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 799 -MT_MB MEM_Inv 0 <-- +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [799 ] 799 +MT_MB MEM_Inv [0 ] 0 -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1737 memory_reads: 1460 memory_writes: 277 @@ -551,67 +556,66 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 92 21 45 54 57 174 48 18 19 22 35 37 56 59 44 36 41 24 22 28 32 48 122 36 32 25 35 96 114 185 19 61 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 1460 -Data 277 -Memory_Data 1460 -Memory_Ack 277 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 1175 +Fetch [1460 ] 1460 +Data [277 ] 277 +Memory_Data [1460 ] 1460 +Memory_Ack [277 ] 277 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [1175 ] 1175 - Transitions - -I Fetch 1460 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I Fetch [1460 ] 1460 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 -M Data 277 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 1175 +M Data [277 ] 277 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [1175 ] 1175 -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 1460 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [1460 ] 1460 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 277 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [277 ] 277 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Jan 28 2010 13:54:58 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 13:57:42 -M5 executing on svvint03 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:23:42 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 8106 # Simulator instruction rate (inst/s) -host_mem_usage 215916 # Number of bytes of host memory used -host_seconds 0.79 # Real time elapsed on the host -host_tick_rate 348501 # Simulator tick rate (ticks/s) +host_inst_rate 24630 # Simulator instruction rate (inst/s) +host_mem_usage 212388 # Number of bytes of host memory used +host_seconds 0.26 # Real time elapsed on the host +host_tick_rate 1058851 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000275 # Number of seconds simulated diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,162 +65,27 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.dir_cntrl0] type=Directory_Controller children=directory memBuffer buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory=system.dir_cntrl0.directory directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -241,6 +106,146 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,40 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:08:14 +Real time: Aug/05/2010 10:35:39 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.8 -Virtual_time_in_minutes: 0.0133333 -Virtual_time_in_hours: 0.000222222 -Virtual_time_in_days: 9.25926e-06 +Virtual_time_in_seconds: 0.44 +Virtual_time_in_minutes: 0.00733333 +Virtual_time_in_hours: 0.000122222 +Virtual_time_in_days: 5.09259e-06 Ruby_current_time: 223854 Ruby_start_time: 0 Ruby_cycles: 223854 -mbytes_resident: 34.6055 -mbytes_total: 34.6133 +mbytes_resident: 34.9609 +mbytes_total: 34.9688 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 223855 [ 223855 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 223855 ] Busy Controller Counts: L2Cache-0:0 @@ -82,9 +71,23 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 276 count: 8464 average: 25.4478 | standard deviation: 56.39 | 0 7102 0 0 0 0 0 0 0 188 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 251 197 238 187 165 13 4 20 3 7 5 4 3 3 1 0 1 1 1 0 0 1 0 1 0 0 0 3 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 276 count: 6414 average: 17.9724 | standard deviation: 47.359 | 0 5768 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 153 110 113 93 66 5 3 16 1 3 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 259 count: 1185 average: 62.838 | standard deviation: 78.9565 | 0 660 0 0 0 0 0 0 0 112 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 98 55 84 84 63 2 1 3 2 3 5 3 2 2 0 0 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 227 count: 865 average: 29.6555 | standard deviation: 60.051 | 0 674 0 0 0 0 0 0 0 0 60 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 41 10 36 6 0 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7397 -page_faults: 2249 +page_reclaims: 7630 +page_faults: 2184 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ Network Stats ------------- +total_msg_count_Request_Control: 7428 59424 +total_msg_count_Response_Data: 6684 481248 +total_msg_count_ResponseL2hit_Data: 744 53568 +total_msg_count_Writeback_Data: 4644 334368 +total_msg_count_Writeback_Control: 17424 139392 +total_msg_count_Unblock_Control: 7428 59424 +total_msgs: 44352 total_bytes: 1127424 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.219641 @@ -190,972 +201,966 @@ outgoing_messages_switch_3_link_2_Writeback_Control: 2002 16016 [ 0 1098 904 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 1114 8912 [ 0 0 1114 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -L1_Replacement 1379 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 1362 -Writeback_Ack 0 -Writeback_Ack_Data 1354 -Writeback_Nack 0 -All_acks 191 -Use_Timeout 1361 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +L1_Replacement [1379 ] 1379 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [1362 ] 1362 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [1354 ] 1354 +Writeback_Nack [0 ] 0 +All_acks [191 ] 191 +Use_Timeout [1361 ] 1361 - Transitions - -I Load 525 -I Ifetch 646 -I Store 191 -I L1_Replacement 0 <-- -I Inv 0 <-- +I Load [525 ] 525 +I Ifetch [646 ] 646 +I Store [191 ] 191 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 -M Load 308 -M Ifetch 3484 -M Store 51 -M L1_Replacement 1086 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- +M Load [308 ] 308 +M Ifetch [3484 ] 3484 +M Store [51 ] 51 +M L1_Replacement [1086 ] 1086 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 -M_W Load 111 -M_W Ifetch 2284 -M_W Store 27 -M_W L1_Replacement 17 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 1143 +M_W Load [111 ] 111 +M_W Ifetch [2284 ] 2284 +M_W Store [27 ] 27 +M_W L1_Replacement [17 ] 17 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [1143 ] 1143 -MM Load 234 -MM Ifetch 0 <-- -MM Store 339 -MM L1_Replacement 268 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- +MM Load [234 ] 234 +MM Ifetch [0 ] 0 +MM Store [339 ] 339 +MM L1_Replacement [268 ] 268 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 -MM_W Load 7 -MM_W Ifetch 0 <-- -MM_W Store 257 -MM_W L1_Replacement 8 -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 218 +MM_W Load [7 ] 7 +MM_W Ifetch [0 ] 0 +MM_W Store [257 ] 257 +MM_W L1_Replacement [8 ] 8 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [218 ] 218 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 191 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [191 ] 191 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 191 +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [191 ] 191 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 1171 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [1171 ] 1171 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 1354 -MI Writeback_Nack 0 <-- +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [1354 ] 1354 +MI Writeback_Nack [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GETS 1171 -L1_GETX 191 -L1_PUTO 0 -L1_PUTX 1354 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 131 -Data 131 -Data_Exclusive 983 -L1_WBCLEANDATA 1059 -L1_WBDIRTYDATA 295 -Writeback_Ack 1098 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 1362 -L2_Replacement 1098 +L1_GETS [1171 ] 1171 +L1_GETX [191 ] 191 +L1_PUTO [0 ] 0 +L1_PUTX [1354 ] 1354 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [131 ] 131 +Data [131 ] 131 +Data_Exclusive [983 ] 983 +L1_WBCLEANDATA [1059 ] 1059 +L1_WBDIRTYDATA [295 ] 295 +Writeback_Ack [1098 ] 1098 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [1362 ] 1362 +L2_Replacement [1098 ] 1098 - Transitions - -NP L1_GETS 983 -NP L1_GETX 131 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- +NP L1_GETS [983 ] 983 +NP L1_GETX [131 ] 131 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 1354 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [1354 ] 1354 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 -M L1_GETS 188 -M L1_GETX 60 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 1098 +M L1_GETS [188 ] 188 +M L1_GETX [60 ] 60 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [1098 ] 1098 -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 1059 -ILXW L1_WBDIRTYDATA 295 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [1059 ] 1059 +ILXW L1_WBDIRTYDATA [295 ] 295 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 983 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 983 -IGS L2_Replacement 0 <-- +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [983 ] 983 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [983 ] 983 +IGS L2_Replacement [0 ] 0 -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 131 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [131 ] 131 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 131 -IGMO Exclusive_Unblock 131 -IGMO L2_Replacement 0 <-- +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [131 ] 131 +IGMO Exclusive_Unblock [131 ] 131 +IGMO L2_Replacement [0 ] 0 -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 60 -MM L2_Replacement 0 <-- +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [60 ] 60 +MM L2_Replacement [0 ] 0 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 188 -OO L2_Replacement 0 <-- +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [188 ] 188 +OO L2_Replacement [0 ] 0 -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 -MI L1_GETS 0 <-- -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 1098 -MI L2_Replacement 0 <-- +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [1098 ] 1098 +MI L2_Replacement [0 ] 0 -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1308 memory_reads: 1114 memory_writes: 194 @@ -1175,201 +1180,200 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 99 29 16 19 22 32 34 52 48 38 30 39 21 21 27 28 37 55 22 31 22 32 70 84 104 13 52 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 131 -GETS 983 -PUTX 1098 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 1114 -Clean_Writeback 904 -Dirty_Writeback 194 -Memory_Data 1114 -Memory_Ack 194 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [131 ] 131 +GETS [983 ] 983 +PUTX [1098 ] 1098 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [1114 ] 1114 +Clean_Writeback [904 ] 904 +Dirty_Writeback [194 ] 194 +Memory_Data [1114 ] 1114 +Memory_Ack [194 ] 194 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 131 -I GETS 983 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 191 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [131 ] 131 +I GETS [983 ] 983 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [191 ] 191 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -M GETX 0 <-- -M GETS 0 <-- -M PUTX 1098 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [1098 ] 1098 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 983 -IS Memory_Data 983 -IS Memory_Ack 2 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [983 ] 983 +IS Memory_Data [983 ] 983 +IS Memory_Ack [2 ] 2 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 131 -MM Memory_Data 131 -MM Memory_Ack 1 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [131 ] 131 +MM Memory_Data [131 ] 131 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 904 -MI Dirty_Writeback 194 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [904 ] 904 +MI Dirty_Writeback [194 ] 194 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Jan 28 2010 14:49:51 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:08:13 -M5 executing on svvint05 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:35:39 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 11859 # Simulator instruction rate (inst/s) -host_mem_usage 216064 # Number of bytes of host memory used -host_seconds 0.55 # Real time elapsed on the host -host_tick_rate 407003 # Simulator tick rate (ticks/s) +host_inst_rate 23717 # Simulator instruction rate (inst/s) +host_mem_usage 212528 # Number of bytes of host memory used +host_seconds 0.27 # Real time elapsed on the host +host_tick_rate 829037 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated sim_seconds 0.000224 # Number of seconds simulated diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/linux/hello +executable=tests/test-progs/hello/bin/alpha/linux/hello gid=100 input=cin max_stack_size=67108864 @@ -65,172 +65,30 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -251,6 +109,154 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,12 +13,12 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered -virtual_net_2: active, ordered -virtual_net_3: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered virtual_net_4: active, unordered virtual_net_5: active, ordered virtual_net_6: inactive @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:55:45 +Real time: Aug/05/2010 10:42:35 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.43 -Virtual_time_in_minutes: 0.00716667 -Virtual_time_in_hours: 0.000119444 -Virtual_time_in_days: 4.97685e-06 +Virtual_time_in_seconds: 0.27 +Virtual_time_in_minutes: 0.0045 +Virtual_time_in_hours: 7.5e-05 +Virtual_time_in_days: 3.125e-06 -Ruby_current_time: 236654 +Ruby_current_time: 243131 Ruby_start_time: 0 -Ruby_cycles: 236654 +Ruby_cycles: 243131 -mbytes_resident: 34.4141 -mbytes_total: 34.4219 +mbytes_resident: 34.8711 +mbytes_total: 34.8789 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 236655 [ 236655 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 243132 ] Busy Controller Counts: L1Cache-0:0 @@ -81,10 +70,32 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 279 count: 8464 average: 26.9601 | standard deviation: 58.5578 | 0 7082 0 0 0 0 0 0 0 0 0 0 0 220 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 268 180 200 165 117 12 3 8 3 4 46 30 32 33 37 0 1 1 1 2 1 4 1 3 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 4 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 279 count: 6414 average: 18.8457 | standard deviation: 49.2277 | 0 5768 0 0 0 0 0 0 0 0 0 0 0 55 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 125 84 121 94 59 8 2 4 1 3 20 12 18 22 8 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 279 count: 1185 average: 66.1527 | standard deviation: 80.7635 | 0 660 0 0 0 0 0 0 0 0 0 0 0 99 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 56 67 56 46 4 0 3 2 0 24 12 14 10 10 0 0 0 1 1 1 2 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 213 count: 865 average: 33.437 | standard deviation: 63.4371 | 0 654 0 0 0 0 0 0 0 0 0 0 0 66 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 40 12 15 12 0 1 1 0 1 2 6 0 1 19 0 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 286 count: 8464 average: 27.7253 | standard deviation: 60.155 | 0 7084 0 0 0 0 0 0 0 0 79 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 215 count: 6414 average: 18.3631 | standard deviation: 49.3028 | 0 5768 0 0 0 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 286 count: 1185 average: 71.4084 | standard deviation: 82.7283 | 0 660 0 0 0 0 0 0 0 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 276 count: 865 average: 37.3029 | standard deviation: 68.2954 | 0 656 0 0 0 0 0 0 0 0 31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7084 average: 2 | standard deviation: 0 | 0 0 7084 ] +miss_latency_L2Cache: [binsize: 1 max: 21 count: 79 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 ] +miss_latency_Directory: [binsize: 2 max: 286 count: 1301 average: 168.209 | standard deviation: 14.0495 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 203 180 133 156 350 5 6 5 2 10 39 29 65 31 60 0 0 0 1 0 1 1 3 0 2 1 0 0 3 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 2 0 4 4 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 1300 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 10 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 215 count: 636 average: 166.722 | standard deviation: 8.46373 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 112 61 67 108 171 2 3 3 1 2 18 10 29 22 23 0 0 0 0 0 1 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 38 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 ] +miss_latency_LD_Directory: [binsize: 2 max: 286 count: 487 average: 169.407 | standard deviation: 17.5782 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 67 68 54 42 153 3 1 0 1 7 19 12 7 6 29 0 0 0 1 0 0 1 0 0 2 1 0 0 2 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 4 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 656 average: 2 | standard deviation: 0 | 0 0 656 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 31 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 ] +miss_latency_ST_Directory: [binsize: 2 max: 276 count: 178 average: 170.247 | standard deviation: 18.1183 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24 51 12 6 26 0 2 2 0 1 2 7 29 3 8 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +127,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7348 -page_faults: 2239 +page_reclaims: 7568 +page_faults: 2181 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,788 +136,900 @@ Network Stats ------------- +total_msg_count_Request_Control: 8046 64368 +total_msg_count_Response_Data: 3903 281016 +total_msg_count_ResponseL2hit_Data: 237 17064 +total_msg_count_Response_Control: 3 24 +total_msg_count_Writeback_Data: 4785 344520 +total_msg_count_Writeback_Control: 3222 25776 +total_msgs: 20196 total_bytes: 732768 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.164956 - links_utilized_percent_switch_0_link_0: 0.0658979 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.264014 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.171423 + links_utilized_percent_switch_0_link_0: 0.0638596 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.278985 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0968503 - links_utilized_percent_switch_1_link_0: 0.0660035 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.127697 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0889284 + links_utilized_percent_switch_1_link_0: 0.0697464 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.10811 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.12111 - links_utilized_percent_switch_2_link_0: 0.0212652 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.220955 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.132082 + links_utilized_percent_switch_2_link_0: 0.023367 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.240796 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.204222 - links_utilized_percent_switch_3_link_0: 0.263592 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.264014 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.0850609 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.209297 + links_utilized_percent_switch_3_link_0: 0.255438 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.278985 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0934681 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 1162 83664 [ 0 1162 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 220 15840 [ 0 220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 38 304 [ 0 38 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 1382 11056 [ 0 0 0 0 1382 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 1220 87840 [ 0 1220 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 134 1072 [ 0 134 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 1180 9440 [ 0 0 0 1180 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 207 14904 [ 0 207 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 983 7864 [ 0 983 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 1301 93672 [ 0 0 0 0 1301 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 79 5688 [ 0 0 0 0 79 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 1380 11040 [ 0 1380 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1354 97488 [ 0 0 0 0 1354 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 1302 10416 [ 0 0 1302 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 241 17352 [ 0 0 0 0 241 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 1074 8592 [ 0 0 0 0 1074 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 646 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 734 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 734 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - --- L1Cache 0 --- + system.l1_cntrl0.sequencer.dcache_request_type_LD: 71.5259% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 28.4741% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 734 100% + + --- L1Cache --- - Event Counts - -Load 1185 -Ifetch 6414 -Store 865 -L1_Replacement 1375 -Data_Shared 154 -Data_Owner 0 -Data_All_Tokens 1228 -Ack 38 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 -Request_Timeout 0 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 1227 +Load [1185 ] 1185 +Ifetch [6414 ] 6414 +Store [865 ] 865 +Atomic [0 ] 0 +L1_Replacement [1384 ] 1384 +Data_Shared [48 ] 48 +Data_Owner [0 ] 0 +Data_All_Tokens [1332 ] 1332 +Ack [1 ] 1 +Ack_All_Tokens [0 ] 0 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Request_Timeout [0 ] 0 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [1331 ] 1331 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 525 -NP Ifetch 646 -NP Store 191 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP Load [525 ] 525 +NP Ifetch [646 ] 646 +NP Store [191 ] 191 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S Load 166 -S Ifetch 314 -S Store 20 -S L1_Replacement 134 -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S Load [95 ] 95 +S Ifetch [64 ] 64 +S Store [18 ] 18 +S Atomic [0 ] 0 +S L1_Replacement [30 ] 30 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M Load 184 -M Ifetch 3447 -M Store 33 -M L1_Replacement 952 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- +M Load [222 ] 222 +M Ifetch [3433 ] 3433 +M Store [35 ] 35 +M Atomic [0 ] 0 +M L1_Replacement [1056 ] 1056 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -MM Load 221 -MM Ifetch 0 <-- -MM Store 333 -MM L1_Replacement 268 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 0 <-- +MM Load [220 ] 220 +MM Ifetch [0 ] 0 +MM Store [331 ] 331 +MM Atomic [0 ] 0 +MM L1_Replacement [268 ] 268 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [0 ] 0 -M_W Load 69 -M_W Ifetch 2007 -M_W Store 25 -M_W L1_Replacement 14 -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 991 +M_W Load [102 ] 102 +M_W Ifetch [2271 ] 2271 +M_W Store [25 ] 25 +M_W Atomic [0 ] 0 +M_W L1_Replacement [21 ] 21 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [0 ] 0 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [1097 ] 1097 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -MM_W Load 20 -MM_W Ifetch 0 <-- -MM_W Store 263 -MM_W L1_Replacement 7 -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 236 +MM_W Load [21 ] 21 +MM_W Ifetch [0 ] 0 +MM_W Store [265 ] 265 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [9 ] 9 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [0 ] 0 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [234 ] 234 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 191 -IM Ack 7 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 0 <-- -IM Request_Timeout 0 <-- +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data_Shared [0 ] 0 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [191 ] 191 +IM Ack [1 ] 1 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [0 ] 0 +IM Request_Timeout [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 20 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [18 ] 18 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [0 ] 0 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 154 -IS Data_Owner 0 <-- -IS Data_All_Tokens 1017 -IS Ack 31 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 0 <-- -IS Request_Timeout 0 <-- +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Shared [48 ] 48 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [1123 ] 1123 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [0 ] 0 +IS Request_Timeout [0 ] 0 -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 1302 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 1302 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 86.2519% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 13.7481% - --- L2Cache 0 --- + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1302 100% + + --- L2Cache --- - Event Counts - -L1_GETS 1140 -L1_GETS_Last_Token 31 -L1_GETX 211 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 1276 -Writeback_Tokens 82 -Writeback_Shared_Data 0 -Writeback_All_Tokens 1272 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 +L1_GETS [1168 ] 1168 +L1_GETS_Last_Token [3 ] 3 +L1_GETX [209 ] 209 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [1349 ] 1349 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [28 ] 28 +Writeback_All_Tokens [1326 ] 1326 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 - Transitions - -NP L1_GETS 986 -NP L1_GETX 138 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 82 -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 1202 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP L1_GETS [1123 ] 1123 +NP L1_GETX [177 ] 177 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [28 ] 28 +NP Writeback_All_Tokens [1323 ] 1323 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 -I L1_GETS 0 <-- -I L1_GETS_Last_Token 31 -I L1_GETX 7 -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 130 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 18 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [34 ] 34 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [1 ] 1 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [3 ] 3 +S L1_GETX [1 ] 1 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [24 ] 24 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 18 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 84 -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 52 -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [42 ] 42 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [2 ] 2 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS 154 -M L1_GETX 48 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 1062 -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- +M L1_GETS [45 ] 45 +M L1_GETX [30 ] 30 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [1249 ] 1249 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1369 - memory_reads: 1162 - memory_writes: 207 - memory_refreshes: 493 - memory_total_request_delays: 529 - memory_delays_per_request: 0.386413 - memory_delays_in_input_queue: 185 +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1542 + memory_reads: 1301 + memory_writes: 241 + memory_refreshes: 507 + memory_total_request_delays: 714 + memory_delays_per_request: 0.463035 + memory_delays_in_input_queue: 240 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 344 - memory_stalls_for_bank_busy: 101 + memory_delays_stalled_at_head_of_bank_queue: 474 + memory_stalls_for_bank_busy: 148 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 19 - memory_stalls_for_bus: 222 + memory_stalls_for_arbitration: 30 + memory_stalls_for_bus: 278 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 2 + memory_stalls_for_read_write_turnaround: 18 memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 75 17 45 46 54 108 37 16 19 22 32 34 52 49 39 31 39 21 21 21 28 38 61 27 30 22 32 72 90 124 14 53 + accesses_per_bank: 80 17 45 54 54 148 45 17 20 22 33 34 54 53 44 33 40 22 21 28 28 42 73 34 32 25 34 75 101 159 19 56 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 163 -GETS 1017 -Lockdown 0 -Unlockdown 0 -Own_Lock_or_Unlock 0 -Data_Owner 19 -Data_All_Tokens 188 -Ack_Owner 65 -Ack_Owner_All_Tokens 874 -Tokens 0 -Ack_All_Tokens 44 -Request_Timeout 0 -Memory_Data 1162 -Memory_Ack 207 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [179 ] 179 +GETS [1123 ] 1123 +Lockdown [0 ] 0 +Unlockdown [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [21 ] 21 +Data_All_Tokens [220 ] 220 +Ack_Owner [21 ] 21 +Ack_Owner_All_Tokens [1029 ] 1029 +Tokens [0 ] 0 +Ack_All_Tokens [24 ] 24 +Request_Timeout [0 ] 0 +Memory_Data [1301 ] 1301 +Memory_Ack [241 ] 241 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 145 -O GETS 1017 -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 44 -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- +O GETX [178 ] 178 +O GETS [1123 ] 1123 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [24 ] 24 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX 18 -NO GETS 0 <-- -NO Lockdown 0 <-- -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 19 -NO Data_All_Tokens 188 -NO Ack_Owner 65 -NO Ack_Owner_All_Tokens 874 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NO GETX [1 ] 1 +NO GETS [0 ] 0 +NO Lockdown [0 ] 0 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [21 ] 21 +NO Data_All_Tokens [220 ] 220 +NO Ack_Owner [21 ] 21 +NO Ack_Owner_All_Tokens [1029 ] 1029 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -L GETX 0 <-- -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 0 <-- -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [0 ] 0 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 207 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [241 ] 241 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 1162 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [1301 ] 1301 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,13 @@ All Rights Reserved -M5 compiled Jan 28 2010 15:54:34 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:55:45 -M5 executing on svvint04 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:42:35 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 236654 because target called exit() +Exiting @ tick 243131 because target called exit() diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 35577 # Simulator instruction rate (inst/s) -host_mem_usage 215884 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 1314701 # Simulator tick rate (ticks/s) +host_inst_rate 45740 # Simulator instruction rate (inst/s) +host_mem_usage 212336 # Number of bytes of host memory used +host_seconds 0.14 # Real time elapsed on the host +host_tick_rate 1736538 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000237 # Number of seconds simulated -sim_ticks 236654 # Number of ticks simulated +sim_seconds 0.000243 # Number of seconds simulated +sim_ticks 243131 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 236654 # number of cpu cycles simulated +system.cpu.numCycles 243131 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -65,142 +65,29 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -num_int_nodes=3 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links1.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -221,6 +108,136 @@ tFaw=0 version=0 +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar +num_int_nodes=3 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=1 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,14 +13,14 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar -virtual_net_0: active, unordered -virtual_net_1: active, unordered +virtual_net_0: active, ordered +virtual_net_1: active, ordered virtual_net_2: active, unordered virtual_net_3: active, unordered -virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 11:55:11 +Real time: Aug/05/2010 11:09:30 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.39 -Virtual_time_in_minutes: 0.0065 -Virtual_time_in_hours: 0.000108333 -Virtual_time_in_days: 4.51389e-06 +Virtual_time_in_seconds: 0.61 +Virtual_time_in_minutes: 0.0101667 +Virtual_time_in_hours: 0.000169444 +Virtual_time_in_days: 7.06019e-06 -Ruby_current_time: 215528 +Ruby_current_time: 207970 Ruby_start_time: 0 -Ruby_cycles: 215528 +Ruby_cycles: 207970 -mbytes_resident: 33.1406 -mbytes_total: 33.1484 -resident_ratio: 1 +mbytes_resident: 34.3633 +mbytes_total: 206.125 +resident_ratio: 0.166768 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 215529 [ 215529 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 207971 ] Busy Controller Counts: L1Cache-0:0 @@ -80,10 +69,32 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 377 count: 8464 average: 24.4641 | standard deviation: 54.9689 | 0 7305 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 199 174 167 309 200 14 3 4 1 4 0 15 1 5 2 1 0 0 0 1 3 4 4 7 1 1 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 1 0 1 0 2 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 15 4 1 1 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 261 count: 6414 average: 16.7424 | standard deviation: 43.645 | 0 5833 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111 113 72 159 92 10 2 2 1 2 0 0 0 1 0 0 0 0 0 1 3 1 4 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 333 count: 1185 average: 57.908 | standard deviation: 75.2483 | 0 765 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 52 60 116 72 4 1 0 0 1 0 12 1 2 2 1 0 0 0 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 377 count: 865 average: 35.904 | standard deviation: 74.7708 | 0 707 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 35 34 36 0 0 2 0 1 0 3 0 2 0 0 0 0 0 0 0 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 14 3 1 0 0 2 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 2 max: 340 count: 8464 average: 23.5711 | standard deviation: 54.4023 | 0 7102 0 0 0 0 203 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 206 count: 6414 average: 15.8318 | standard deviation: 43.5273 | 0 5768 0 0 0 0 65 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 320 count: 1185 average: 57.1789 | standard deviation: 73.4856 | 0 660 0 0 0 0 105 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 340 count: 865 average: 34.9179 | standard deviation: 73.5132 | 0 674 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 7102 average: 2 | standard deviation: 0 | 0 0 7102 ] +miss_latency_L2Cache: [binsize: 1 max: 12 count: 203 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 203 ] +miss_latency_Directory: [binsize: 2 max: 340 count: 1159 average: 157.779 | standard deviation: 26.9285 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 105 186 155 195 147 260 3 10 2 4 5 17 3 8 6 12 5 1 0 0 0 0 0 0 0 1 0 0 0 0 2 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 2 3 15 0 0 0 0 1 0 0 0 1 3 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +imcomplete_dir_Times: 1158 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 5768 average: 2 | standard deviation: 0 | 0 0 5768 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 65 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 65 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 206 count: 581 average: 153.578 | standard deviation: 6.13441 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 104 55 89 94 142 2 1 1 2 2 14 2 2 3 6 2 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 660 average: 2 | standard deviation: 0 | 0 0 660 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 105 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 105 ] +miss_latency_LD_Directory: [binsize: 2 max: 320 count: 420 average: 155.183 | standard deviation: 18.008 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 75 63 68 46 92 1 7 1 2 2 3 0 4 2 4 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 2 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 674 average: 2 | standard deviation: 0 | 0 0 674 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 33 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 33 ] +miss_latency_ST_Directory: [binsize: 2 max: 340 count: 158 average: 180.127 | standard deviation: 61.3036 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 7 37 38 7 26 0 2 0 0 1 0 1 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 3 14 0 0 0 0 1 0 0 0 1 3 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,8 +126,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7120 -page_faults: 2128 +page_reclaims: 9927 +page_faults: 0 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -124,453 +135,665 @@ Network Stats ------------- +total_msg_count_Request_Control: 3477 27816 +total_msg_count_Response_Data: 3477 250344 +total_msg_count_Writeback_Data: 660 47520 +total_msg_count_Writeback_Control: 9627 77016 +total_msg_count_Unblock_Control: 3477 27816 +total_msgs: 20718 total_bytes: 430512 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.107382 - links_utilized_percent_switch_0_link_0: 0.0671258 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.147637 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.111284 + links_utilized_percent_switch_0_link_0: 0.0695653 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.153003 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152706 - links_utilized_percent_switch_1_link_0: 0.0369094 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.268503 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.158256 + links_utilized_percent_switch_1_link_0: 0.0382507 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.278261 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.20807 - links_utilized_percent_switch_2_link_0: 0.268503 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.147637 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.215632 + links_utilized_percent_switch_2_link_0: 0.278261 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.153003 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 1159 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 1143 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 0 1159 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 220 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 923 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 1159 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 1159 83448 [ 0 0 0 0 1159 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 1143 9144 [ 0 0 0 1143 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 1159 9272 [ 0 0 1159 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 220 15840 [ 0 0 0 0 0 220 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 2066 16528 [ 0 0 1143 0 0 923 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 1159 9272 [ 0 0 0 0 0 1159 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 581 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 581 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 646 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 646 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100% + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 581 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 581 average: 4 | standard deviation: 0 | 0 0 0 0 581 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 646 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 578 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 578 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 716 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 716 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 72.6644% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 27.3356% + system.l1_cntrl0.sequencer.dcache_request_type_LD: 73.324% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 26.676% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 578 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 578 average: 7.5917 | standard deviation: 1.2123 | 0 0 0 0 59 0 0 0 519 ] + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 716 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 1159 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 1159 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.L2cacheMemory_request_type_LD: 36.2381% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 13.6324% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 50.1294% - --- L1Cache 0 --- + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 1159 100% + + --- L1Cache --- - Event Counts - -Load 1209 -Ifetch 6447 -Store 946 -L2_Replacement 1143 -L1_to_L2 1354 -L2_to_L1D 138 -L2_to_L1I 65 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 1159 -Writeback_Ack 1143 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 1159 +Load [1201 ] 1201 +Ifetch [6436 ] 6436 +Store [919 ] 919 +L2_Replacement [1143 ] 1143 +L1_to_L2 [1354 ] 1354 +Trigger_L2_to_L1D [138 ] 138 +Trigger_L2_to_L1I [65 ] 65 +Complete_L2_to_L1 [203 ] 203 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [1159 ] 1159 +Writeback_Ack [1143 ] 1143 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [1159 ] 1159 - Transitions - -I Load 420 -I Ifetch 581 -I Store 158 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- +I Load [420 ] 420 +I Ifetch [581 ] 581 +I Store [158 ] 158 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 -M Load 368 -M Ifetch 5833 -M Store 66 -M L2_Replacement 923 -M L1_to_L2 1061 -M L2_to_L1D 68 -M L2_to_L1I 65 -M Other_GETX 0 <-- -M Other_GETS 0 <-- +M Load [368 ] 368 +M Ifetch [5833 ] 5833 +M Store [66 ] 66 +M L2_Replacement [923 ] 923 +M L1_to_L2 [1061 ] 1061 +M Trigger_L2_to_L1D [68 ] 68 +M Trigger_L2_to_L1I [65 ] 65 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 -MM Load 397 -MM Ifetch 0 <-- -MM Store 641 -MM L2_Replacement 220 -MM L1_to_L2 293 -MM L2_to_L1D 70 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- +MM Load [397 ] 397 +MM Ifetch [0 ] 0 +MM Store [641 ] 641 +MM L2_Replacement [220 ] 220 +MM L1_to_L2 [293 ] 293 +MM Trigger_L2_to_L1D [70 ] 70 +MM Trigger_L2_to_L1I [0 ] 0 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 158 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [0 ] 0 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [158 ] 158 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 0 <-- -M_W All_acks_no_sharers 1001 +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [0 ] 0 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [1001 ] 1001 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 158 +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [0 ] 0 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [0 ] 0 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [158 ] 158 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 1001 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [0 ] 0 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [1001 ] 1001 -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 -MI Load 24 -MI Ifetch 33 -MI Store 81 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 1143 +MI Load [16 ] 16 +MI Ifetch [22 ] 22 +MI Store [54 ] 54 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [1143 ] 1143 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [0 ] 0 +MT Complete_L2_to_L1 [133 ] 133 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [0 ] 0 +MMT Store [0 ] 0 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [0 ] 0 +MMT Complete_L2_to_L1 [70 ] 70 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1379 memory_reads: 1159 memory_writes: 220 - memory_refreshes: 449 - memory_total_request_delays: 342 - memory_delays_per_request: 0.248006 - memory_delays_in_input_queue: 1 + memory_refreshes: 434 + memory_total_request_delays: 471 + memory_delays_per_request: 0.341552 + memory_delays_in_input_queue: 15 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 341 - memory_stalls_for_bank_busy: 167 + memory_delays_stalled_at_head_of_bank_queue: 456 + memory_stalls_for_bank_busy: 86 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 19 - memory_stalls_for_bus: 57 + memory_stalls_for_arbitration: 30 + memory_stalls_for_bus: 78 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 98 + memory_stalls_for_read_write_turnaround: 262 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 75 17 45 40 54 101 33 16 20 22 32 34 53 50 39 31 39 22 21 27 28 38 81 22 31 23 32 72 89 126 14 52 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 519 -GETS 1114 -PUT 1143 -Unblock 1159 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 923 -Writeback_Exclusive_Dirty 220 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 1159 -Memory_Ack 220 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [189 ] 189 +GETS [1027 ] 1027 +PUT [1143 ] 1143 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [1159 ] 1159 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [923 ] 923 +Writeback_Exclusive_Dirty [220 ] 220 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [1159 ] 1159 +Memory_Ack [220 ] 220 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 1143 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [1143 ] 1143 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -E GETX 158 -E GETS 1001 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 0 <-- -NO_B Unblock 1159 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- +E GETX [158 ] 158 +E GETS [1001 ] 1001 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 1159 +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [1159 ] 1159 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [1159 ] 1159 -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 -WB GETX 27 -WB GETS 20 -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 923 -WB Writeback_Exclusive_Dirty 220 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -WB_E_W GETX 334 -WB_E_W GETS 93 -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 220 +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [27 ] 27 +WB GETS [19 ] 19 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [923 ] 923 +WB Writeback_Exclusive_Dirty [220 ] 220 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [4 ] 4 +WB_E_W GETS [7 ] 7 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/simout Wed Aug 11 14:38:35 2010 -0700 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simout +Redirecting stderr to build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,13 +7,13 @@ All Rights Reserved -M5 compiled Jan 28 2010 11:30:01 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 11:55:11 -M5 executing on svvint06 +M5 compiled Aug 5 2010 11:09:13 +M5 revision c5f5b5533e96 7536 default qtip tip brad/regress_updates +M5 started Aug 5 2010 11:09:30 +M5 executing on SC2B0617 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/linux/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 215528 because target called exit() +Exiting @ tick 207970 because target called exit() diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt --- a/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/linux/simple-timing-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 45742 # Simulator instruction rate (inst/s) -host_mem_usage 213100 # Number of bytes of host memory used -host_seconds 0.14 # Real time elapsed on the host -host_tick_rate 1539442 # Simulator tick rate (ticks/s) +host_inst_rate 31390 # Simulator instruction rate (inst/s) +host_mem_usage 211076 # Number of bytes of host memory used +host_seconds 0.20 # Real time elapsed on the host +host_tick_rate 1018487 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 6404 # Number of instructions simulated -sim_seconds 0.000216 # Number of seconds simulated -sim_ticks 215528 # Number of ticks simulated +sim_seconds 0.000208 # Number of seconds simulated +sim_ticks 207970 # Number of ticks simulated system.cpu.dtb.data_accesses 2060 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 2050 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 215528 # number of cpu cycles simulated +system.cpu.numCycles 207970 # number of cpu cycles simulated system.cpu.num_insts 6404 # Number of instructions executed system.cpu.num_refs 2060 # Number of memory references system.cpu.workload.PROG:num_syscalls 17 # Number of system calls diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,166 +65,28 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.dir_cntrl0] type=Directory_Controller children=directory memBuffer buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory=system.dir_cntrl0.directory directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 to_mem_ctrl_latency=1 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -245,6 +107,149 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 13:57:45 +Real time: Aug/05/2010 10:31:34 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.45 -Virtual_time_in_minutes: 0.0075 -Virtual_time_in_hours: 0.000125 -Virtual_time_in_days: 5.20833e-06 +Virtual_time_in_seconds: 0.26 +Virtual_time_in_minutes: 0.00433333 +Virtual_time_in_hours: 7.22222e-05 +Virtual_time_in_days: 3.00926e-06 Ruby_current_time: 103637 Ruby_start_time: 0 Ruby_cycles: 103637 -mbytes_resident: 33.0938 -mbytes_total: 33.1016 +mbytes_resident: 33.5703 +mbytes_total: 33.5781 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 103638 [ 103638 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 103638 ] Busy Controller Counts: L1Cache-0:0 @@ -82,9 +71,23 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] -miss_latency_2: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] +miss_latency_LD: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 223 count: 3294 average: 30.4624 | standard deviation: 61.2716 | 0 2722 0 0 0 0 0 0 0 25 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68 156 96 122 80 3 4 5 3 3 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 1 max: 181 count: 2585 average: 21.5791 | standard deviation: 52.0174 | 0 0 0 2285 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 0 70 0 67 0 59 0 54 0 1 1 1 0 3 0 0 0 3 ] +miss_latency_LD_NULL: [binsize: 2 max: 217 count: 415 average: 79.6169 | standard deviation: 81.8661 | 0 211 0 0 0 0 0 0 0 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 30 58 25 52 15 1 2 2 2 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 223 count: 294 average: 39.1837 | standard deviation: 68.3072 | 0 226 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 28 4 11 11 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7156 -page_faults: 2112 +page_reclaims: 7325 +page_faults: 2071 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ Network Stats ------------- +total_msg_count_Control: 3357 26856 +total_msg_count_Request_Control: 1293 10344 +total_msg_count_Response_Data: 3666 263952 +total_msg_count_Response_Control: 5220 41760 +total_msg_count_Writeback_Data: 327 23544 +total_msg_count_Writeback_Control: 231 1848 +total_msgs: 14094 total_bytes: 368304 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.0891754 @@ -186,352 +197,346 @@ outgoing_messages_switch_3_link_2_Response_Data: 103 7416 [ 0 103 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Response_Control: 436 3488 [ 0 436 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -Inv 431 -L1_Replacement 502 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 204 -DataS_fromL1 0 -Data_all_Acks 368 -Ack 0 -Ack_all 0 -WB_Ack 124 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Inv [431 ] 431 +L1_Replacement [502 ] 502 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [204 ] 204 +DataS_fromL1 [0 ] 0 +Data_all_Acks [368 ] 368 +Ack [0 ] 0 +Ack_all [0 ] 0 +WB_Ack [124 ] 124 - Transitions - -NP Load 182 -NP Ifetch 270 -NP Store 58 -NP Inv 162 -NP L1_Replacement 0 <-- +NP Load [182 ] 182 +NP Ifetch [270 ] 270 +NP Store [58 ] 58 +NP Inv [162 ] 162 +NP L1_Replacement [0 ] 0 -I Load 22 -I Ifetch 30 -I Store 10 -I Inv 0 <-- -I L1_Replacement 206 +I Load [22 ] 22 +I Ifetch [30 ] 30 +I Store [10 ] 10 +I Inv [0 ] 0 +I L1_Replacement [206 ] 206 -S Load 0 <-- -S Ifetch 2285 -S Store 0 <-- -S Inv 124 -S L1_Replacement 172 +S Load [0 ] 0 +S Ifetch [2285 ] 2285 +S Store [0 ] 0 +S Inv [124 ] 124 +S L1_Replacement [172 ] 172 -E Load 140 -E Ifetch 0 <-- -E Store 41 -E Inv 83 -E L1_Replacement 79 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- +E Load [140 ] 140 +E Ifetch [0 ] 0 +E Store [41 ] 41 +E Inv [83 ] 83 +E L1_Replacement [79 ] 79 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 -M Load 71 -M Ifetch 0 <-- -M Store 185 -M Inv 62 -M L1_Replacement 45 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- +M Load [71 ] 71 +M Ifetch [0 ] 0 +M Store [185 ] 185 +M Inv [62 ] 62 +M L1_Replacement [45 ] 45 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 0 <-- -IS Data_Exclusive 204 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 300 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Exclusive [204 ] 204 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [300 ] 300 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 0 <-- -IM Data_all_Acks 68 -IM Ack 0 <-- +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data [0 ] 0 +IM Data_all_Acks [68 ] 68 +IM Ack [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [0 ] 0 -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [0 ] 0 -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 124 +M_I Load [0 ] 0 +M_I Ifetch [0 ] 0 +M_I Store [0 ] 0 +M_I Inv [0 ] 0 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [124 ] 124 -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GET_INSTR 300 -L1_GETS 209 -L1_GETX 71 -L1_UPGRADE 0 -L1_PUTX 124 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 43 -L2_Replacement_clean 496 -Mem_Data 547 -Mem_Ack 539 -WB_Data 62 -WB_Data_clean 0 -Ack 0 -Ack_all 369 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 272 -MEM_Inv 0 +L1_GET_INSTR [300 ] 300 +L1_GETS [209 ] 209 +L1_GETX [71 ] 71 +L1_UPGRADE [0 ] 0 +L1_PUTX [124 ] 124 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [43 ] 43 +L2_Replacement_clean [496 ] 496 +Mem_Data [547 ] 547 +Mem_Ack [539 ] 539 +WB_Data [62 ] 62 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [369 ] 369 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [272 ] 272 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 291 -NP L1_GETS 192 -NP L1_GETX 64 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- +NP L1_GET_INSTR [291 ] 291 +NP L1_GETS [192 ] 192 +NP L1_GETX [64 ] 64 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 -SS L1_GET_INSTR 9 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 286 -SS MEM_Inv 0 <-- +SS L1_GET_INSTR [9 ] 9 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_UPGRADE [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [286 ] 286 +SS MEM_Inv [0 ] 0 -M L1_GET_INSTR 0 <-- -M L1_GETS 12 -M L1_GETX 4 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 39 -M L2_Replacement_clean 69 -M MEM_Inv 0 <-- +M L1_GET_INSTR [0 ] 0 +M L1_GETS [12 ] 12 +M L1_GETX [4 ] 4 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [39 ] 39 +M L2_Replacement_clean [69 ] 69 +M MEM_Inv [0 ] 0 -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 124 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 4 -MT L2_Replacement_clean 141 -MT MEM_Inv 0 <-- +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [124 ] 124 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [4 ] 4 +MT L2_Replacement_clean [141 ] 141 +MT MEM_Inv [0 ] 0 -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 5 -M_I L1_GETX 3 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 539 -M_I MEM_Inv 0 <-- +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [5 ] 5 +M_I L1_GETX [3 ] 3 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [539 ] 539 +M_I MEM_Inv [0 ] 0 -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 2 -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 2 -MT_I MEM_Inv 0 <-- +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [2 ] 2 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [2 ] 2 +MT_I MEM_Inv [0 ] 0 -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 60 -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 81 +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [60 ] 60 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [81 ] 81 -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 286 +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [286 ] 286 -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 192 -ISS MEM_Inv 0 <-- +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [192 ] 192 +ISS MEM_Inv [0 ] 0 -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 291 -IS MEM_Inv 0 <-- +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [291 ] 291 +IS MEM_Inv [0 ] 0 -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 64 -IM MEM_Inv 0 <-- +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [64 ] 64 +IM MEM_Inv [0 ] 0 -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [0 ] 0 +SS_MB MEM_Inv [0 ] 0 -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 272 -MT_MB MEM_Inv 0 <-- +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [272 ] 272 +MT_MB MEM_Inv [0 ] 0 -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 650 memory_reads: 547 memory_writes: 103 @@ -551,67 +556,66 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 26 14 0 49 21 21 42 25 6 4 7 4 24 42 26 3 5 7 7 18 10 29 15 50 19 5 6 16 14 24 19 92 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 547 -Data 103 -Memory_Data 547 -Memory_Ack 103 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 436 +Fetch [547 ] 547 +Data [103 ] 103 +Memory_Data [547 ] 547 +Memory_Ack [103 ] 103 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [436 ] 436 - Transitions - -I Fetch 547 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I Fetch [547 ] 547 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 -M Data 103 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 436 +M Data [103 ] 103 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [436 ] 436 -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 547 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [547 ] 547 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 103 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [103 ] 103 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Jan 28 2010 13:54:58 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 13:57:44 -M5 executing on svvint03 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:31:34 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 21475 # Simulator instruction rate (inst/s) -host_mem_usage 214848 # Number of bytes of host memory used -host_seconds 0.12 # Real time elapsed on the host -host_tick_rate 863649 # Simulator tick rate (ticks/s) +host_inst_rate 25769 # Simulator instruction rate (inst/s) +host_mem_usage 211408 # Number of bytes of host memory used +host_seconds 0.10 # Real time elapsed on the host +host_tick_rate 1036329 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000104 # Number of seconds simulated diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,162 +65,27 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true -buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] +[system.dir_cntrl0] type=Directory_Controller children=directory memBuffer buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory +directory=system.dir_cntrl0.directory directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -241,6 +106,146 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:08:15 +Real time: Aug/05/2010 10:37:10 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.51 -Virtual_time_in_minutes: 0.0085 -Virtual_time_in_hours: 0.000141667 -Virtual_time_in_days: 5.90278e-06 +Virtual_time_in_seconds: 0.41 +Virtual_time_in_minutes: 0.00683333 +Virtual_time_in_hours: 0.000113889 +Virtual_time_in_days: 4.74537e-06 Ruby_current_time: 85988 Ruby_start_time: 0 Ruby_cycles: 85988 -mbytes_resident: 33.25 -mbytes_total: 33.2578 +mbytes_resident: 33.6484 +mbytes_total: 33.6562 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 85989 [ 85989 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 85989 ] Busy Controller Counts: L2Cache-0:0 @@ -82,9 +71,23 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 2 max: 269 count: 3294 average: 25.1044 | standard deviation: 56.2234 | 0 2784 0 0 0 0 0 0 0 69 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 80 86 86 80 64 7 5 1 2 0 2 4 2 1 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 2 max: 227 count: 2585 average: 18.8561 | standard deviation: 48.7313 | 0 2315 0 0 0 0 0 0 0 27 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 48 53 42 50 34 2 4 1 1 0 2 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_NULL: [binsize: 2 max: 267 count: 415 average: 61.0506 | standard deviation: 78.3756 | 0 233 0 0 0 0 0 0 0 42 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 32 18 42 18 23 1 0 0 1 0 0 1 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 2 max: 269 count: 294 average: 29.3027 | standard deviation: 60.9274 | 0 236 0 0 0 0 0 0 0 0 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 2 12 7 4 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +119,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7143 -page_faults: 2153 +page_reclaims: 7386 +page_faults: 2090 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,6 +128,14 @@ Network Stats ------------- +total_msg_count_Request_Control: 2811 22488 +total_msg_count_Response_Data: 2562 184464 +total_msg_count_ResponseL2hit_Data: 249 17928 +total_msg_count_Writeback_Data: 1737 125064 +total_msg_count_Writeback_Control: 6480 51840 +total_msg_count_Unblock_Control: 2810 22480 +total_msgs: 16649 total_bytes: 424264 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.212617 @@ -190,972 +201,966 @@ outgoing_messages_switch_3_link_2_Writeback_Control: 745 5960 [ 0 411 334 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Unblock_Control: 427 3416 [ 0 0 427 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -L1_Replacement 506 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 510 -Writeback_Ack 0 -Writeback_Ack_Data 502 -Writeback_Nack 0 -All_acks 58 -Use_Timeout 509 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +L1_Replacement [506 ] 506 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [510 ] 510 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [502 ] 502 +Writeback_Nack [0 ] 0 +All_acks [58 ] 58 +Use_Timeout [509 ] 509 - Transitions - -I Load 182 -I Ifetch 270 -I Store 58 -I L1_Replacement 0 <-- -I Inv 0 <-- +I Load [182 ] 182 +I Ifetch [270 ] 270 +I Store [58 ] 58 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 -M Load 82 -M Ifetch 1224 -M Store 33 -M L1_Replacement 406 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- +M Load [82 ] 82 +M Ifetch [1224 ] 1224 +M Store [33 ] 33 +M L1_Replacement [406 ] 406 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 -M_W Load 49 -M_W Ifetch 1091 -M_W Store 7 -M_W L1_Replacement 4 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 444 +M_W Load [49 ] 49 +M_W Ifetch [1091 ] 1091 +M_W Store [7 ] 7 +M_W L1_Replacement [4 ] 4 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [444 ] 444 -MM Load 99 -MM Ifetch 0 <-- -MM Store 114 -MM L1_Replacement 96 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- +MM Load [99 ] 99 +MM Ifetch [0 ] 0 +MM Store [114 ] 114 +MM L1_Replacement [96 ] 96 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 -MM_W Load 3 -MM_W Ifetch 0 <-- -MM_W Store 82 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 65 +MM_W Load [3 ] 3 +MM_W Ifetch [0 ] 0 +MM_W Store [82 ] 82 +MM_W L1_Replacement [0 ] 0 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [65 ] 65 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 58 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [58 ] 58 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 58 +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [58 ] 58 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 452 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [452 ] 452 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 502 -MI Writeback_Nack 0 <-- +MI Load [0 ] 0 +MI Ifetch [0 ] 0 +MI Store [0 ] 0 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [502 ] 502 +MI Writeback_Nack [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GETS 455 -L1_GETX 58 -L1_PUTO 0 -L1_PUTX 502 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 44 -Data 44 -Data_Exclusive 383 -L1_WBCLEANDATA 396 -L1_WBDIRTYDATA 106 -Writeback_Ack 411 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 510 -L2_Replacement 411 +L1_GETS [455 ] 455 +L1_GETX [58 ] 58 +L1_PUTO [0 ] 0 +L1_PUTX [502 ] 502 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [44 ] 44 +Data [44 ] 44 +Data_Exclusive [383 ] 383 +L1_WBCLEANDATA [396 ] 396 +L1_WBDIRTYDATA [106 ] 106 +Writeback_Ack [411 ] 411 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [510 ] 510 +L2_Replacement [411 ] 411 - Transitions - -NP L1_GETS 383 -NP L1_GETX 44 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- +NP L1_GETS [383 ] 383 +NP L1_GETX [44 ] 44 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 502 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [502 ] 502 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 -M L1_GETS 69 -M L1_GETX 14 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 411 +M L1_GETS [69 ] 69 +M L1_GETX [14 ] 14 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [411 ] 411 -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 396 -ILXW L1_WBDIRTYDATA 106 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [396 ] 396 +ILXW L1_WBDIRTYDATA [106 ] 106 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 383 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 383 -IGS L2_Replacement 0 <-- +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [383 ] 383 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [383 ] 383 +IGS L2_Replacement [0 ] 0 -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 44 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [44 ] 44 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 44 -IGMO Exclusive_Unblock 44 -IGMO L2_Replacement 0 <-- +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [44 ] 44 +IGMO Exclusive_Unblock [44 ] 44 +IGMO L2_Replacement [0 ] 0 -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 14 -MM L2_Replacement 0 <-- +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [14 ] 14 +MM L2_Replacement [0 ] 0 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 69 -OO L2_Replacement 0 <-- +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [69 ] 69 +OO L2_Replacement [0 ] 0 -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 -MI L1_GETS 3 -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 411 -MI L2_Replacement 0 <-- +MI L1_GETS [3 ] 3 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [411 ] 411 +MI L2_Replacement [0 ] 0 -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 504 memory_reads: 427 memory_writes: 77 @@ -1175,201 +1180,200 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 35 20 20 28 21 5 3 6 4 21 40 20 3 4 5 7 13 10 16 14 41 16 5 5 12 12 18 14 58 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 44 -GETS 383 -PUTX 411 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 426 -Clean_Writeback 334 -Dirty_Writeback 77 -Memory_Data 427 -Memory_Ack 77 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [44 ] 44 +GETS [383 ] 383 +PUTX [411 ] 411 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [426 ] 426 +Clean_Writeback [334 ] 334 +Dirty_Writeback [77 ] 77 +Memory_Data [427 ] 427 +Memory_Ack [77 ] 77 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 44 -I GETS 383 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 75 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [44 ] 44 +I GETS [383 ] 383 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [75 ] 75 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -M GETX 0 <-- -M GETS 0 <-- -M PUTX 411 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [411 ] 411 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 382 -IS Memory_Data 383 -IS Memory_Ack 1 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [382 ] 382 +IS Memory_Data [383 ] 383 +IS Memory_Ack [1 ] 1 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 44 -MM Memory_Data 44 -MM Memory_Ack 1 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [44 ] 44 +MM Memory_Data [44 ] 44 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 334 -MI Dirty_Writeback 77 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [334 ] 334 +MI Dirty_Writeback [77 ] 77 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,10 @@ All Rights Reserved -M5 compiled Jan 28 2010 14:49:51 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:08:15 -M5 executing on svvint05 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:37:10 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,9 +1,9 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 14317 # Simulator instruction rate (inst/s) -host_mem_usage 214996 # Number of bytes of host memory used -host_seconds 0.18 # Real time elapsed on the host -host_tick_rate 477706 # Simulator tick rate (ticks/s) +host_inst_rate 19822 # Simulator instruction rate (inst/s) +host_mem_usage 211548 # Number of bytes of host memory used +host_seconds 0.13 # Real time elapsed on the host +host_tick_rate 661411 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated sim_seconds 0.000086 # Number of seconds simulated diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,172 +65,30 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 -num_int_nodes=4 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 +memBuffer=system.dir_cntrl0.memBuffer number_of_TBEs=256 recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node -int_node=2 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -size=134217728 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -251,6 +109,154 @@ tFaw=0 version=0 +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar +num_int_nodes=4 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.l2_cntrl0 +int_node=1 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=2 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,12 +13,12 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered -virtual_net_2: active, ordered -virtual_net_3: active, unordered +virtual_net_2: active, unordered +virtual_net_3: active, ordered virtual_net_4: active, unordered virtual_net_5: active, ordered virtual_net_6: inactive @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 15:55:46 +Real time: Aug/05/2010 10:43:25 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.35 -Virtual_time_in_minutes: 0.00583333 -Virtual_time_in_hours: 9.72222e-05 -Virtual_time_in_days: 4.05093e-06 +Virtual_time_in_seconds: 0.25 +Virtual_time_in_minutes: 0.00416667 +Virtual_time_in_hours: 6.94444e-05 +Virtual_time_in_days: 2.89352e-06 -Ruby_current_time: 90308 +Ruby_current_time: 92099 Ruby_start_time: 0 -Ruby_cycles: 90308 +Ruby_cycles: 92099 -mbytes_resident: 33.1172 -mbytes_total: 33.125 +mbytes_resident: 33.5859 +mbytes_total: 33.5938 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 90309 [ 90309 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 92100 ] Busy Controller Counts: L1Cache-0:0 @@ -81,10 +70,32 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 283 count: 3294 average: 26.4159 | standard deviation: 58.1846 | 0 2776 0 0 0 0 0 0 0 0 0 0 0 76 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 89 61 81 78 45 5 4 1 0 2 20 13 13 11 10 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 283 count: 2585 average: 19.2785 | standard deviation: 49.8133 | 0 2315 0 0 0 0 0 0 0 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44 44 38 49 22 3 4 0 0 0 9 11 3 8 6 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 273 count: 415 average: 66.3494 | standard deviation: 81.4668 | 0 233 0 0 0 0 0 0 0 0 0 0 0 33 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 31 15 34 18 20 1 0 1 0 2 6 2 10 2 2 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 259 count: 294 average: 32.8027 | standard deviation: 63.5503 | 0 228 0 0 0 0 0 0 0 0 0 0 0 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 2 9 11 3 1 0 0 0 0 5 0 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 2 max: 293 count: 3294 average: 26.9596 | standard deviation: 59.7209 | 0 2781 0 0 0 0 0 0 0 0 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 2 max: 293 count: 2585 average: 18.7741 | standard deviation: 50.0281 | 0 2315 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 2 max: 277 count: 415 average: 72.1108 | standard deviation: 82.9193 | 0 233 0 0 0 0 0 0 0 0 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 277 count: 294 average: 35.1973 | standard deviation: 68.9222 | 0 233 0 0 0 0 0 0 0 0 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 2781 average: 2 | standard deviation: 0 | 0 0 2781 ] +miss_latency_L2Cache: [binsize: 1 max: 21 count: 23 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 ] +miss_latency_Directory: [binsize: 2 max: 293 count: 490 average: 168.898 | standard deviation: 16.9003 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 79 76 50 53 117 4 3 4 1 6 13 21 19 9 22 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 2 0 1 1 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 169 count: 1 average: 169 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 489 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 293 count: 261 average: 167.479 | standard deviation: 13.0564 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 49 27 34 54 2 1 3 1 3 3 15 14 5 9 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 21 count: 9 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 ] +miss_latency_LD_Directory: [binsize: 2 max: 277 count: 173 average: 169.197 | standard deviation: 16.5371 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 15 18 15 50 1 2 0 0 2 10 4 3 2 10 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 21 count: 5 average: 21 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 ] +miss_latency_ST_Directory: [binsize: 2 max: 277 count: 56 average: 174.589 | standard deviation: 28.9061 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 6 12 5 4 13 1 0 1 0 1 0 2 2 2 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -116,8 +127,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 7136 -page_faults: 2141 +page_reclaims: 7341 +page_faults: 2084 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -125,788 +136,896 @@ Network Stats ------------- +total_msg_count_Request_Control: 3012 24096 +total_msg_count_Response_Data: 1470 105840 +total_msg_count_ResponseL2hit_Data: 69 4968 +total_msg_count_Writeback_Data: 1782 128304 +total_msg_count_Writeback_Control: 1206 9648 +total_msgs: 7539 total_bytes: 272856 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.160659 - links_utilized_percent_switch_0_link_0: 0.0646399 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.256677 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.167897 + links_utilized_percent_switch_0_link_0: 0.0626635 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.27313 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.0939286 - links_utilized_percent_switch_1_link_0: 0.0641693 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.123688 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0864762 + links_utilized_percent_switch_1_link_0: 0.0682825 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.10467 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.120795 - links_utilized_percent_switch_2_link_0: 0.0213436 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.220246 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.131387 + links_utilized_percent_switch_2_link_0: 0.023358 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.239416 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.200204 - links_utilized_percent_switch_3_link_0: 0.25856 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.256677 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.0853745 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.205739 + links_utilized_percent_switch_3_link_0: 0.250654 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.27313 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.0934321 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 442 31824 [ 0 442 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 76 5472 [ 0 76 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 8 64 [ 0 8 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 518 4144 [ 0 0 0 0 518 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 452 32544 [ 0 452 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 50 400 [ 0 50 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 447 3576 [ 0 0 0 447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 81 5832 [ 0 81 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 366 2928 [ 0 366 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 490 35280 [ 0 0 0 0 490 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 23 1656 [ 0 0 0 0 23 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 513 4104 [ 0 513 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 502 36144 [ 0 0 0 0 502 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 491 3928 [ 0 0 491 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 92 6624 [ 0 0 0 0 92 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 402 3216 [ 0 0 0 0 402 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 270 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: nan + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 243 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 243 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - --- L1Cache 0 --- + system.l1_cntrl0.sequencer.dcache_request_type_LD: 74.8971% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 25.1029% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 243 100% + + --- L1Cache --- - Event Counts - -Load 415 -Ifetch 2585 -Store 294 -L1_Replacement 502 -Data_Shared 59 -Data_Owner 0 -Data_All_Tokens 459 -Ack 8 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 -Request_Timeout 0 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 458 +Load [415 ] 415 +Ifetch [2585 ] 2585 +Store [294 ] 294 +Atomic [0 ] 0 +L1_Replacement [506 ] 506 +Data_Shared [18 ] 18 +Data_Owner [0 ] 0 +Data_All_Tokens [495 ] 495 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Request_Timeout [0 ] 0 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [494 ] 494 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 182 -NP Ifetch 270 -NP Store 58 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP Load [182 ] 182 +NP Ifetch [270 ] 270 +NP Store [58 ] 58 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S Load 30 -S Ifetch 188 -S Store 8 -S L1_Replacement 50 -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S Load [6 ] 6 +S Ifetch [44 ] 44 +S Store [3 ] 3 +S Atomic [0 ] 0 +S L1_Replacement [15 ] 15 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M Load 67 -M Ifetch 1196 -M Store 29 -M L1_Replacement 356 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- +M Load [78 ] 78 +M Ifetch [1233 ] 1233 +M Store [31 ] 31 +M Atomic [0 ] 0 +M L1_Replacement [391 ] 391 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -MM Load 96 -MM Ifetch 0 <-- -MM Store 111 -MM L1_Replacement 96 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 0 <-- +MM Load [98 ] 98 +MM Ifetch [0 ] 0 +MM Store [107 ] 107 +MM Atomic [0 ] 0 +MM L1_Replacement [96 ] 96 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [0 ] 0 -M_W Load 34 -M_W Ifetch 931 -M_W Store 3 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 389 +M_W Load [47 ] 47 +M_W Ifetch [1038 ] 1038 +M_W Store [6 ] 6 +M_W Atomic [0 ] 0 +M_W L1_Replacement [4 ] 4 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [0 ] 0 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [427 ] 427 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -MM_W Load 6 -MM_W Ifetch 0 <-- -MM_W Store 85 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 69 +MM_W Load [4 ] 4 +MM_W Ifetch [0 ] 0 +MM_W Store [89 ] 89 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [0 ] 0 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [0 ] 0 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [67 ] 67 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 58 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 0 <-- -IM Request_Timeout 0 <-- +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [0 ] 0 +IM Data_Shared [0 ] 0 +IM Data_Owner [0 ] 0 +IM Data_All_Tokens [58 ] 58 +IM Ack [0 ] 0 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [0 ] 0 +IM Request_Timeout [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 8 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [3 ] 3 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [0 ] 0 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [0 ] 0 +OM Request_Timeout [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 59 -IS Data_Owner 0 <-- -IS Data_All_Tokens 393 -IS Ack 7 -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 0 <-- -IS Request_Timeout 0 <-- +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [0 ] 0 +IS Data_Shared [18 ] 18 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [434 ] 434 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [0 ] 0 +IS Request_Timeout [0 ] 0 -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 491 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 491 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 88.391% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 11.609% - --- L2Cache 0 --- + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 491 100% + + --- L2Cache --- - Event Counts - -L1_GETS 445 -L1_GETS_Last_Token 7 -L1_GETX 66 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 463 -Writeback_Tokens 27 -Writeback_Shared_Data 0 -Writeback_All_Tokens 475 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 0 +L1_GETS [451 ] 451 +L1_GETS_Last_Token [1 ] 1 +L1_GETX [61 ] 61 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [500 ] 500 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [15 ] 15 +Writeback_All_Tokens [487 ] 487 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 - Transitions - -NP L1_GETS 386 -NP L1_GETX 48 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 27 -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 444 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP L1_GETS [434 ] 434 +NP L1_GETX [56 ] 56 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [15 ] 15 +NP Writeback_All_Tokens [487 ] 487 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [0 ] 0 -I L1_GETS 0 <-- -I L1_GETS_Last_Token 7 -I L1_GETX 1 -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 34 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 8 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [6 ] 6 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [0 ] 0 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [1 ] 1 +S L1_GETX [0 ] 0 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [14 ] 14 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 5 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 31 -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 23 -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [16 ] 16 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS 59 -M L1_GETX 12 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 398 -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- +M L1_GETS [17 ] 17 +M L1_GETX [4 ] 4 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [464 ] 464 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 523 - memory_reads: 442 - memory_writes: 81 - memory_refreshes: 189 - memory_total_request_delays: 199 - memory_delays_per_request: 0.380497 - memory_delays_in_input_queue: 67 +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 582 + memory_reads: 490 + memory_writes: 92 + memory_refreshes: 192 + memory_total_request_delays: 314 + memory_delays_per_request: 0.539519 + memory_delays_in_input_queue: 90 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 132 - memory_stalls_for_bank_busy: 41 + memory_delays_stalled_at_head_of_bank_queue: 224 + memory_stalls_for_bank_busy: 106 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 7 - memory_stalls_for_bus: 80 + memory_stalls_for_arbitration: 8 + memory_stalls_for_bus: 104 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 4 + memory_stalls_for_read_write_turnaround: 6 memory_stalls_for_read_read_turnaround: 0 - accesses_per_bank: 19 10 0 41 20 19 31 22 5 3 6 4 21 40 20 3 4 6 7 14 10 16 14 41 16 5 5 12 12 18 14 65 + accesses_per_bank: 20 13 0 46 20 20 38 23 5 5 7 4 24 42 25 3 4 6 7 14 10 21 14 46 16 5 5 12 14 18 16 79 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 63 -GETS 409 -Lockdown 0 -Unlockdown 0 -Own_Lock_or_Unlock 0 -Data_Owner 6 -Data_All_Tokens 75 -Ack_Owner 25 -Ack_Owner_All_Tokens 323 -Tokens 0 -Ack_All_Tokens 18 -Request_Timeout 0 -Memory_Data 442 -Memory_Ack 81 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [57 ] 57 +GETS [434 ] 434 +Lockdown [0 ] 0 +Unlockdown [0 ] 0 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [2 ] 2 +Data_All_Tokens [90 ] 90 +Ack_Owner [14 ] 14 +Ack_Owner_All_Tokens [374 ] 374 +Tokens [0 ] 0 +Ack_All_Tokens [14 ] 14 +Request_Timeout [0 ] 0 +Memory_Data [490 ] 490 +Memory_Ack [92 ] 92 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 49 -O GETS 393 -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 18 -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- +O GETX [56 ] 56 +O GETS [434 ] 434 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [14 ] 14 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX 5 -NO GETS 0 <-- -NO Lockdown 0 <-- -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 6 -NO Data_All_Tokens 75 -NO Ack_Owner 25 -NO Ack_Owner_All_Tokens 323 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NO GETX [1 ] 1 +NO GETS [0 ] 0 +NO Lockdown [0 ] 0 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [2 ] 2 +NO Data_All_Tokens [90 ] 90 +NO Ack_Owner [14 ] 14 +NO Ack_Owner_All_Tokens [374 ] 374 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -L GETX 0 <-- -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 0 <-- -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [0 ] 0 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX 9 -O_W GETS 16 -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 81 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [92 ] 92 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 442 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [490 ] 490 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,13 @@ All Rights Reserved -M5 compiled Jan 28 2010 15:54:34 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 15:55:46 -M5 executing on svvint04 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:43:25 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 90308 because target called exit() +Exiting @ tick 92099 because target called exit() diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 18406 # Simulator instruction rate (inst/s) -host_mem_usage 214900 # Number of bytes of host memory used -host_seconds 0.15 # Real time elapsed on the host -host_tick_rate 602029 # Simulator tick rate (ticks/s) +host_inst_rate 42948 # Simulator instruction rate (inst/s) +host_mem_usage 211392 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1534907 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000090 # Number of seconds simulated -sim_ticks 90308 # Number of ticks simulated +sim_seconds 0.000092 # Number of seconds simulated +sim_ticks 92099 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 90308 # number of cpu cycles simulated +system.cpu.numCycles 92099 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,7 +5,7 @@ [system] type=System -children=cpu physmem ruby +children=cpu dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem @@ -32,8 +32,8 @@ system=system tracer=system.cpu.tracer workload=system.cpu.workload -dcache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[1] -icache_port=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +dcache_port=system.l1_cntrl0.sequencer.port[1] +icache_port=system.l1_cntrl0.sequencer.port[0] [system.cpu.dtb] type=AlphaTLB @@ -54,7 +54,7 @@ env= errout=cerr euid=100 -executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/hello/bin/alpha/tru64/hello +executable=tests/test-progs/hello/bin/alpha/tru64/hello gid=100 input=cin max_stack_size=67108864 @@ -65,142 +65,29 @@ system=system uid=100 -[system.physmem] -type=PhysicalMemory -file= -latency=30 -latency_var=0 -null=false -range=0:134217727 -zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort - -[system.ruby] -type=RubySystem -children=debug network profiler tracer -block_size_bytes=64 -clock=1 -debug=system.ruby.debug -mem_size=134217728 -network=system.ruby.network -profiler=system.ruby.profiler -random_seed=1234 -randomization=false -stats_filename=ruby.stats -tracer=system.ruby.tracer - -[system.ruby.debug] -type=RubyDebug -filter_string=none -output_filename=none -protocol_trace=false -start_time=1 -verbosity_string=none - -[system.ruby.network] -type=SimpleNetwork -children=topology -adaptive_routing=true +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter buffer_size=0 -control_msg_size=8 -endpoint_bandwidth=10000 -link_latency=1 -number_of_virtual_networks=10 -topology=system.ruby.network.topology - -[system.ruby.network.topology] -type=Topology -children=ext_links0 ext_links1 int_links0 int_links1 -ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 -int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 -num_int_nodes=3 -print_config=false - -[system.ruby.network.topology.ext_links0] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node -int_node=0 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu.icache_port system.cpu.dcache_port - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1] -type=ExtLink -children=ext_node -bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node -int_node=1 -latency=1 -weight=1 - -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false recycle_latency=10 transitions_per_cycle=32 version=0 -[system.ruby.network.topology.ext_links1.ext_node.directory] +[system.dir_cntrl0.directory] type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 size=134217728 +use_map=false version=0 -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] +[system.dir_cntrl0.memBuffer] type=RubyMemoryControl bank_bit_0=8 bank_busy_time=11 @@ -221,6 +108,136 @@ tFaw=0 version=0 +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu.icache_port system.cpu.dcache_port + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.physmem] +type=PhysicalMemory +file= +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.l1_cntrl0.sequencer.physMemPort + +[system.ruby] +type=RubySystem +children=debug network profiler tracer +block_size_bytes=64 +clock=1 +debug=system.ruby.debug +mem_size=134217728 +network=system.ruby.network +no_mem_vec=false +profiler=system.ruby.profiler +random_seed=1234 +randomization=false +stats_filename=ruby.stats +tracer=system.ruby.tracer + +[system.ruby.debug] +type=RubyDebug +filter_string=none +output_filename=none +protocol_trace=false +start_time=1 +verbosity_string=none + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=10000 +link_latency=1 +number_of_virtual_networks=10 +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 int_links0 int_links1 +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar +num_int_nodes=3 +print_config=false + +[system.ruby.network.topology.ext_links0] +type=ExtLink +bw_multiplier=64 +ext_node=system.l1_cntrl0 +int_node=0 +latency=1 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=ExtLink +bw_multiplier=64 +ext_node=system.dir_cntrl0 +int_node=1 +latency=1 +weight=1 + [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,14 +13,14 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar -virtual_net_0: active, unordered -virtual_net_1: active, unordered +virtual_net_0: active, ordered +virtual_net_1: active, ordered virtual_net_2: active, unordered virtual_net_3: active, unordered -virtual_net_4: active, ordered -virtual_net_5: active, ordered +virtual_net_4: active, unordered +virtual_net_5: active, unordered virtual_net_6: inactive virtual_net_7: inactive virtual_net_8: inactive @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Jan/28/2010 11:48:25 +Real time: Aug/05/2010 14:44:19 Profiler Stats -------------- @@ -43,31 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.33 -Virtual_time_in_minutes: 0.0055 -Virtual_time_in_hours: 9.16667e-05 -Virtual_time_in_days: 3.81944e-06 +Virtual_time_in_seconds: 0.21 +Virtual_time_in_minutes: 0.0035 +Virtual_time_in_hours: 5.83333e-05 +Virtual_time_in_days: 2.43056e-06 -Ruby_current_time: 81672 +Ruby_current_time: 78408 Ruby_start_time: 0 -Ruby_cycles: 81672 +Ruby_cycles: 78408 -mbytes_resident: 31.8555 -mbytes_total: 31.8633 +mbytes_resident: 33.3242 +mbytes_total: 33.332 resident_ratio: 1 -Total_misses: 0 -total_misses: 0 [ 0 ] -user_misses: 0 [ 0 ] -supervisor_misses: 0 [ 0 ] - -ruby_cycles_executed: 81673 [ 81673 ] - -transactions_started: 0 [ 0 ] -transactions_ended: 0 [ 0 ] -cycles_per_transaction: 0 [ 0 ] -misses_per_transaction: 0 [ 0 ] - +ruby_cycles_executed: [ 78409 ] Busy Controller Counts: L1Cache-0:0 @@ -80,10 +69,32 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 2 max: 333 count: 3294 average: 23.7942 | standard deviation: 53.6415 | 0 2853 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 87 74 46 111 83 4 0 4 2 0 2 2 0 0 1 1 2 0 0 0 2 2 2 3 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_1: [binsize: 2 max: 243 count: 2585 average: 17.6507 | standard deviation: 45.0947 | 0 2337 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 38 47 26 56 63 2 0 2 1 0 1 2 0 0 0 1 1 0 0 0 1 1 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 2 max: 333 count: 415 average: 57.9108 | standard deviation: 76.4181 | 0 269 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 41 16 18 39 18 1 0 1 0 0 1 0 0 0 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 2 max: 333 count: 294 average: 29.6531 | standard deviation: 64.3241 | 0 247 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 11 2 16 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 1 0 0 1 ] +miss_latency: [binsize: 2 max: 320 count: 3294 average: 22.8033 | standard deviation: 52.924 | 0 2784 0 0 0 0 69 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 1 max: 181 count: 2585 average: 16.5544 | standard deviation: 44.4412 | 0 0 2315 0 0 0 0 0 0 0 0 0 22 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_LD: [binsize: 2 max: 319 count: 415 average: 57.4602 | standard deviation: 75.1127 | 0 233 0 0 0 0 36 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 320 count: 294 average: 28.8265 | standard deviation: 63.3064 | 0 236 0 0 0 0 11 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 2784 average: 2 | standard deviation: 0 | 0 0 2784 ] +miss_latency_L2Cache: [binsize: 1 max: 12 count: 69 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 69 ] +miss_latency_Directory: [binsize: 2 max: 320 count: 441 average: 155.823 | standard deviation: 21.7136 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 35 77 96 65 60 75 2 0 2 1 4 0 1 2 4 4 1 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 3 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 158 count: 1 average: 158 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +imcomplete_dir_Times: 440 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 2 count: 2315 average: 2 | standard deviation: 0 | 0 0 2315 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 12 count: 22 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 22 ] +miss_latency_IFETCH_Directory: [binsize: 1 max: 181 count: 248 average: 152.819 | standard deviation: 5.60689 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 17 19 16 48 18 11 31 24 15 37 0 1 0 0 0 0 0 0 0 3 0 0 0 0 0 0 1 1 0 0 2 0 1 1 2 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 233 average: 2 | standard deviation: 0 | 0 0 233 ] +miss_latency_LD_L2Cache: [binsize: 1 max: 12 count: 36 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 36 ] +miss_latency_LD_Directory: [binsize: 2 max: 319 count: 146 average: 157.178 | standard deviation: 25.3138 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 16 34 23 16 17 26 1 0 2 0 1 0 0 1 3 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 236 average: 2 | standard deviation: 0 | 0 0 236 ] +miss_latency_ST_L2Cache: [binsize: 1 max: 12 count: 11 average: 12 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 11 ] +miss_latency_ST_Directory: [binsize: 2 max: 320 count: 47 average: 167.468 | standard deviation: 46.1312 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 8 7 7 4 12 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 0 1 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -115,8 +126,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 6878 -page_faults: 2029 +page_reclaims: 7298 +page_faults: 2071 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -124,453 +135,665 @@ Network Stats ------------- +total_msg_count_Request_Control: 1323 10584 +total_msg_count_Response_Data: 1323 95256 +total_msg_count_Writeback_Data: 243 17496 +total_msg_count_Writeback_Control: 3582 28656 +total_msg_count_Unblock_Control: 1320 10560 +total_msgs: 7791 total_bytes: 162552 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.106447 - links_utilized_percent_switch_0_link_0: 0.0672507 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.145644 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.110878 + links_utilized_percent_switch_0_link_0: 0.0700502 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.151706 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152707 - links_utilized_percent_switch_1_link_0: 0.0364109 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.269003 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.159064 + links_utilized_percent_switch_1_link_0: 0.0379266 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.280201 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.207323 - links_utilized_percent_switch_2_link_0: 0.269003 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.145644 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.215954 + links_utilized_percent_switch_2_link_0: 0.280201 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.151706 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 425 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 0 441 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 81 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 344 0 0 425 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 440 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 441 31752 [ 0 0 0 0 441 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 425 3400 [ 0 0 0 425 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 441 3528 [ 0 0 441 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 81 5832 [ 0 0 0 0 0 81 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 769 6152 [ 0 0 425 0 0 344 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 440 3520 [ 0 0 0 0 0 440 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 248 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 248 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_misses_per_transaction: inf +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 270 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 270 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_IFETCH: 100% + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 248 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 248 average: 4 | standard deviation: 0 | 0 0 0 0 248 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 270 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 193 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 193 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_misses_per_transaction: inf +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 240 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 240 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 75.6477% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 24.3523% + system.l1_cntrl0.sequencer.dcache_request_type_LD: 75.8333% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 24.1667% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 193 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 8 count: 193 average: 7.25389 | standard deviation: 1.56292 | 0 0 0 0 36 0 0 0 157 ] + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 240 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_misses_per_transaction: nan +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 441 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.L2cacheMemory_request_type_LD: 33.1066% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 10.6576% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 56.2358% - --- L1Cache 0 --- + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 441 100% + + --- L1Cache --- - Event Counts - -Load 437 -Ifetch 2603 -Store 306 -L2_Replacement 425 -L1_to_L2 502 -L2_to_L1D 47 -L2_to_L1I 22 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 441 -Writeback_Ack 425 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 441 +Load [428 ] 428 +Ifetch [2597 ] 2597 +Store [302 ] 302 +L2_Replacement [425 ] 425 +L1_to_L2 [502 ] 502 +Trigger_L2_to_L1D [47 ] 47 +Trigger_L2_to_L1I [22 ] 22 +Complete_L2_to_L1 [69 ] 69 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [441 ] 441 +Writeback_Ack [425 ] 425 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [441 ] 441 - Transitions - -I Load 146 -I Ifetch 248 -I Store 47 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- +I Load [146 ] 146 +I Ifetch [248 ] 248 +I Store [47 ] 47 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 -M Load 131 -M Ifetch 2337 -M Store 36 -M L2_Replacement 344 -M L1_to_L2 397 -M L2_to_L1D 23 -M L2_to_L1I 22 -M Other_GETX 0 <-- -M Other_GETS 0 <-- +M Load [131 ] 131 +M Ifetch [2337 ] 2337 +M Store [36 ] 36 +M L2_Replacement [344 ] 344 +M L1_to_L2 [397 ] 397 +M Trigger_L2_to_L1D [23 ] 23 +M Trigger_L2_to_L1I [22 ] 22 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 -MM Load 138 -MM Ifetch 0 <-- -MM Store 211 -MM L2_Replacement 81 -MM L1_to_L2 105 -MM L2_to_L1D 24 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- +MM Load [138 ] 138 +MM Ifetch [0 ] 0 +MM Store [211 ] 211 +MM L2_Replacement [81 ] 81 +MM L1_to_L2 [105 ] 105 +MM Trigger_L2_to_L1D [24 ] 24 +MM Trigger_L2_to_L1I [0 ] 0 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 47 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [0 ] 0 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [47 ] 47 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 0 <-- -M_W All_acks_no_sharers 394 +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [0 ] 0 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [394 ] 394 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 47 +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [0 ] 0 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [0 ] 0 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [47 ] 47 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 394 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [0 ] 0 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [394 ] 394 -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 -MI Load 22 -MI Ifetch 18 -MI Store 12 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 425 +MI Load [13 ] 13 +MI Ifetch [12 ] 12 +MI Store [8 ] 8 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [425 ] 425 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [0 ] 0 +MT Complete_L2_to_L1 [45 ] 45 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [0 ] 0 +MMT Store [0 ] 0 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [0 ] 0 +MMT Complete_L2_to_L1 [24 ] 24 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 522 memory_reads: 441 memory_writes: 81 - memory_refreshes: 171 - memory_total_request_delays: 124 - memory_delays_per_request: 0.237548 + memory_refreshes: 164 + memory_total_request_delays: 147 + memory_delays_per_request: 0.281609 memory_delays_in_input_queue: 2 memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 122 - memory_stalls_for_bank_busy: 45 + memory_delays_stalled_at_head_of_bank_queue: 145 + memory_stalls_for_bank_busy: 27 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 8 + memory_stalls_for_arbitration: 6 memory_stalls_for_bus: 23 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 46 + memory_stalls_for_read_write_turnaround: 89 memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 18 10 0 36 20 19 31 22 5 4 7 4 22 41 22 3 4 6 7 13 10 18 14 41 16 5 5 12 13 18 14 62 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 106 -GETS 464 -PUT 425 -Unblock 440 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 344 -Writeback_Exclusive_Dirty 81 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 441 -Memory_Ack 81 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [53 ] 53 +GETS [410 ] 410 +PUT [425 ] 425 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [440 ] 440 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [344 ] 344 +Writeback_Exclusive_Dirty [81 ] 81 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [441 ] 441 +Memory_Ack [81 ] 81 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 425 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [425 ] 425 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -E GETX 47 -E GETS 394 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 0 <-- -NO_B Unblock 440 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- +E GETX [47 ] 47 +E GETS [394 ] 394 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 441 +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [440 ] 440 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [441 ] 441 -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 -WB GETX 4 -WB GETS 15 -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 344 -WB Writeback_Exclusive_Dirty 81 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -WB_E_W GETX 55 -WB_E_W GETS 55 -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 81 +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [4 ] 4 +WB GETS [14 ] 14 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [344 ] 344 +WB Writeback_Exclusive_Dirty [81 ] 81 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [2 ] 2 +WB_E_W GETS [2 ] 2 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,13 @@ All Rights Reserved -M5 compiled Jan 28 2010 11:30:01 -M5 revision 6068d4fc30d3+ 6931+ default qtip tip brad/rubycfg_regress_udpate -M5 started Jan 28 2010 11:48:25 -M5 executing on svvint06 +M5 compiled Aug 5 2010 14:43:33 +M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates +M5 started Aug 5 2010 14:44:19 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/00.hello/alpha/tru64/simple-timing-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... info: Increasing stack size by one page. Hello world! -Exiting @ tick 81672 because target called exit() +Exiting @ tick 78408 because target called exit() diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt --- a/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/00.hello/ref/alpha/tru64/simple-timing-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,13 +1,13 @@ ---------- Begin Simulation Statistics ---------- -host_inst_rate 32212 # Simulator instruction rate (inst/s) -host_mem_usage 212236 # Number of bytes of host memory used -host_seconds 0.08 # Real time elapsed on the host -host_tick_rate 1020887 # Simulator tick rate (ticks/s) +host_inst_rate 42947 # Simulator instruction rate (inst/s) +host_mem_usage 211060 # Number of bytes of host memory used +host_seconds 0.06 # Real time elapsed on the host +host_tick_rate 1306713 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_insts 2577 # Number of instructions simulated -sim_seconds 0.000082 # Number of seconds simulated -sim_ticks 81672 # Number of ticks simulated +sim_seconds 0.000078 # Number of seconds simulated +sim_ticks 78408 # Number of ticks simulated system.cpu.dtb.data_accesses 717 # DTB accesses system.cpu.dtb.data_acv 0 # DTB access violations system.cpu.dtb.data_hits 709 # DTB hits @@ -42,7 +42,7 @@ system.cpu.itb.write_hits 0 # DTB write hits system.cpu.itb.write_misses 0 # DTB write misses system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles -system.cpu.numCycles 81672 # number of cpu cycles simulated +system.cpu.numCycles 78408 # number of cpu cycles simulated system.cpu.num_insts 2577 # Number of instructions executed system.cpu.num_refs 717 # Number of memory references system.cpu.workload.PROG:num_syscalls 4 # Number of system calls diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,14 @@ [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.l1_cntrl0.sequencer.port[0] [system.cpu1] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.l1_cntrl1.sequencer.port[0] [system.cpu2] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.l1_cntrl2.sequencer.port[0] [system.cpu3] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.l1_cntrl3.sequencer.port[0] [system.cpu4] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.l1_cntrl4.sequencer.port[0] [system.cpu5] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.l1_cntrl5.sequencer.port[0] [system.cpu6] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.l1_cntrl6.sequencer.port[0] [system.cpu7] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,49 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.l1_cntrl7.sequencer.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 [system.funcmem] type=PhysicalMemory @@ -139,6 +189,387 @@ zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl1.sequencer.dcache +L1IcacheMemory=system.l1_cntrl1.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl1.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl1.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl1.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.l1_cntrl1.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl2.sequencer.dcache +L1IcacheMemory=system.l1_cntrl2.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl2.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl2.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl2.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.l1_cntrl2.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl3.sequencer.dcache +L1IcacheMemory=system.l1_cntrl3.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl3.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl3.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl3.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.l1_cntrl3.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl4.sequencer.dcache +L1IcacheMemory=system.l1_cntrl4.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl4.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=4 + +[system.l1_cntrl4.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl4.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl4.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.l1_cntrl4.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl5.sequencer.dcache +L1IcacheMemory=system.l1_cntrl5.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl5.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=5 + +[system.l1_cntrl5.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl5.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl5.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.l1_cntrl5.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl6.sequencer.dcache +L1IcacheMemory=system.l1_cntrl6.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl6.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=6 + +[system.l1_cntrl6.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl6.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl6.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.l1_cntrl6.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl7.sequencer.dcache +L1IcacheMemory=system.l1_cntrl7.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl7.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=7 + +[system.l1_cntrl7.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl7.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl7.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.l1_cntrl7.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -147,7 +578,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort [system.ruby] type=RubySystem @@ -188,505 +619,90 @@ children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +name=Crossbar num_int_nodes=11 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l1_cntrl1 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=1 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.l1_cntrl2 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=2 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links3] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node +ext_node=system.l1_cntrl3 int_node=3 latency=1 weight=1 -[system.ruby.network.topology.ext_links3.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=3 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links4] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node +ext_node=system.l1_cntrl4 int_node=4 latency=1 weight=1 -[system.ruby.network.topology.ext_links4.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=4 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links5] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node +ext_node=system.l1_cntrl5 int_node=5 latency=1 weight=1 -[system.ruby.network.topology.ext_links5.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=5 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links6] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node +ext_node=system.l1_cntrl6 int_node=6 latency=1 weight=1 -[system.ruby.network.topology.ext_links6.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=6 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links7] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node +ext_node=system.l1_cntrl7 int_node=7 latency=1 weight=1 -[system.ruby.network.topology.ext_links7.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=7 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links8] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node +ext_node=system.l2_cntrl0 int_node=8 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links9] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node +ext_node=system.dir_cntrl0 int_node=9 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:37:29 +Real time: Aug/05/2010 10:32:52 Profiler Stats -------------- -Elapsed_time_in_seconds: 43 -Elapsed_time_in_minutes: 0.716667 -Elapsed_time_in_hours: 0.0119444 -Elapsed_time_in_days: 0.000497685 +Elapsed_time_in_seconds: 45 +Elapsed_time_in_minutes: 0.75 +Elapsed_time_in_hours: 0.0125 +Elapsed_time_in_days: 0.000520833 -Virtual_time_in_seconds: 42.96 -Virtual_time_in_minutes: 0.716 -Virtual_time_in_hours: 0.0119333 -Virtual_time_in_days: 0.000497222 +Virtual_time_in_seconds: 43.61 +Virtual_time_in_minutes: 0.726833 +Virtual_time_in_hours: 0.0121139 +Virtual_time_in_days: 0.000504745 -Ruby_current_time: 3719757 +Ruby_current_time: 3732466 Ruby_start_time: 0 -Ruby_cycles: 3719757 +Ruby_cycles: 3732466 -mbytes_resident: 31.1289 -mbytes_total: 332.066 -resident_ratio: 0.0937548 +mbytes_resident: 32.6719 +mbytes_total: 32.6758 +resident_ratio: 1 -ruby_cycles_executed: [ 3719758 3719758 3719758 3719758 3719758 3719758 3719758 3719758 ] +ruby_cycles_executed: [ 3732467 3732467 3732467 3732467 3732467 3732467 3732467 3732467 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,26 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1207997 average: 1.94937 | standard deviation: 0.21925 | 0 61165 1146832 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1211683 average: 1.94861 | standard deviation: 0.220786 | 0 62264 1149419 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1096 count: 1207982 average: 47.2632 | standard deviation: 87.5809 | 820246 0 0 12973 11256 8994 17847 40609 25225 42554 9212 3741 16692 9471 11172 15656 163 11587 19417 8757 12623 971 6786 8002 7495 3787 2265 8848 5127 7731 3455 937 5328 4126 3619 4052 242 2825 4110 2460 2617 358 2236 2202 2247 1258 401 1959 1336 1484 1007 157 1157 1014 866 802 80 656 659 574 477 94 467 375 407 241 42 307 241 254 168 29 168 140 127 117 15 95 111 93 72 14 78 46 65 41 3 33 33 22 18 7 19 17 14 7 1 8 7 15 10 1 2 3 5 3 1 6 6 1 1 3 3 5 4 1 0 2 1 0 0 0 0 2 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 989 count: 785672 average: 30.8191 | standard deviation: 72.2854 | 626312 0 0 2843 2491 355 17847 15354 10445 19140 268 3733 7267 2205 5283 5517 159 5561 8454 3320 4992 966 1947 3616 2571 478 2264 3550 2053 3343 615 937 2397 1381 1550 1485 241 1150 1699 921 935 357 794 905 854 257 400 756 504 634 249 157 485 391 373 252 80 258 275 208 141 94 188 157 165 65 42 119 96 102 50 29 65 60 50 36 15 39 46 35 16 14 31 23 26 18 3 18 12 6 5 7 5 7 5 2 1 2 2 9 4 1 2 1 3 0 1 4 3 1 1 3 3 1 1 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 1096 count: 422310 average: 77.856 | standard deviation: 103.83 | 193934 0 0 10130 8765 8639 0 25255 14780 23414 8944 8 9425 7266 5889 10139 4 6026 10963 5437 7631 5 4839 4386 4924 3309 1 5298 3074 4388 2840 0 2931 2745 2069 2567 1 1675 2411 1539 1682 1 1442 1297 1393 1001 1 1203 832 850 758 0 672 623 493 550 0 398 384 366 336 0 279 218 242 176 0 188 145 152 118 0 103 80 77 81 0 56 65 58 56 0 47 23 39 23 0 15 21 16 13 0 14 10 9 5 0 6 5 6 6 0 0 2 2 3 0 2 3 0 0 0 0 4 3 0 0 1 1 0 0 0 0 1 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1116 count: 1211667 average: 47.2793 | standard deviation: 87.5084 | 822593 0 0 12940 11442 8952 17968 40920 25037 42608 9111 3731 16764 9493 11124 15765 168 11624 19400 8960 12651 1020 6792 7916 7419 3810 2242 8892 5237 7918 3567 908 5426 4261 3691 4138 229 2997 4070 2559 2629 413 2278 2171 2186 1184 403 1886 1354 1493 980 182 1193 1045 766 749 84 613 766 538 422 74 458 398 358 222 55 291 255 219 157 23 185 169 140 105 13 91 97 71 59 9 70 50 53 39 4 32 39 27 36 4 17 17 18 22 1 16 12 9 7 3 6 7 8 7 1 5 4 3 1 0 3 2 3 5 0 2 2 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 8 max: 1116 count: 788971 average: 30.7783 | standard deviation: 72.1085 | 629001 0 0 2823 2652 348 17967 15405 10362 19276 245 3726 7199 2175 5268 5722 162 5601 8324 3338 5036 1020 2062 3453 2491 465 2242 3570 2156 3427 648 908 2389 1458 1557 1432 228 1201 1708 988 917 412 805 917 824 253 401 791 539 609 268 182 512 400 310 268 83 247 288 207 118 74 176 170 139 63 55 103 86 84 57 23 70 66 51 30 13 29 37 28 19 9 21 18 23 10 4 9 17 11 10 4 6 4 11 7 1 7 4 2 4 3 2 2 4 2 1 3 2 1 1 0 1 1 2 2 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 8 max: 1026 count: 422696 average: 78.0789 | standard deviation: 103.87 | 193592 0 0 10117 8790 8604 1 25515 14675 23332 8866 5 9565 7318 5856 10043 6 6023 11076 5622 7615 0 4730 4463 4928 3345 0 5322 3081 4491 2919 0 3037 2803 2134 2706 1 1796 2362 1571 1712 1 1473 1254 1362 931 2 1095 815 884 712 0 681 645 456 481 1 366 478 331 304 0 282 228 219 159 0 188 169 135 100 0 115 103 89 75 0 62 60 43 40 0 49 32 30 29 0 23 22 16 26 0 11 13 7 15 0 9 8 7 3 0 4 5 4 5 0 2 2 2 0 0 2 1 1 3 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 8 max: 1116 count: 1211667 average: 47.2793 | standard deviation: 87.5084 | 822593 0 0 12940 11442 8952 17968 40920 25037 42608 9111 3731 16764 9493 11124 15765 168 11624 19400 8960 12651 1020 6792 7916 7419 3810 2242 8892 5237 7918 3567 908 5426 4261 3691 4138 229 2997 4070 2559 2629 413 2278 2171 2186 1184 403 1886 1354 1493 980 182 1193 1045 766 749 84 613 766 538 422 74 458 398 358 222 55 291 255 219 157 23 185 169 140 105 13 91 97 71 59 9 70 50 53 39 4 32 39 27 36 4 17 17 18 22 1 16 12 9 7 3 6 7 8 7 1 5 4 3 1 0 3 2 3 5 0 2 2 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 8 max: 1116 count: 788971 average: 30.7783 | standard deviation: 72.1085 | 629001 0 0 2823 2652 348 17967 15405 10362 19276 245 3726 7199 2175 5268 5722 162 5601 8324 3338 5036 1020 2062 3453 2491 465 2242 3570 2156 3427 648 908 2389 1458 1557 1432 228 1201 1708 988 917 412 805 917 824 253 401 791 539 609 268 182 512 400 310 268 83 247 288 207 118 74 176 170 139 63 55 103 86 84 57 23 70 66 51 30 13 29 37 28 19 9 21 18 23 10 4 9 17 11 10 4 6 4 11 7 1 7 4 2 4 3 2 2 4 2 1 3 2 1 1 0 1 1 2 2 0 0 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 8 max: 1026 count: 422696 average: 78.0789 | standard deviation: 103.87 | 193592 0 0 10117 8790 8604 1 25515 14675 23332 8866 5 9565 7318 5856 10043 6 6023 11076 5622 7615 0 4730 4463 4928 3345 0 5322 3081 4491 2919 0 3037 2803 2134 2706 1 1796 2362 1571 1712 1 1473 1254 1362 931 2 1095 815 884 712 0 681 645 456 481 1 366 478 331 304 0 282 228 219 159 0 188 169 135 100 0 115 103 89 75 0 62 60 43 40 0 49 32 30 29 0 23 22 16 26 0 11 13 7 15 0 9 8 7 3 0 4 5 4 5 0 2 2 2 0 0 2 1 1 3 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -87,12 +100,12 @@ Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1070 count: 1901917 average: 23.6676 | standard deviation: 66.5163 | 1605803 77057 36746 50742 28570 31081 16600 13024 11911 7715 8177 3975 2999 2315 1628 1395 701 445 347 259 191 78 56 23 29 17 9 14 5 0 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1192255 average: 0.00257328 | standard deviation: 0.0573328 | 1189606 2240 399 10 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1070 count: 709662 average: 63.4255 | standard deviation: 96.6231 | 413548 77057 36746 50742 28570 31081 16600 13024 11911 7715 8177 3975 2999 2315 1628 1395 701 445 347 259 191 78 56 23 29 17 9 14 5 0 4 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 32 max: 1090 count: 1908755 average: 23.6627 | standard deviation: 66.4412 | 1611862 76809 36792 50911 28801 30966 17018 13313 12086 7932 7947 3970 3027 2294 1518 1343 664 492 318 214 183 105 50 55 26 29 8 8 8 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 3 count: 1196683 average: 0.00248604 | standard deviation: 0.0563214 | 1194112 2177 384 10 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 1090 count: 712072 average: 63.4252 | standard deviation: 96.4952 | 415179 76809 36792 50911 28801 30966 17018 13313 12086 7932 7947 3970 3027 2294 1518 1343 664 492 318 214 183 105 50 55 26 29 8 8 8 1 2 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 469671 average: 0.00546127 | standard deviation: 0.0851706 | 467524 1739 398 10 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 2 count: 722584 average: 0.000696113 | standard deviation: 0.0264364 | 722082 501 1 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 3 count: 471408 average: 0.0053266 | standard deviation: 0.0839969 | 469301 1713 384 10 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 1 count: 725275 average: 0.000639757 | standard deviation: 0.0252934 | 724811 464 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -103,10 +116,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 42 +user_time: 43 system_time: 0 -page_reclaims: 8989 -page_faults: 0 +page_reclaims: 7285 +page_faults: 1893 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -114,1380 +127,634 @@ Network Stats ------------- +total_msg_count_Control: 1167270 9338160 +total_msg_count_Request_Control: 1265816 10126528 +total_msg_count_Response_Data: 1414233 101824776 +total_msg_count_Response_Control: 1730577 13844616 +total_msgs: 5577896 total_bytes: 135134080 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.416622 - links_utilized_percent_switch_0_link_0: 0.1753 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.657944 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.415722 + links_utilized_percent_switch_0_link_0: 0.174622 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.656822 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Request_Control: 59677 477416 [ 59677 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 47767 3439224 [ 0 47767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 32078 256624 [ 0 32078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 49180 393440 [ 49180 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 40975 2950200 [ 0 40975 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 71523 572184 [ 0 30612 40911 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Request_Control: 59687 477496 [ 59687 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 47741 3437352 [ 0 47741 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 32062 256496 [ 0 32062 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 49236 393888 [ 49236 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 41051 2955672 [ 0 41051 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 71618 572944 [ 0 30582 41036 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.413921 - links_utilized_percent_switch_1_link_0: 0.174086 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.653756 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.415365 + links_utilized_percent_switch_1_link_0: 0.174713 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.656018 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 59368 474944 [ 59368 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 47459 3417048 [ 0 47459 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 31548 252384 [ 0 31548 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 48980 391840 [ 48980 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 40679 2928888 [ 0 40679 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 71272 570176 [ 0 30597 40675 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 59688 477504 [ 59688 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 47753 3438216 [ 0 47753 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 32223 257784 [ 0 32223 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 49214 393712 [ 49214 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 40992 2951424 [ 0 40992 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 71571 572568 [ 0 30632 40939 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.408998 - links_utilized_percent_switch_2_link_0: 0.173244 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.644752 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.412946 + links_utilized_percent_switch_2_link_0: 0.173394 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.652498 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 58740 469920 [ 58740 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 47251 3402072 [ 0 47251 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 31542 252336 [ 0 31542 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 48715 389720 [ 48715 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 40048 2883456 [ 0 40048 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 70517 564136 [ 0 30181 40336 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 59380 475040 [ 59380 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 47445 3416040 [ 0 47445 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 48904 391232 [ 48904 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 40786 2936592 [ 0 40786 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 71107 568856 [ 0 30529 40578 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.411754 - links_utilized_percent_switch_3_link_0: 0.172789 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.65072 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.410046 + links_utilized_percent_switch_3_link_0: 0.172873 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.647218 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Request_Control: 58992 471936 [ 58992 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 47078 3389616 [ 0 47078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 48495 387960 [ 48495 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 40552 2919744 [ 0 40552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 70641 565128 [ 0 30354 40287 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Request_Control: 58937 471496 [ 58937 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 47245 3401640 [ 0 47245 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 32052 256416 [ 0 32052 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 48744 389952 [ 48744 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 40396 2908512 [ 0 40396 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 70836 566688 [ 0 30232 40604 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.410354 - links_utilized_percent_switch_4_link_0: 0.172598 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.64811 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.408584 + links_utilized_percent_switch_4_link_0: 0.172466 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.644702 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Request_Control: 58702 469616 [ 58702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 46983 3382776 [ 0 46983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 32068 256544 [ 0 32068 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 48464 387712 [ 48464 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 40376 2907072 [ 0 40376 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 70314 562512 [ 0 30046 40268 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Request_Control: 58818 470544 [ 58818 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 47125 3393000 [ 0 47125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 32035 256280 [ 0 32035 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 48536 388288 [ 48536 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 40244 2897568 [ 0 40244 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 70534 564272 [ 0 30267 40267 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.406591 - links_utilized_percent_switch_5_link_0: 0.170992 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.642191 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.405162 + links_utilized_percent_switch_5_link_0: 0.17135 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.638974 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 58275 466200 [ 58275 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 46593 3354696 [ 0 46593 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 31226 249808 [ 0 31226 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 47996 383968 [ 47996 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 39989 2879208 [ 0 39989 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 69862 558896 [ 0 29968 39894 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 58457 467656 [ 58457 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 46900 3376800 [ 0 46900 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 31090 248720 [ 0 31090 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 48278 386224 [ 48278 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 39847 2868984 [ 0 39847 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 70089 560712 [ 0 30167 39922 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.403555 - links_utilized_percent_switch_6_link_0: 0.170507 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.636603 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.403843 + links_utilized_percent_switch_6_link_0: 0.170658 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.637028 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Request_Control: 57883 463064 [ 57883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 46461 3345192 [ 0 46461 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 47887 383096 [ 47887 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 39582 2849904 [ 0 39582 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 69477 555816 [ 0 29723 39754 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Request_Control: 58163 465304 [ 58163 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 46662 3359664 [ 0 46662 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 31459 251672 [ 0 31459 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 48088 384704 [ 48088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 39744 2861568 [ 0 39744 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 69753 558024 [ 0 29920 39833 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.404768 - links_utilized_percent_switch_7_link_0: 0.170843 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.638692 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.405049 + links_utilized_percent_switch_7_link_0: 0.170688 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.63941 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Request_Control: 58034 464272 [ 58034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 46530 3350160 [ 0 46530 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 31591 252728 [ 0 31591 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 48033 384264 [ 48033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 39723 2860056 [ 0 39723 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 69616 556928 [ 0 29815 39801 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Request_Control: 58279 466232 [ 58279 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 46646 3358512 [ 0 46646 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 31576 252608 [ 0 31576 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 48088 384704 [ 48088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 39937 2875464 [ 0 39937 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 69794 558352 [ 0 29976 39818 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 1.37857 - links_utilized_percent_switch_8_link_0: 0.521419 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 2.23573 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 1.37946 + links_utilized_percent_switch_8_link_0: 0.521488 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 2.23743 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 387750 3102000 [ 387750 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Data: 93552 6735744 [ 0 93552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 321925 2575400 [ 0 0 321925 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 389088 3112704 [ 389088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Data: 93896 6760512 [ 0 93896 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 322997 2583976 [ 0 0 322997 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 321925 2575400 [ 321925 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Data: 147748 10637856 [ 0 147748 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 11614 92912 [ 0 11614 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 322998 2583984 [ 322998 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Data: 148408 10685376 [ 0 148408 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 11557 92456 [ 0 11557 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.24336e-05 - links_utilized_percent_switch_9_link_0: 6.72087e-07 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.41951e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.23913e-05 + links_utilized_percent_switch_9_link_0: 6.69798e-07 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.41127e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.760712 - links_utilized_percent_switch_10_link_0: 0.701199 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.696345 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.692977 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.691155 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.690391 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.683967 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.68203 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.683371 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 2.08568 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 2.68835e-06 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.760901 + links_utilized_percent_switch_10_link_0: 0.69849 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.698852 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.693576 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.691492 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.689863 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.685401 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.682632 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.682751 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 2.08595 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 2.67919e-06 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Request_Control: 59677 477416 [ 59677 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 47767 3439224 [ 0 47767 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 32078 256624 [ 0 32078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 59368 474944 [ 59368 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 47459 3417048 [ 0 47459 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 31548 252384 [ 0 31548 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 58740 469920 [ 58740 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 47251 3402072 [ 0 47251 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 31542 252336 [ 0 31542 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 58992 471936 [ 58992 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 47078 3389616 [ 0 47078 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 31492 251936 [ 0 31492 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 58702 469616 [ 58702 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 46983 3382776 [ 0 46983 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 32068 256544 [ 0 32068 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 58275 466200 [ 58275 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 46593 3354696 [ 0 46593 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 31226 249808 [ 0 31226 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 57883 463064 [ 57883 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 46461 3345192 [ 0 46461 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 58034 464272 [ 58034 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 46530 3350160 [ 0 46530 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 31591 252728 [ 0 31591 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Control: 387750 3102000 [ 387750 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Data: 93552 6735744 [ 0 93552 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 321925 2575400 [ 0 0 321925 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Request_Control: 59687 477496 [ 59687 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 47741 3437352 [ 0 47741 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 32062 256496 [ 0 32062 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Request_Control: 59688 477504 [ 59688 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 47753 3438216 [ 0 47753 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 32223 257784 [ 0 32223 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Request_Control: 59380 475040 [ 59380 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 47445 3416040 [ 0 47445 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 31365 250920 [ 0 31365 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Request_Control: 58937 471496 [ 58937 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 47245 3401640 [ 0 47245 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 32052 256416 [ 0 32052 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Request_Control: 58818 470544 [ 58818 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 47125 3393000 [ 0 47125 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 32035 256280 [ 0 32035 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Request_Control: 58457 467656 [ 58457 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 46900 3376800 [ 0 46900 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 31090 248720 [ 0 31090 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Request_Control: 58163 465304 [ 58163 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 46662 3359664 [ 0 46662 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 31459 251672 [ 0 31459 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Request_Control: 58279 466232 [ 58279 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 46646 3358512 [ 0 46646 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 31576 252608 [ 0 31576 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Control: 389088 3112704 [ 389088 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Data: 93896 6760512 [ 0 93896 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 322997 2583976 [ 0 0 322997 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Control: 2 16 [ 2 0 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 99861 -Ifetch 0 -Store 53771 -Inv 30612 -L1_Replacement 0 -Fwd_GETX 17155 -Fwd_GETS 11910 -Fwd_GET_INSTR 0 -Data 10502 -Data_Exclusive 0 -DataS_fromL1 11846 -Data_all_Acks 25419 -Ack 20165 -Ack_all 11913 -WB_Ack 0 +Load [98791 97731 97572 97071 99913 100001 99360 98538 ] 788977 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [52644 52277 51881 52218 53591 53703 53197 53193 ] 422704 +Inv [30267 30167 29920 29976 30582 30632 30529 30232 ] 242305 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Fwd_GETX [16858 16733 16742 16669 17159 17120 16916 17012 ] 135209 +Fwd_GETS [11693 11557 11501 11634 11946 11936 11935 11692 ] 93894 +Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 +Data [10403 10206 10182 10219 10424 10432 10223 10248 ] 82337 +Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +DataS_fromL1 [11716 11632 11590 11515 11931 11884 11727 11899 ] 93894 +Data_all_Acks [25006 25062 24890 24912 25386 25437 25495 25098 ] 201286 +Ack [20223 19508 19853 19917 20145 20331 19685 20306 ] 159968 +Ack_all [11812 11582 11606 11659 11917 11892 11680 11746 ] 93894 +WB_Ack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- +NP Load [2 2 2 2 2 1 1 2 ] 14 +NP Ifetch [0 0 0 0 0 0 0 0 ] 0 +NP Store [0 0 0 0 0 1 1 0 ] 2 +NP Inv [0 0 0 0 0 0 0 0 ] 0 +NP L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -I Load 20113 -I Ifetch 0 <-- -I Store 11009 -I Inv 0 <-- -I L1_Replacement 0 <-- +I Load [19981 19985 19842 19782 20128 20157 20050 20037 ] 159962 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [10790 10667 10674 10624 10815 10861 10767 10743 ] 85941 +I Inv [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -S Load 33892 -S Ifetch 0 <-- -S Store 18056 -S Inv 11768 -S L1_Replacement 0 <-- +S Load [33647 33078 32817 32546 33727 33844 33654 33380 ] 266693 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [17763 17624 17570 17680 18291 18194 18085 17962 ] 143169 +S Inv [11809 11774 11653 11704 11690 11802 11753 11649 ] 93834 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- +E Load [0 0 0 0 0 0 0 0 ] 0 +E Ifetch [0 0 0 0 0 0 0 0 ] 0 +E Store [0 0 0 0 0 0 0 0 ] 0 +E Inv [0 0 0 0 0 0 0 0 ] 0 +E L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +E Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -M Load 45855 -M Ifetch 0 <-- -M Store 24705 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 17155 -M Fwd_GETS 11910 -M Fwd_GET_INSTR 0 <-- +M Load [45161 44666 44911 44741 46056 45999 45655 45119 ] 362308 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [24091 23986 23637 23914 24485 24647 24344 24488 ] 193592 +M Inv [0 0 0 0 0 0 0 0 ] 0 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Fwd_GETX [16858 16733 16742 16669 17159 17120 16916 17012 ] 135209 +M Fwd_GETS [11693 11557 11501 11634 11946 11936 11935 11692 ] 93894 +M Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2199 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11846 -IS Data_all_Acks 6068 +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS Inv [2104 2145 2121 2033 2094 2096 2148 2119 ] 16860 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +IS DataS_fromL1 [11716 11632 11590 11515 11931 11884 11727 11899 ] 93894 +IS Data_all_Acks [6163 6209 6132 6235 6104 6177 6176 6020 ] 49216 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10502 -IM Data_all_Acks 17152 -IM Ack 0 <-- +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM Inv [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Data [10403 10206 10182 10219 10424 10432 10223 10248 ] 82337 +IM Data_all_Acks [16739 16708 16637 16644 17188 17164 17171 16959 ] 135210 +IM Ack [0 0 0 0 0 0 0 0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16645 -SM L1_Replacement 0 <-- -SM Ack 20165 -SM Ack_all 11913 +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM Inv [16354 16248 16146 16239 16798 16734 16628 16464 ] 131611 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Ack [20223 19508 19853 19917 20145 20331 19685 20306 ] 159968 +SM Ack_all [11812 11582 11606 11659 11917 11892 11680 11746 ] 93894 -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2199 +IS_I Load [0 0 0 0 0 0 0 0 ] 0 +IS_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS_I Store [0 0 0 0 0 0 0 0 ] 0 +IS_I Inv [0 0 0 0 0 0 0 0 ] 0 +IS_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS_I Data_Exclusive [0 0 0 0 0 0 0 0 ] 0 +IS_I DataS_fromL1 [0 0 0 0 0 0 0 0 ] 0 +IS_I Data_all_Acks [2104 2145 2121 2033 2094 2096 2148 2119 ] 16860 -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- +M_I Load [0 0 0 0 0 0 0 0 ] 0 +M_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_I Store [0 0 0 0 0 0 0 0 ] 0 +M_I Inv [0 0 0 0 0 0 0 0 ] 0 +M_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +M_I Fwd_GET_INSTR [0 0 0 0 0 0 0 0 ] 0 +M_I WB_Ack [0 0 0 0 0 0 0 0 ] 0 -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- +E_I Load [0 0 0 0 0 0 0 0 ] 0 +E_I Ifetch [0 0 0 0 0 0 0 0 ] 0 +E_I Store [0 0 0 0 0 0 0 0 ] 0 +E_I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.icache + system.l1_cntrl1.sequencer.icache_total_misses: 0 + system.l1_cntrl1.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.icache_total_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.dcache + system.l1_cntrl1.sequencer.dcache_total_misses: 0 + system.l1_cntrl1.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 1 --- +Cache Stats: system.l1_cntrl2.sequencer.icache + system.l1_cntrl2.sequencer.icache_total_misses: 0 + system.l1_cntrl2.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.icache_total_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.sequencer.dcache + system.l1_cntrl2.sequencer.dcache_total_misses: 0 + system.l1_cntrl2.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.sequencer.icache + system.l1_cntrl3.sequencer.icache_total_misses: 0 + system.l1_cntrl3.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.icache_total_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.sequencer.dcache + system.l1_cntrl3.sequencer.dcache_total_misses: 0 + system.l1_cntrl3.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.sequencer.icache + system.l1_cntrl4.sequencer.icache_total_misses: 0 + system.l1_cntrl4.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.icache_total_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.sequencer.dcache + system.l1_cntrl4.sequencer.dcache_total_misses: 0 + system.l1_cntrl4.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.sequencer.icache + system.l1_cntrl5.sequencer.icache_total_misses: 0 + system.l1_cntrl5.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.icache_total_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.sequencer.dcache + system.l1_cntrl5.sequencer.dcache_total_misses: 0 + system.l1_cntrl5.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.sequencer.icache + system.l1_cntrl6.sequencer.icache_total_misses: 0 + system.l1_cntrl6.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.icache_total_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.sequencer.dcache + system.l1_cntrl6.sequencer.dcache_total_misses: 0 + system.l1_cntrl6.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.sequencer.icache + system.l1_cntrl7.sequencer.icache_total_misses: 0 + system.l1_cntrl7.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.icache_total_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.sequencer.dcache + system.l1_cntrl7.sequencer.dcache_total_misses: 0 + system.l1_cntrl7.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -Load 100000 -Ifetch 0 -Store 53094 -Inv 30597 -L1_Replacement 0 -Fwd_GETX 16861 -Fwd_GETS 11910 -Fwd_GET_INSTR 0 -Data 10170 -Data_Exclusive 0 -DataS_fromL1 11904 -Data_all_Acks 25385 -Ack 19858 -Ack_all 11690 -WB_Ack 0 +L1_GET_INSTR [0 ] 0 +L1_GETS [2029820 ] 2029820 +L1_GETX [2559777 ] 2559777 +L1_UPGRADE [315940 ] 315940 +L1_PUTX [0 ] 0 +L1_PUTX_old [0 ] 0 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [0 ] 0 +L2_Replacement_clean [0 ] 0 +Mem_Data [2 ] 2 +Mem_Ack [0 ] 0 +WB_Data [93894 ] 93894 +WB_Data_clean [0 ] 0 +Ack [0 ] 0 +Ack_all [0 ] 0 +Unblock [93893 ] 93893 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [229104 ] 229104 +MEM_Inv [0 ] 0 - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Inv 0 <-- -NP L1_Replacement 0 <-- +NP L1_GET_INSTR [0 ] 0 +NP L1_GETS [1 ] 1 +NP L1_GETX [1 ] 1 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [0 ] 0 -I Load 20208 -I Ifetch 0 <-- -I Store 10728 -I Inv 0 <-- -I L1_Replacement 0 <-- +SS L1_GET_INSTR [0 ] 0 +SS L1_GETS [66069 ] 66069 +SS L1_GETX [82337 ] 82337 +SS L1_UPGRADE [11557 ] 11557 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [0 ] 0 +SS MEM_Inv [0 ] 0 -S Load 34188 -S Ifetch 0 <-- -S Store 18042 -S Inv 11866 -S L1_Replacement 0 <-- +M L1_GET_INSTR [0 ] 0 +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [0 ] 0 +M L2_Replacement_clean [0 ] 0 +M MEM_Inv [0 ] 0 -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [93895 ] 93895 +MT L1_GETX [135209 ] 135209 +MT L1_PUTX [0 ] 0 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L2_Replacement_clean [0 ] 0 +MT MEM_Inv [0 ] 0 -M Load 45604 -M Ifetch 0 <-- -M Store 24322 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16861 -M Fwd_GETS 11910 -M Fwd_GET_INSTR 0 <-- +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [0 ] 0 +M_I Mem_Ack [0 ] 0 +M_I MEM_Inv [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2209 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11904 -IS Data_all_Acks 6095 +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [0 ] 0 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [0 ] 0 +MT_I MEM_Inv [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10170 -IM Data_all_Acks 17081 -IM Ack 0 <-- +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [0 ] 0 +MCT_I WB_Data [0 ] 0 +MCT_I WB_Data_clean [0 ] 0 +MCT_I Ack_all [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16522 -SM L1_Replacement 0 <-- -SM Ack 19858 -SM Ack_all 11690 +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [0 ] 0 -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2209 +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [1 ] 1 +ISS L1_GETX [1 ] 1 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [0 ] 0 +ISS Mem_Data [0 ] 0 +ISS MEM_Inv [0 ] 0 -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [5 ] 5 +IS L1_GETX [24 ] 24 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [0 ] 0 +IS Mem_Data [1 ] 1 +IS MEM_Inv [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [252 ] 252 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [0 ] 0 +IM Mem_Data [1 ] 1 +IM MEM_Inv [0 ] 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [471486 ] 471486 +SS_MB L1_GETX [567420 ] 567420 +SS_MB L1_UPGRADE [263790 ] 263790 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [93894 ] 93894 +SS_MB MEM_Inv [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [857401 ] 857401 +MT_MB L1_GETX [1067485 ] 1067485 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [0 ] 0 +MT_MB L1_PUTX_old [0 ] 0 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [0 ] 0 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [135210 ] 135210 +MT_MB MEM_Inv [0 ] 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 - --- L1Cache 2 --- - - Event Counts - -Load 98032 -Ifetch 0 -Store 52759 -Inv 30181 -L1_Replacement 0 -Fwd_GETX 17070 -Fwd_GETS 11489 -Fwd_GET_INSTR 0 -Data 10282 -Data_Exclusive 0 -DataS_fromL1 11777 -Data_all_Acks 25192 -Ack 19798 -Ack_all 11744 -WB_Ack 0 +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [386073 ] 386073 +MT_IIB L1_GETX [501723 ] 501723 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [93894 ] 93894 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 -I Load 20153 -I Ifetch 0 <-- -I Store 10822 -I Inv 0 <-- -I L1_Replacement 0 <-- +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [154637 ] 154637 +MT_SB L1_GETX [205577 ] 205577 +MT_SB L1_UPGRADE [40593 ] 40593 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [93893 ] 93893 +MT_SB MEM_Inv [0 ] 0 -S Load 32864 -S Ifetch 0 <-- -S Store 17738 -S Inv 11696 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45014 -M Ifetch 0 <-- -M Store 24198 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 17070 -M Fwd_GETS 11489 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2209 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11777 -IS Data_all_Acks 6168 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10282 -IM Data_all_Acks 16815 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16276 -SM L1_Replacement 0 <-- -SM Ack 19798 -SM Ack_all 11744 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2209 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 3 --- - - Event Counts - -Load 98574 -Ifetch 0 -Store 52923 -Inv 30354 -L1_Replacement 0 -Fwd_GETX 16724 -Fwd_GETS 11914 -Fwd_GET_INSTR 0 -Data 10232 -Data_Exclusive 0 -DataS_fromL1 11649 -Data_all_Acks 25197 -Ack 19845 -Ack_all 11647 -WB_Ack 0 - - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19854 -I Ifetch 0 <-- -I Store 10574 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33422 -S Ifetch 0 <-- -S Store 18065 -S Inv 11545 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45296 -M Ifetch 0 <-- -M Store 24284 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16724 -M Fwd_GETS 11914 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2159 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11649 -IS Data_all_Acks 6047 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10232 -IM Data_all_Acks 16991 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16650 -SM L1_Replacement 0 <-- -SM Ack 19845 -SM Ack_all 11647 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2159 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 4 --- - - Event Counts - -Load 97813 -Ifetch 0 -Store 53065 -Inv 30046 -L1_Replacement 0 -Fwd_GETX 16936 -Fwd_GETS 11720 -Fwd_GET_INSTR 0 -Data 10345 -Data_Exclusive 0 -DataS_fromL1 11611 -Data_all_Acks 25027 -Ack 20243 -Ack_all 11825 -WB_Ack 0 - - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19807 -I Ifetch 0 <-- -I Store 10748 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 32839 -S Ifetch 0 <-- -S Store 17907 -S Inv 11513 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 45167 -M Ifetch 0 <-- -M Store 24408 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16936 -M Fwd_GETS 11720 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2106 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11611 -IS Data_all_Acks 6089 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10345 -IM Data_all_Acks 16832 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16427 -SM L1_Replacement 0 <-- -SM Ack 20243 -SM Ack_all 11825 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2106 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 97539 -Ifetch 0 -Store 52365 -Inv 29968 -L1_Replacement 0 -Fwd_GETX 16625 -Fwd_GETS 11682 -Fwd_GET_INSTR 0 -Data 10163 -Data_Exclusive 0 -DataS_fromL1 11587 -Data_all_Acks 24843 -Ack 19662 -Ack_all 11564 -WB_Ack 0 - - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19687 -I Ifetch 0 <-- -I Store 10596 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33227 -S Ifetch 0 <-- -S Store 17711 -S Inv 11590 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44624 -M Ifetch 0 <-- -M Store 24057 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16625 -M Fwd_GETS 11682 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2068 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11587 -IS Data_all_Acks 6032 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10163 -IM Data_all_Acks 16743 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16310 -SM L1_Replacement 0 <-- -SM Ack 19662 -SM Ack_all 11564 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2068 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 96539 -Ifetch 0 -Store 52066 -Inv 29723 -L1_Replacement 0 -Fwd_GETX 16738 -Fwd_GETS 11422 -Fwd_GET_INSTR 0 -Data 10102 -Data_Exclusive 0 -DataS_fromL1 11594 -Data_all_Acks 24765 -Ack 19839 -Ack_all 11526 -WB_Ack 0 - - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19723 -I Ifetch 0 <-- -I Store 10567 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 32252 -S Ifetch 0 <-- -S Store 17595 -S Inv 11486 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44562 -M Ifetch 0 <-- -M Store 23904 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16738 -M Fwd_GETS 11422 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 2066 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11594 -IS Data_all_Acks 6065 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10102 -IM Data_all_Acks 16634 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16171 -SM L1_Replacement 0 <-- -SM Ack 19839 -SM Ack_all 11526 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 2066 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 97318 -Ifetch 0 -Store 52277 -Inv 29815 -L1_Replacement 0 -Fwd_GETX 16715 -Fwd_GETS 11504 -Fwd_GET_INSTR 0 -Data 10140 -Data_Exclusive 0 -DataS_fromL1 11582 -Data_all_Acks 24808 -Ack 19950 -Ack_all 11641 -WB_Ack 0 - - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Inv 0 <-- -NP L1_Replacement 0 <-- - -I Load 19811 -I Ifetch 0 <-- -I Store 10672 -I Inv 0 <-- -I L1_Replacement 0 <-- - -S Load 33045 -S Ifetch 0 <-- -S Store 17548 -S Inv 11790 -S L1_Replacement 0 <-- - -E Load 0 <-- -E Ifetch 0 <-- -E Store 0 <-- -E Inv 0 <-- -E L1_Replacement 0 <-- -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- - -M Load 44461 -M Ifetch 0 <-- -M Store 24056 -M Inv 0 <-- -M L1_Replacement 0 <-- -M Fwd_GETX 16715 -M Fwd_GETS 11504 -M Fwd_GET_INSTR 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 1978 -IS L1_Replacement 0 <-- -IS Data_Exclusive 0 <-- -IS DataS_fromL1 11582 -IS Data_all_Acks 6252 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 0 <-- -IM Data 10140 -IM Data_all_Acks 16578 -IM Ack 0 <-- - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 16047 -SM L1_Replacement 0 <-- -SM Ack 19950 -SM Ack_all 11641 - -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 1978 - -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 0 <-- -M_I Inv 0 <-- -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 0 <-- - -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- - - Event Counts - -L1_GET_INSTR 0 -L1_GETS 2024573 -L1_GETX 2549715 -L1_UPGRADE 314708 -L1_PUTX 0 -L1_PUTX_old 0 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 0 -L2_Replacement_clean 0 -Mem_Data 2 -Mem_Ack 0 -WB_Data 93550 -WB_Data_clean 0 -Ack 0 -Ack_all 0 -Unblock 93550 -Unblock_Cancel 0 -Exclusive_Unblock 228375 -MEM_Inv 0 - - - Transitions - -NP L1_GET_INSTR 0 <-- -NP L1_GETS 0 <-- -NP L1_GETX 2 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 0 <-- - -SS L1_GET_INSTR 0 <-- -SS L1_GETS 65810 -SS L1_GETX 81936 -SS L1_UPGRADE 11614 -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 0 <-- -SS MEM_Inv 0 <-- - -M L1_GET_INSTR 0 <-- -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 0 <-- -M L2_Replacement_clean 0 <-- -M MEM_Inv 0 <-- - -MT L1_GET_INSTR 0 <-- -MT L1_GETS 93551 -MT L1_GETX 134824 -MT L1_PUTX 0 <-- -MT L1_PUTX_old 0 <-- -MT L2_Replacement 0 <-- -MT L2_Replacement_clean 0 <-- -MT MEM_Inv 0 <-- - -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 0 <-- -M_I L1_GETX 0 <-- -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 0 <-- -M_I Mem_Ack 0 <-- -M_I MEM_Inv 0 <-- - -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 0 <-- -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 0 <-- -MT_I MEM_Inv 0 <-- - -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 0 <-- -MCT_I WB_Data 0 <-- -MCT_I WB_Data_clean 0 <-- -MCT_I Ack_all 0 <-- - -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 0 <-- - -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- - -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 0 <-- -ISS Mem_Data 0 <-- -ISS MEM_Inv 0 <-- - -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 0 <-- -IS MEM_Inv 0 <-- - -IM L1_GET_INSTR 0 <-- -IM L1_GETS 244 -IM L1_GETX 183 -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 0 <-- -IM Mem_Data 2 -IM MEM_Inv 0 <-- - -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 470476 -SS_MB L1_GETX 564705 -SS_MB L1_UPGRADE 262728 -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 93549 -SS_MB MEM_Inv 0 <-- - -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 855369 -MT_MB L1_GETX 1063853 -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 0 <-- -MT_MB L1_PUTX_old 0 <-- -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 0 <-- -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 134826 -MT_MB MEM_Inv 0 <-- - -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- - -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 384672 -MT_IIB L1_GETX 499786 -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 93550 -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- - -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- - -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 154451 -MT_SB L1_GETX 204426 -MT_SB L1_UPGRADE 40366 -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 93550 -MT_SB MEM_Inv 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -1507,67 +774,66 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 2 -Data 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 0 +Fetch [2 ] 2 +Data [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [0 ] 0 - Transitions - -I Fetch 2 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I Fetch [2 ] 2 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 -M Data 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 0 <-- +M Data [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [0 ] 0 -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 2 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [2 ] 2 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu7: completed 10000 read accesses @373359 -system.cpu1: completed 10000 read accesses @375374 -system.cpu0: completed 10000 read accesses @376725 -system.cpu2: completed 10000 read accesses @380778 -system.cpu5: completed 10000 read accesses @382682 -system.cpu3: completed 10000 read accesses @383505 -system.cpu4: completed 10000 read accesses @386561 -system.cpu6: completed 10000 read accesses @389125 -system.cpu1: completed 20000 read accesses @745885 -system.cpu0: completed 20000 read accesses @748353 -system.cpu2: completed 20000 read accesses @753861 -system.cpu7: completed 20000 read accesses @758042 -system.cpu5: completed 20000 read accesses @759129 -system.cpu3: completed 20000 read accesses @764814 -system.cpu4: completed 20000 read accesses @768939 -system.cpu6: completed 20000 read accesses @774936 -system.cpu1: completed 30000 read accesses @1121924 -system.cpu2: completed 30000 read accesses @1124427 -system.cpu0: completed 30000 read accesses @1125253 -system.cpu7: completed 30000 read accesses @1139134 -system.cpu4: completed 30000 read accesses @1139334 -system.cpu3: completed 30000 read accesses @1144574 -system.cpu5: completed 30000 read accesses @1145748 -system.cpu6: completed 30000 read accesses @1147208 -system.cpu0: completed 40000 read accesses @1492239 -system.cpu1: completed 40000 read accesses @1495604 -system.cpu2: completed 40000 read accesses @1499940 -system.cpu4: completed 40000 read accesses @1518641 -system.cpu7: completed 40000 read accesses @1518771 -system.cpu5: completed 40000 read accesses @1528667 -system.cpu6: completed 40000 read accesses @1530209 -system.cpu3: completed 40000 read accesses @1537371 -system.cpu0: completed 50000 read accesses @1865558 -system.cpu1: completed 50000 read accesses @1868280 -system.cpu2: completed 50000 read accesses @1884528 -system.cpu7: completed 50000 read accesses @1899621 -system.cpu4: completed 50000 read accesses @1903698 -system.cpu5: completed 50000 read accesses @1909143 -system.cpu3: completed 50000 read accesses @1910503 -system.cpu6: completed 50000 read accesses @1915590 -system.cpu0: completed 60000 read accesses @2235441 -system.cpu1: completed 60000 read accesses @2240292 -system.cpu2: completed 60000 read accesses @2270206 -system.cpu4: completed 60000 read accesses @2278819 -system.cpu7: completed 60000 read accesses @2284397 -system.cpu5: completed 60000 read accesses @2288761 -system.cpu3: completed 60000 read accesses @2289377 -system.cpu6: completed 60000 read accesses @2312599 -system.cpu0: completed 70000 read accesses @2605926 -system.cpu1: completed 70000 read accesses @2606409 -system.cpu4: completed 70000 read accesses @2648937 -system.cpu2: completed 70000 read accesses @2655948 -system.cpu5: completed 70000 read accesses @2662046 -system.cpu3: completed 70000 read accesses @2664803 -system.cpu7: completed 70000 read accesses @2675843 -system.cpu6: completed 70000 read accesses @2704307 -system.cpu1: completed 80000 read accesses @2972591 -system.cpu0: completed 80000 read accesses @2986258 -system.cpu3: completed 80000 read accesses @3027695 -system.cpu4: completed 80000 read accesses @3034526 -system.cpu2: completed 80000 read accesses @3036101 -system.cpu5: completed 80000 read accesses @3049670 -system.cpu7: completed 80000 read accesses @3053840 -system.cpu6: completed 80000 read accesses @3088364 -system.cpu1: completed 90000 read accesses @3348204 -system.cpu0: completed 90000 read accesses @3355393 -system.cpu3: completed 90000 read accesses @3393344 -system.cpu2: completed 90000 read accesses @3410223 -system.cpu4: completed 90000 read accesses @3417605 -system.cpu5: completed 90000 read accesses @3432894 -system.cpu7: completed 90000 read accesses @3437480 -system.cpu6: completed 90000 read accesses @3470461 -system.cpu1: completed 100000 read accesses @3719757 +system.cpu4: completed 10000 read accesses @371319 +system.cpu0: completed 10000 read accesses @374132 +system.cpu3: completed 10000 read accesses @376921 +system.cpu5: completed 10000 read accesses @377717 +system.cpu1: completed 10000 read accesses @378458 +system.cpu2: completed 10000 read accesses @380499 +system.cpu7: completed 10000 read accesses @384625 +system.cpu6: completed 10000 read accesses @392714 +system.cpu0: completed 20000 read accesses @746882 +system.cpu1: completed 20000 read accesses @747768 +system.cpu3: completed 20000 read accesses @751201 +system.cpu4: completed 20000 read accesses @754052 +system.cpu2: completed 20000 read accesses @756891 +system.cpu5: completed 20000 read accesses @758829 +system.cpu7: completed 20000 read accesses @771937 +system.cpu6: completed 20000 read accesses @782300 +system.cpu0: completed 30000 read accesses @1118226 +system.cpu1: completed 30000 read accesses @1123177 +system.cpu4: completed 30000 read accesses @1126209 +system.cpu2: completed 30000 read accesses @1126605 +system.cpu3: completed 30000 read accesses @1136317 +system.cpu5: completed 30000 read accesses @1150478 +system.cpu7: completed 30000 read accesses @1157056 +system.cpu6: completed 30000 read accesses @1158703 +system.cpu1: completed 40000 read accesses @1490911 +system.cpu0: completed 40000 read accesses @1491884 +system.cpu4: completed 40000 read accesses @1499728 +system.cpu2: completed 40000 read accesses @1507155 +system.cpu3: completed 40000 read accesses @1510905 +system.cpu5: completed 40000 read accesses @1531762 +system.cpu6: completed 40000 read accesses @1537542 +system.cpu7: completed 40000 read accesses @1548913 +system.cpu1: completed 50000 read accesses @1863344 +system.cpu0: completed 50000 read accesses @1867390 +system.cpu4: completed 50000 read accesses @1875943 +system.cpu2: completed 50000 read accesses @1880519 +system.cpu3: completed 50000 read accesses @1894164 +system.cpu5: completed 50000 read accesses @1907344 +system.cpu6: completed 50000 read accesses @1912470 +system.cpu7: completed 50000 read accesses @1934832 +system.cpu0: completed 60000 read accesses @2235164 +system.cpu1: completed 60000 read accesses @2235372 +system.cpu2: completed 60000 read accesses @2255489 +system.cpu4: completed 60000 read accesses @2255789 +system.cpu3: completed 60000 read accesses @2285501 +system.cpu6: completed 60000 read accesses @2287062 +system.cpu5: completed 60000 read accesses @2288078 +system.cpu7: completed 60000 read accesses @2318455 +system.cpu0: completed 70000 read accesses @2608054 +system.cpu1: completed 70000 read accesses @2612960 +system.cpu2: completed 70000 read accesses @2625598 +system.cpu4: completed 70000 read accesses @2647034 +system.cpu3: completed 70000 read accesses @2656375 +system.cpu6: completed 70000 read accesses @2669788 +system.cpu5: completed 70000 read accesses @2674918 +system.cpu7: completed 70000 read accesses @2701597 +system.cpu0: completed 80000 read accesses @2969057 +system.cpu1: completed 80000 read accesses @2983204 +system.cpu2: completed 80000 read accesses @3009749 +system.cpu4: completed 80000 read accesses @3025995 +system.cpu3: completed 80000 read accesses @3035695 +system.cpu5: completed 80000 read accesses @3050099 +system.cpu6: completed 80000 read accesses @3059863 +system.cpu7: completed 80000 read accesses @3076434 +system.cpu0: completed 90000 read accesses @3351979 +system.cpu1: completed 90000 read accesses @3359824 +system.cpu2: completed 90000 read accesses @3385786 +system.cpu4: completed 90000 read accesses @3406557 +system.cpu3: completed 90000 read accesses @3413289 +system.cpu5: completed 90000 read accesses @3435121 +system.cpu6: completed 90000 read accesses @3437923 +system.cpu7: completed 90000 read accesses @3458885 +system.cpu1: completed 100000 read accesses @3732466 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:36:48 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:36:46 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:32:07 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3719757 because maximum number of loads reached +Exiting @ tick 3732466 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340040 # Number of bytes of host memory used -host_seconds 42.78 # Real time elapsed on the host -host_tick_rate 86943 # Simulator tick rate (ticks/s) +host_mem_usage 342208 # Number of bytes of host memory used +host_seconds 44.56 # Real time elapsed on the host +host_tick_rate 83759 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003720 # Number of seconds simulated -sim_ticks 3719757 # Number of ticks simulated +sim_seconds 0.003732 # Number of seconds simulated +sim_ticks 3732466 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99860 # number of read accesses completed -system.cpu0.num_writes 53770 # number of write accesses completed +system.cpu0.num_reads 99912 # number of read accesses completed +system.cpu0.num_writes 53590 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53093 # number of write accesses completed +system.cpu1.num_writes 53703 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98032 # number of read accesses completed -system.cpu2.num_writes 52757 # number of write accesses completed +system.cpu2.num_reads 99360 # number of read accesses completed +system.cpu2.num_writes 53195 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98573 # number of read accesses completed -system.cpu3.num_writes 52922 # number of write accesses completed +system.cpu3.num_reads 98537 # number of read accesses completed +system.cpu3.num_writes 53193 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 97812 # number of read accesses completed -system.cpu4.num_writes 53065 # number of write accesses completed +system.cpu4.num_reads 98791 # number of read accesses completed +system.cpu4.num_writes 52642 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 97538 # number of read accesses completed -system.cpu5.num_writes 52364 # number of write accesses completed +system.cpu5.num_reads 97730 # number of read accesses completed +system.cpu5.num_writes 52276 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 96539 # number of read accesses completed -system.cpu6.num_writes 52064 # number of write accesses completed +system.cpu6.num_reads 97571 # number of read accesses completed +system.cpu6.num_writes 51880 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97318 # number of read accesses completed -system.cpu7.num_writes 52275 # number of write accesses completed +system.cpu7.num_reads 97070 # number of read accesses completed +system.cpu7.num_writes 52217 # number of write accesses completed ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,14 @@ [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.l1_cntrl0.sequencer.port[0] [system.cpu1] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.l1_cntrl1.sequencer.port[0] [system.cpu2] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.l1_cntrl2.sequencer.port[0] [system.cpu3] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.l1_cntrl3.sequencer.port[0] [system.cpu4] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.l1_cntrl4.sequencer.port[0] [system.cpu5] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.l1_cntrl5.sequencer.port[0] [system.cpu6] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.l1_cntrl6.sequencer.port[0] [system.cpu7] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,48 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.l1_cntrl7.sequencer.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 [system.funcmem] type=PhysicalMemory @@ -139,6 +188,370 @@ zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl1.sequencer.dcache +L1IcacheMemory=system.l1_cntrl1.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl1.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl1.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.l1_cntrl1.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl2.sequencer.dcache +L1IcacheMemory=system.l1_cntrl2.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl2.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl2.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.l1_cntrl2.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl3.sequencer.dcache +L1IcacheMemory=system.l1_cntrl3.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl3.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl3.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.l1_cntrl3.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl4.sequencer.dcache +L1IcacheMemory=system.l1_cntrl4.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl4.sequencer +transitions_per_cycle=32 +version=4 + +[system.l1_cntrl4.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl4.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl4.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.l1_cntrl4.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl5.sequencer.dcache +L1IcacheMemory=system.l1_cntrl5.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl5.sequencer +transitions_per_cycle=32 +version=5 + +[system.l1_cntrl5.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl5.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl5.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.l1_cntrl5.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl6.sequencer.dcache +L1IcacheMemory=system.l1_cntrl6.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl6.sequencer +transitions_per_cycle=32 +version=6 + +[system.l1_cntrl6.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl6.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl6.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.l1_cntrl6.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl7.sequencer.dcache +L1IcacheMemory=system.l1_cntrl7.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl7.sequencer +transitions_per_cycle=32 +version=7 + +[system.l1_cntrl7.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl7.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl7.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.l1_cntrl7.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -147,7 +560,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort [system.ruby] type=RubySystem @@ -188,487 +601,90 @@ children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +name=Crossbar num_int_nodes=11 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l1_cntrl1 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer -transitions_per_cycle=32 -version=1 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.l1_cntrl2 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer -transitions_per_cycle=32 -version=2 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links3] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node +ext_node=system.l1_cntrl3 int_node=3 latency=1 weight=1 -[system.ruby.network.topology.ext_links3.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer -transitions_per_cycle=32 -version=3 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links4] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node +ext_node=system.l1_cntrl4 int_node=4 latency=1 weight=1 -[system.ruby.network.topology.ext_links4.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer -transitions_per_cycle=32 -version=4 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links5] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node +ext_node=system.l1_cntrl5 int_node=5 latency=1 weight=1 -[system.ruby.network.topology.ext_links5.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer -transitions_per_cycle=32 -version=5 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links6] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node +ext_node=system.l1_cntrl6 int_node=6 latency=1 weight=1 -[system.ruby.network.topology.ext_links6.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer -transitions_per_cycle=32 -version=6 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links7] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node +ext_node=system.l1_cntrl7 int_node=7 latency=1 weight=1 -[system.ruby.network.topology.ext_links7.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer -transitions_per_cycle=32 -version=7 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links8] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node +ext_node=system.l2_cntrl0 int_node=8 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links9] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node +ext_node=system.dir_cntrl0 int_node=9 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:38:52 +Real time: Aug/05/2010 10:39:22 Profiler Stats -------------- -Elapsed_time_in_seconds: 30 -Elapsed_time_in_minutes: 0.5 -Elapsed_time_in_hours: 0.00833333 -Elapsed_time_in_days: 0.000347222 +Elapsed_time_in_seconds: 32 +Elapsed_time_in_minutes: 0.533333 +Elapsed_time_in_hours: 0.00888889 +Elapsed_time_in_days: 0.00037037 -Virtual_time_in_seconds: 30.63 -Virtual_time_in_minutes: 0.5105 -Virtual_time_in_hours: 0.00850833 -Virtual_time_in_days: 0.000354514 +Virtual_time_in_seconds: 29.8 +Virtual_time_in_minutes: 0.496667 +Virtual_time_in_hours: 0.00827778 +Virtual_time_in_days: 0.000344907 -Ruby_current_time: 3383480 +Ruby_current_time: 3378223 Ruby_start_time: 0 -Ruby_cycles: 3383480 +Ruby_cycles: 3378223 -mbytes_resident: 31.1758 -mbytes_total: 332.199 -resident_ratio: 0.0938584 +mbytes_resident: 32.7617 +mbytes_total: 32.7656 +resident_ratio: 1 -ruby_cycles_executed: [ 3383481 3383481 3383481 3383481 3383481 3383481 3383481 3383481 ] +ruby_cycles_executed: [ 3378224 3378224 3378224 3378224 3378224 3378224 3378224 3378224 ] Busy Controller Counts: L2Cache-0:0 @@ -67,13 +67,26 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1224321 average: 1.94443 | standard deviation: 0.229099 | 0 68041 1156280 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1222043 average: 1.94347 | standard deviation: 0.230951 | 0 69087 1152956 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 3867 count: 1224307 average: 42.2125 | standard deviation: 176.83 | 1120193 100 18422 250 3697 208 20055 99 4698 333 9493 182 6212 231 4498 196 5380 146 3026 431 3578 201 1712 1300 2300 299 1246 1179 1311 691 911 859 562 1056 709 654 462 707 409 573 330 526 208 545 261 415 162 365 175 313 146 267 103 218 103 205 80 151 93 135 60 94 55 71 59 59 41 45 41 43 25 43 16 31 21 32 21 10 15 14 10 15 8 8 10 11 3 5 9 6 6 4 4 6 2 6 2 1 4 2 3 3 0 4 0 0 3 1 0 0 0 1 0 0 0 0 3 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 3867 count: 795461 average: 41.7693 | standard deviation: 175.853 | 728451 2 12003 191 2273 112 13052 34 3039 166 6174 100 3966 173 2859 112 3400 77 2124 112 2321 116 1129 856 1452 179 824 756 1029 226 579 535 370 687 463 438 297 467 315 303 212 351 132 368 156 264 104 243 137 191 94 174 61 126 56 132 56 96 69 83 39 57 32 46 30 39 31 29 27 22 22 23 12 25 9 21 12 7 10 7 7 11 7 7 5 7 3 3 9 6 1 1 1 4 1 5 0 0 2 1 2 2 0 3 0 0 1 1 0 0 0 1 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 32 max: 3728 count: 428846 average: 43.0346 | standard deviation: 178.625 | 391742 98 6419 59 1424 96 7003 65 1659 167 3319 82 2246 58 1639 84 1980 69 902 319 1257 85 583 444 848 120 422 423 282 465 332 324 192 369 246 216 165 240 94 270 118 175 76 177 105 151 58 122 38 122 52 93 42 92 47 73 24 55 24 52 21 37 23 25 29 20 10 16 14 21 3 20 4 6 12 11 9 3 5 7 3 4 1 1 5 4 0 2 0 0 5 3 3 2 1 1 2 1 2 1 1 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 32 max: 4888 count: 1222028 average: 42.2254 | standard deviation: 176.829 | 1118074 86 18632 241 3716 204 19830 91 4757 357 9527 157 6071 243 4428 211 5350 127 2900 436 3710 172 1685 1272 2259 339 1244 1165 1282 703 940 889 557 1010 743 604 474 701 491 570 334 539 236 502 282 401 197 392 193 301 125 268 99 255 121 191 69 159 96 127 40 102 42 91 48 65 38 37 38 47 21 36 26 30 19 22 21 19 21 16 7 16 6 9 2 5 9 5 9 10 1 4 2 4 2 2 2 2 1 1 2 0 0 3 2 0 2 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 32 max: 3997 count: 793661 average: 41.7359 | standard deviation: 175.901 | 726878 4 12184 181 2270 97 12851 40 3037 168 6119 72 3949 180 2796 110 3448 63 2063 90 2368 104 1074 824 1469 200 805 736 1014 247 600 572 367 653 458 404 307 468 381 297 213 353 161 325 173 261 118 248 134 161 84 174 66 173 73 130 46 96 75 76 24 64 26 71 26 39 28 24 28 26 10 23 16 18 10 14 11 15 13 10 3 12 2 8 0 2 5 4 7 7 0 4 1 2 2 2 2 2 1 0 0 0 0 2 2 0 2 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 32 max: 4888 count: 428367 average: 43.1323 | standard deviation: 178.531 | 391196 82 6448 60 1446 107 6979 51 1720 189 3408 85 2122 63 1632 101 1902 64 837 346 1342 68 611 448 790 139 439 429 268 456 340 317 190 357 285 200 167 233 110 273 121 186 75 177 109 140 79 144 59 140 41 94 33 82 48 61 23 63 21 51 16 38 16 20 22 26 10 13 10 21 11 13 10 12 9 8 10 4 8 6 4 4 4 1 2 3 4 1 2 3 1 0 1 2 0 0 0 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 32 max: 4888 count: 1222028 average: 42.2254 | standard deviation: 176.829 | 1118074 86 18632 241 3716 204 19830 91 4757 357 9527 157 6071 243 4428 211 5350 127 2900 436 3710 172 1685 1272 2259 339 1244 1165 1282 703 940 889 557 1010 743 604 474 701 491 570 334 539 236 502 282 401 197 392 193 301 125 268 99 255 121 191 69 159 96 127 40 102 42 91 48 65 38 37 38 47 21 36 26 30 19 22 21 19 21 16 7 16 6 9 2 5 9 5 9 10 1 4 2 4 2 2 2 2 1 1 2 0 0 3 2 0 2 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_LD_NULL: [binsize: 32 max: 3997 count: 793661 average: 41.7359 | standard deviation: 175.901 | 726878 4 12184 181 2270 97 12851 40 3037 168 6119 72 3949 180 2796 110 3448 63 2063 90 2368 104 1074 824 1469 200 805 736 1014 247 600 572 367 653 458 404 307 468 381 297 213 353 161 325 173 261 118 248 134 161 84 174 66 173 73 130 46 96 75 76 24 64 26 71 26 39 28 24 28 26 10 23 16 18 10 14 11 15 13 10 3 12 2 8 0 2 5 4 7 7 0 4 1 2 2 2 2 2 1 0 0 0 0 2 2 0 2 0 1 0 0 0 1 0 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 32 max: 4888 count: 428367 average: 43.1323 | standard deviation: 178.531 | 391196 82 6448 60 1446 107 6979 51 1720 189 3408 85 2122 63 1632 101 1902 64 837 346 1342 68 611 448 790 139 439 429 268 456 340 317 190 357 285 200 167 233 110 273 121 186 75 177 109 140 79 144 59 140 41 94 33 82 48 61 23 63 21 51 16 38 16 20 22 26 10 13 10 21 11 13 10 12 9 8 10 4 8 6 4 4 4 1 2 3 4 1 2 3 1 0 1 2 0 0 0 0 0 1 2 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,10 +116,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 30 -system_time: 0 -page_reclaims: 9017 -page_faults: 0 +user_time: 28 +system_time: 1 +page_reclaims: 7356 +page_faults: 1911 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -114,149 +127,158 @@ Network Stats ------------- +total_msg_count_Request_Control: 312048 2496384 +total_msg_count_Response_Data: 12 864 +total_msg_count_ResponseLocal_Data: 311742 22445424 +total_msg_count_Response_Control: 114033 912264 +total_msg_count_Forwarded_Control: 312000 2496000 +total_msg_count_Invalidate_Control: 2029 16232 +total_msg_count_Unblock_Control: 312006 2496048 +total_msgs: 1363870 total_bytes: 30863216 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.130563 - links_utilized_percent_switch_0_link_0: 0.0497661 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.211361 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.131232 + links_utilized_percent_switch_0_link_0: 0.0501218 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.212342 bw: 160000 base_latency: 1 outgoing_messages_switch_0_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 12977 934344 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 4794 38352 [ 0 0 4794 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 12995 103960 [ 12995 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 12993 935496 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 12993 103944 [ 0 0 12993 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseLocal_Data: 13058 940176 [ 0 0 13058 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 4791 38328 [ 0 0 4791 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Forwarded_Control: 13037 104296 [ 13037 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Invalidate_Control: 99 792 [ 99 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 13073 104584 [ 13073 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 13025 937800 [ 0 0 13025 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 99 792 [ 0 0 99 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 13071 104568 [ 0 0 13071 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.131025 - links_utilized_percent_switch_1_link_0: 0.0500265 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.212023 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.131323 + links_utilized_percent_switch_1_link_0: 0.0501147 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.212532 bw: 160000 base_latency: 1 outgoing_messages_switch_1_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13047 939384 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 4825 38600 [ 0 0 4825 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 13041 104328 [ 13041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Invalidate_Control: 113 904 [ 113 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 13065 104520 [ 13065 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13026 937872 [ 0 0 13026 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 113 904 [ 0 0 113 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 13063 104504 [ 0 0 13063 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_ResponseLocal_Data: 13061 940392 [ 0 0 13061 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 4731 37848 [ 0 0 4731 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Forwarded_Control: 13047 104376 [ 13047 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 13072 104576 [ 13072 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseLocal_Data: 13039 938808 [ 0 0 13039 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 13070 104560 [ 0 0 13070 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.130359 - links_utilized_percent_switch_2_link_0: 0.0496922 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.211027 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.131139 + links_utilized_percent_switch_2_link_0: 0.0499789 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.212299 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 12963 933336 [ 0 0 12963 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 4756 38048 [ 0 0 4756 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 12979 103832 [ 12979 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 12972 933984 [ 0 0 12972 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 97 776 [ 0 0 97 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 12977 103816 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 13017 937224 [ 0 0 13017 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Forwarded_Control: 13044 104352 [ 13044 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Invalidate_Control: 101 808 [ 101 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 13030 104240 [ 13030 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 13031 938232 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 101 808 [ 0 0 101 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 13029 104232 [ 0 0 13029 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.13073 - links_utilized_percent_switch_3_link_0: 0.0497838 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.211677 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.13049 + links_utilized_percent_switch_3_link_0: 0.0497573 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.211223 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12985 934920 [ 0 0 12985 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 4762 38096 [ 0 0 4762 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 13023 104184 [ 13023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 12993 103944 [ 12993 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 13017 937224 [ 0 0 13017 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 104 832 [ 0 0 104 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 12991 103928 [ 0 0 12991 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 12960 933120 [ 0 0 12960 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 4757 38056 [ 0 0 4757 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Forwarded_Control: 12973 103784 [ 12973 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 12972 103776 [ 12972 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 12963 933336 [ 0 0 12963 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 12970 103760 [ 0 0 12970 0 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.131205 - links_utilized_percent_switch_4_link_0: 0.0500587 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.212351 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.129438 + links_utilized_percent_switch_4_link_0: 0.0493392 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.209536 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 13069 940968 [ 0 0 13069 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 4715 37720 [ 0 0 4715 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 13059 104472 [ 13059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 13082 104656 [ 13082 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 13048 939456 [ 0 0 13048 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 103 824 [ 0 0 103 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 13080 104640 [ 0 0 13080 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 12856 925632 [ 0 0 12856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 4674 37392 [ 0 0 4674 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Forwarded_Control: 12873 102984 [ 12873 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Invalidate_Control: 92 736 [ 92 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 12871 102968 [ 12871 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 12860 925920 [ 0 0 12860 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 92 736 [ 0 0 92 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 12869 102952 [ 0 0 12869 0 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.13071 - links_utilized_percent_switch_5_link_0: 0.0498414 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.211579 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.129667 + links_utilized_percent_switch_5_link_0: 0.0493943 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.209939 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 13020 937440 [ 0 0 13020 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 4616 36928 [ 0 0 4616 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 13012 104096 [ 13012 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 13033 104264 [ 13033 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 13001 936072 [ 0 0 13001 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 102 816 [ 0 0 102 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 13031 104248 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_ResponseLocal_Data: 12862 926064 [ 0 0 12862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 4742 37936 [ 0 0 4742 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Forwarded_Control: 12896 103168 [ 12896 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Invalidate_Control: 96 768 [ 96 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 12870 102960 [ 12870 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 12890 928080 [ 0 0 12890 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 96 768 [ 0 0 96 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 12868 102944 [ 0 0 12868 0 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.131064 - links_utilized_percent_switch_6_link_0: 0.0499375 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.212191 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.131649 + links_utilized_percent_switch_6_link_0: 0.0501355 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.213162 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_ResponseLocal_Data: 13031 938232 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4732 37856 [ 0 0 4732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 13061 104488 [ 13061 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 13048 104384 [ 13048 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 13044 939168 [ 0 0 13044 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 98 784 [ 0 0 98 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 13047 104376 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_ResponseLocal_Data: 13062 940464 [ 0 0 13062 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 4752 38016 [ 0 0 4752 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Forwarded_Control: 13098 104784 [ 13098 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Invalidate_Control: 87 696 [ 87 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 13072 104576 [ 13072 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 13088 942336 [ 0 0 13088 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 87 696 [ 0 0 87 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 13071 104568 [ 0 0 13071 0 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.130272 - links_utilized_percent_switch_7_link_0: 0.0497081 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.210836 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.131133 + links_utilized_percent_switch_7_link_0: 0.0500544 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.212212 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 4785 38280 [ 0 0 4785 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 12972 103776 [ 12972 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Invalidate_Control: 116 928 [ 116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 12981 103848 [ 12981 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 12955 932760 [ 0 0 12955 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 116 928 [ 0 0 116 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 12980 103840 [ 0 0 12980 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 13038 938736 [ 0 0 13038 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 4790 38320 [ 0 0 4790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Forwarded_Control: 13032 104256 [ 13032 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Invalidate_Control: 112 896 [ 112 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 13054 104432 [ 13054 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 13018 937296 [ 0 0 13018 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 112 896 [ 0 0 112 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 13052 104416 [ 0 0 13052 0 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.143257 - links_utilized_percent_switch_8_link_0: 0.0769755 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.209539 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.143338 + links_utilized_percent_switch_8_link_0: 0.0769754 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.2097 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 104176 833408 [ 104176 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 104014 832112 [ 104014 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_0_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 104162 833296 [ 0 0 104162 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 104000 832000 [ 0 0 104000 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Response_Control: 37150 297200 [ 0 0 37150 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 104162 833296 [ 104162 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Invalidate_Control: 460 3680 [ 460 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Response_Control: 37218 297744 [ 0 0 37218 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Forwarded_Control: 104000 832000 [ 104000 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Invalidate_Control: 443 3544 [ 443 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 1.40388e-05 - links_utilized_percent_switch_9_link_0: 1.47777e-06 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.65998e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 1.40606e-05 + links_utilized_percent_switch_9_link_0: 1.48007e-06 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 2.66412e-05 bw: 160000 base_latency: 1 outgoing_messages_switch_9_link_0_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_0_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 @@ -264,2281 +286,1130 @@ switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.190316 - links_utilized_percent_switch_10_link_0: 0.199064 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.200106 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.198769 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.199135 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.200235 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.199366 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.19975 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.198832 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.190349 + links_utilized_percent_switch_10_link_0: 0.200487 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.200459 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.199916 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.199029 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.197357 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.197577 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.200542 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.200218 bw: 160000 base_latency: 1 links_utilized_percent_switch_10_link_8: 0.307902 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 5.91107e-06 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 5.92027e-06 bw: 160000 base_latency: 1 outgoing_messages_switch_10_link_0_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 12977 934344 [ 0 0 12977 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 4794 38352 [ 0 0 4794 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Forwarded_Control: 13008 104064 [ 13008 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_ResponseLocal_Data: 13058 940176 [ 0 0 13058 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Control: 4791 38328 [ 0 0 4791 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Forwarded_Control: 13037 104296 [ 13037 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Invalidate_Control: 99 792 [ 99 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_1_Response_Data: 1 72 [ 0 0 1 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13047 939384 [ 0 0 13047 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 4825 38600 [ 0 0 4825 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Forwarded_Control: 13041 104328 [ 13041 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Invalidate_Control: 113 904 [ 113 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 12963 933336 [ 0 0 12963 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 4756 38048 [ 0 0 4756 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Forwarded_Control: 12986 103888 [ 12986 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Invalidate_Control: 97 776 [ 97 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12985 934920 [ 0 0 12985 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Control: 4762 38096 [ 0 0 4762 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Forwarded_Control: 13023 104184 [ 13023 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Invalidate_Control: 104 832 [ 104 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 13069 940968 [ 0 0 13069 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 4715 37720 [ 0 0 4715 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Forwarded_Control: 13059 104472 [ 13059 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 13020 937440 [ 0 0 13020 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 4616 36928 [ 0 0 4616 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Forwarded_Control: 13012 104096 [ 13012 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Invalidate_Control: 102 816 [ 102 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_ResponseLocal_Data: 13031 938232 [ 0 0 13031 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4732 37856 [ 0 0 4732 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Forwarded_Control: 13061 104488 [ 13061 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Invalidate_Control: 98 784 [ 98 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12964 933408 [ 0 0 12964 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 4785 38280 [ 0 0 4785 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Forwarded_Control: 12972 103776 [ 12972 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Invalidate_Control: 116 928 [ 116 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 104176 833408 [ 104176 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_ResponseLocal_Data: 13061 940392 [ 0 0 13061 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 4731 37848 [ 0 0 4731 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Forwarded_Control: 13047 104376 [ 13047 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 13017 937224 [ 0 0 13017 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 4774 38192 [ 0 0 4774 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Forwarded_Control: 13044 104352 [ 13044 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Invalidate_Control: 101 808 [ 101 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 12960 933120 [ 0 0 12960 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Control: 4757 38056 [ 0 0 4757 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Forwarded_Control: 12973 103784 [ 12973 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Invalidate_Control: 103 824 [ 103 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 12856 925632 [ 0 0 12856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 4674 37392 [ 0 0 4674 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Forwarded_Control: 12873 102984 [ 12873 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Invalidate_Control: 92 736 [ 92 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_ResponseLocal_Data: 12862 926064 [ 0 0 12862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 4742 37936 [ 0 0 4742 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Forwarded_Control: 12896 103168 [ 12896 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Invalidate_Control: 96 768 [ 96 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_ResponseLocal_Data: 13062 940464 [ 0 0 13062 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 4752 38016 [ 0 0 4752 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Forwarded_Control: 13098 104784 [ 13098 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Invalidate_Control: 87 696 [ 87 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 13038 938736 [ 0 0 13038 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Control: 4790 38320 [ 0 0 4790 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Forwarded_Control: 13032 104256 [ 13032 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Invalidate_Control: 112 896 [ 112 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 104014 832112 [ 104014 0 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_8_Response_Data: 2 144 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Unblock_Control: 104162 833296 [ 0 0 104162 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Unblock_Control: 104000 832000 [ 0 0 104000 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Request_Control: 2 16 [ 0 2 0 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_9_Unblock_Control: 2 16 [ 0 0 2 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 99023 -Ifetch 0 -Store 53582 -L1_Replacement 0 -Own_GETX 15 -Fwd_GETX 21995 -Fwd_GETS 41350 -Fwd_DMA 0 -Inv 102 -Ack 4794 -Data 115 -Exclusive_Data 12863 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4711 -Use_Timeout 12878 +Load [98072 98434 100000 99606 99361 99698 99687 98810 ] 793668 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [52986 53087 53736 53526 54098 53889 53574 53478 ] 428374 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Own_GETX [13 6 9 14 12 8 12 10 ] 84 +Fwd_GETX [22585 22076 22466 22259 22813 23029 23300 22375 ] 180903 +Fwd_GETS [40144 40688 41281 41243 40853 40620 40250 40825 ] 325904 +Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +Inv [92 96 87 112 99 103 101 103 ] 793 +Ack [4674 4742 4752 4790 4791 4731 4774 4757 ] 38011 +Data [103 106 101 132 118 116 113 111 ] 900 +Exclusive_Data [12753 12756 12961 12906 12941 12946 12904 12849 ] 103016 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +All_acks [4576 4645 4653 4679 4683 4651 4668 4662 ] 37217 +Use_Timeout [12766 12762 12969 12920 12953 12954 12915 12859 ] 103098 - Transitions - -I Load 8283 -I Ifetch 0 <-- -I Store 4542 -I L1_Replacement 0 <-- -I Inv 0 <-- +I Load [8294 8225 8418 8375 8388 8419 8362 8309 ] 66790 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [4436 4494 4506 4509 4536 4512 4509 4507 ] 36009 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I Inv [0 0 0 0 0 0 0 0 ] 0 -S Load 166 -S Ifetch 0 <-- -S Store 100 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 15 +S Load [154 166 157 239 168 205 157 146 ] 1392 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [87 92 88 115 106 99 100 98 ] 785 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +S Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +S Inv [16 14 13 17 12 17 13 13 ] 115 -O Load 114 -O Ifetch 0 <-- -O Store 70 -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 7 -O Fwd_DMA 0 <-- +O Load [89 130 106 104 86 63 96 70 ] 744 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [54 59 60 55 43 42 59 58 ] 430 +O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +O Fwd_GETX [2 5 1 4 2 2 1 2 ] 19 +O Fwd_GETS [4 7 7 3 3 3 2 0 ] 29 +O Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M Load 138 -M Ifetch 0 <-- -M Store 67 -M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 70 -M Fwd_DMA 0 <-- +M Load [132 130 137 130 106 99 130 117 ] 981 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [66 60 74 61 64 68 61 68 ] 522 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Fwd_GETX [33 32 26 36 34 21 35 22 ] 239 +M Fwd_GETS [56 64 61 59 45 44 60 60 ] 449 +M Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -M_W Load 14727 -M_W Ifetch 0 <-- -M_W Store 7998 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1309 -M_W Fwd_GETS 2512 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 169 +M_W Load [14713 14467 15193 15198 15098 14823 14978 14489 ] 118959 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [8035 7961 8156 8085 8127 8170 8092 8047 ] 64673 +M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 +M_W Fwd_GETX [1348 1345 1422 1395 1440 1376 1484 1274 ] 11084 +M_W Fwd_GETS [2559 2460 2622 2567 2549 2429 2423 2488 ] 20097 +M_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +M_W Inv [0 0 0 0 0 0 0 0 ] 0 +M_W Use_Timeout [155 156 161 156 143 133 156 150 ] 1210 -MM Load 11464 -MM Ifetch 0 <-- -MM Store 6136 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4431 -MM Fwd_GETS 8345 -MM Fwd_DMA 0 <-- +MM Load [11277 11480 11564 11508 11508 11628 11573 11517 ] 92055 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [6104 6138 6257 6214 6255 6190 6205 6045 ] 49408 +MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM Fwd_GETX [4563 4445 4540 4487 4606 4662 4693 4532 ] 36528 +MM Fwd_GETS [8114 8221 8342 8338 8268 8227 8127 8245 ] 65882 +MM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 -MM_W Load 64131 -MM_W Ifetch 0 <-- -MM_W Store 34669 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16168 -MM_W Fwd_GETS 30363 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12709 +MM_W Load [63413 63836 64425 64052 64007 64461 64391 64162 ] 512747 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [34204 34283 34595 34487 34967 34808 34548 34655 ] 276547 +MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W Own_GETX [0 0 0 0 0 0 0 0 ] 0 +MM_W Fwd_GETX [16598 16196 16426 16296 16700 16934 17040 16497 ] 132687 +MM_W Fwd_GETS [29364 29873 30189 30226 29952 29871 29572 29978 ] 239025 +MM_W Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +MM_W Inv [0 0 0 0 0 0 0 0 ] 0 +MM_W Use_Timeout [12611 12606 12808 12764 12810 12821 12759 12709 ] 101888 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4704 -IM Data 0 <-- -IM Exclusive_Data 4683 +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Inv [0 0 0 0 0 0 0 0 ] 0 +IM Ack [4578 4659 4663 4675 4676 4656 4676 4673 ] 37256 +IM Data [0 0 0 0 0 0 0 0 ] 0 +IM Exclusive_Data [4552 4629 4630 4645 4652 4630 4644 4644 ] 37026 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 87 -SM Ack 24 -SM Data 0 <-- -SM Exclusive_Data 13 +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +SM Inv [76 82 74 95 87 86 88 90 ] 678 +SM Ack [23 24 28 34 43 25 24 23 ] 224 +SM Data [0 0 0 0 0 0 0 0 ] 0 +SM Exclusive_Data [11 10 14 20 19 13 12 8 ] 107 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 15 -OM Fwd_GETX 55 -OM Fwd_GETS 53 -OM Fwd_DMA 0 <-- -OM Ack 66 -OM All_acks 4711 +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM Own_GETX [13 6 9 14 12 8 12 10 ] 84 +OM Fwd_GETX [41 53 51 41 31 34 47 48 ] 346 +OM Fwd_GETS [47 63 60 50 36 46 66 54 ] 422 +OM Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +OM Ack [73 59 61 81 72 50 74 61 ] 531 +OM All_acks [4576 4645 4653 4679 4683 4651 4668 4662 ] 37217 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 115 -IS Exclusive_Data 8167 +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Inv [0 0 0 0 0 0 0 0 ] 0 +IS Data [103 106 101 132 118 116 113 111 ] 900 +IS Exclusive_Data [8190 8117 8317 8241 8270 8303 8248 8197 ] 65883 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +SI Load [0 0 0 0 0 0 0 0 ] 0 +SI Ifetch [0 0 0 0 0 0 0 0 ] 0 +SI Store [0 0 0 0 0 0 0 0 ] 0 +SI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +SI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +SI Inv [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +SI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +OI Load [0 0 0 0 0 0 0 0 ] 0 +OI Ifetch [0 0 0 0 0 0 0 0 ] 0 +OI Store [0 0 0 0 0 0 0 0 ] 0 +OI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- +MI Load [0 0 0 0 0 0 0 0 ] 0 +MI Ifetch [0 0 0 0 0 0 0 0 ] 0 +MI Store [0 0 0 0 0 0 0 0 ] 0 +MI L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Fwd_DMA [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +II Load [0 0 0 0 0 0 0 0 ] 0 +II Ifetch [0 0 0 0 0 0 0 0 ] 0 +II Store [0 0 0 0 0 0 0 0 ] 0 +II L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +II Inv [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack_Data [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.icache + system.l1_cntrl1.sequencer.icache_total_misses: 0 + system.l1_cntrl1.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.icache_total_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.dcache + system.l1_cntrl1.sequencer.dcache_total_misses: 0 + system.l1_cntrl1.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 1 --- +Cache Stats: system.l1_cntrl2.sequencer.icache + system.l1_cntrl2.sequencer.icache_total_misses: 0 + system.l1_cntrl2.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.icache_total_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.sequencer.dcache + system.l1_cntrl2.sequencer.dcache_total_misses: 0 + system.l1_cntrl2.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.sequencer.icache + system.l1_cntrl3.sequencer.icache_total_misses: 0 + system.l1_cntrl3.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.icache_total_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.sequencer.dcache + system.l1_cntrl3.sequencer.dcache_total_misses: 0 + system.l1_cntrl3.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.sequencer.icache + system.l1_cntrl4.sequencer.icache_total_misses: 0 + system.l1_cntrl4.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.icache_total_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.sequencer.dcache + system.l1_cntrl4.sequencer.dcache_total_misses: 0 + system.l1_cntrl4.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.sequencer.icache + system.l1_cntrl5.sequencer.icache_total_misses: 0 + system.l1_cntrl5.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.icache_total_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.sequencer.dcache + system.l1_cntrl5.sequencer.dcache_total_misses: 0 + system.l1_cntrl5.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.sequencer.icache + system.l1_cntrl6.sequencer.icache_total_misses: 0 + system.l1_cntrl6.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.icache_total_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.sequencer.dcache + system.l1_cntrl6.sequencer.dcache_total_misses: 0 + system.l1_cntrl6.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.sequencer.icache + system.l1_cntrl7.sequencer.icache_total_misses: 0 + system.l1_cntrl7.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.icache_total_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.sequencer.dcache + system.l1_cntrl7.sequencer.dcache_total_misses: 0 + system.l1_cntrl7.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_hw_prefetches: 0 + + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + + --- L2Cache --- - Event Counts - -Load 99832 -Ifetch 0 -Store 53534 -L1_Replacement 0 -Own_GETX 15 -Fwd_GETX 22841 -Fwd_GETS 40784 -Fwd_DMA 0 -Inv 113 -Ack 4825 -Data 126 -Exclusive_Data 12922 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4716 -Use_Timeout 12937 +L1_GETS [2721937 ] 2721937 +L1_GETX [1519721 ] 1519721 +L1_PUTO [0 ] 0 +L1_PUTX [0 ] 0 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [1 ] 1 +Data [1 ] 1 +Data_Exclusive [1 ] 1 +L1_WBCLEANDATA [0 ] 0 +L1_WBDIRTYDATA [0 ] 0 +Writeback_Ack [0 ] 0 +Writeback_Nack [0 ] 0 +Unblock [900 ] 900 +Exclusive_Unblock [103100 ] 103100 +L2_Replacement [0 ] 0 - Transitions - -I Load 8348 -I Ifetch 0 <-- -I Store 4563 -I L1_Replacement 0 <-- -I Inv 0 <-- +NP L1_GETS [1 ] 1 +NP L1_GETX [1 ] 1 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 -S Load 229 -S Ifetch 0 <-- -S Store 102 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 24 +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 -O Load 78 -O Ifetch 0 <-- -O Store 52 -O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 2 -O Fwd_DMA 0 <-- +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 -M Load 127 -M Ifetch 0 <-- -M Store 53 -M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 54 -M Fwd_DMA 0 <-- +ILX L1_GETS [66331 ] 66331 +ILX L1_GETX [36769 ] 36769 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [0 ] 0 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 -M_W Load 14558 -M_W Ifetch 0 <-- -M_W Store 8082 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1302 -M_W Fwd_GETS 2460 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 139 +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 -MM Load 11606 -MM Ifetch 0 <-- -MM Store 6135 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4608 -MM Fwd_GETS 8243 -MM Fwd_DMA 0 <-- +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 -MM_W Load 64886 -MM_W Ifetch 0 <-- -MM_W Store 34547 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16860 -MM_W Fwd_GETS 29977 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12798 +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4712 -IM Data 0 <-- -IM Exclusive_Data 4688 +ILOSX L1_GETS [451 ] 451 +ILOSX L1_GETX [449 ] 449 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 89 -SM Ack 30 -SM Data 0 <-- -SM Exclusive_Data 13 +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 15 -OM Fwd_GETX 37 -OM Fwd_GETS 48 -OM Fwd_DMA 0 <-- -OM Ack 83 -OM All_acks 4716 +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 126 -IS Exclusive_Data 8221 +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 - --- L1Cache 2 --- - - Event Counts - -Load 98648 -Ifetch 0 -Store 53693 -L1_Replacement 0 -Own_GETX 14 -Fwd_GETX 22578 -Fwd_GETS 40716 -Fwd_DMA 0 -Inv 97 -Ack 4756 -Data 101 -Exclusive_Data 12862 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4665 -Use_Timeout 12876 +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 - - Transitions - -I Load 8314 -I Ifetch 0 <-- -I Store 4523 -I L1_Replacement 0 <-- -I Inv 0 <-- +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 -S Load 156 -S Ifetch 0 <-- -S Store 88 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 13 +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 -O Load 95 -O Ifetch 0 <-- -O Store 54 -O L1_Replacement 0 <-- -O Fwd_GETX 1 -O Fwd_GETS 5 -O Fwd_DMA 0 <-- +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 -M Load 117 -M Ifetch 0 <-- -M Store 75 -M L1_Replacement 0 <-- -M Fwd_GETX 25 -M Fwd_GETS 55 -M Fwd_DMA 0 <-- +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 -M_W Load 14809 -M_W Ifetch 0 <-- -M_W Store 8056 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1398 -M_W Fwd_GETS 2484 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 155 +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 -MM Load 11304 -MM Ifetch 0 <-- -MM Store 6290 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4562 -MM Fwd_GETS 8234 -MM Fwd_DMA 0 <-- +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 -MM_W Load 63853 -MM_W Ifetch 0 <-- -MM_W Store 34607 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16552 -MM_W Fwd_GETS 29888 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12721 +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4666 -IM Data 0 <-- -IM Exclusive_Data 4647 +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 7 -SM Data 0 <-- -SM Exclusive_Data 4 +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 14 -OM Fwd_GETX 40 -OM Fwd_GETS 50 -OM Fwd_DMA 0 <-- -OM Ack 83 -OM All_acks 4665 +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 101 -IS Exclusive_Data 8211 +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +ILXW L1_GETS [0 ] 0 +ILXW L1_GETX [0 ] 0 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [0 ] 0 +ILXW L1_WBDIRTYDATA [0 ] 0 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +IFLOXX L1_GETS [2648154 ] 2648154 +IFLOXX L1_GETX [1473522 ] 1473522 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [449 ] 449 +IFLOXX Exclusive_Unblock [102649 ] 102649 +IFLOXX L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 +IFLOSX L1_GETS [3177 ] 3177 +IFLOSX L1_GETX [4409 ] 4409 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [451 ] 451 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +IFLXO L1_GETS [3395 ] 3395 +IFLXO L1_GETX [4544 ] 4544 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [449 ] 449 +IFLXO L2_Replacement [0 ] 0 - --- L1Cache 3 --- - - Event Counts - -Load 99441 -Ifetch 0 -Store 53405 -L1_Replacement 0 -Own_GETX 6 -Fwd_GETX 22814 -Fwd_GETS 40551 -Fwd_DMA 0 -Inv 104 -Ack 4762 -Data 117 -Exclusive_Data 12868 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4673 -Use_Timeout 12874 +IGS L1_GETS [162 ] 162 +IGS L1_GETX [27 ] 27 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [0 ] 0 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [1 ] 1 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [1 ] 1 +IGS L2_Replacement [0 ] 0 - - Transitions - -I Load 8319 -I Ifetch 0 <-- -I Store 4518 -I L1_Replacement 0 <-- -I Inv 0 <-- +IGM L1_GETS [252 ] 252 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [1 ] 1 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 -S Load 207 -S Ifetch 0 <-- -S Store 92 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 25 +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 -O Load 119 -O Ifetch 0 <-- -O Store 64 -O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 6 -O Fwd_DMA 0 <-- +IGMO L1_GETS [14 ] 14 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [0 ] 0 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [1 ] 1 +IGMO Exclusive_Unblock [1 ] 1 +IGMO L2_Replacement [0 ] 0 -M Load 168 -M Ifetch 0 <-- -M Store 54 -M L1_Replacement 0 <-- -M Fwd_GETX 44 -M Fwd_GETS 66 -M Fwd_DMA 0 <-- +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 -M_W Load 15070 -M_W Ifetch 0 <-- -M_W Store 8037 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1396 -M_W Fwd_GETS 2516 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 164 +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 -MM Load 11490 -MM Ifetch 0 <-- -MM Store 6222 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4591 -MM Fwd_GETS 8173 -MM Fwd_DMA 0 <-- +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 -MM_W Load 64068 -MM_W Ifetch 0 <-- -MM_W Store 34418 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16723 -MM_W Fwd_GETS 29713 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12710 +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4672 -IM Data 0 <-- -IM Exclusive_Data 4654 +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 79 -SM Ack 33 -SM Data 0 <-- -SM Exclusive_Data 13 +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 6 -OM Fwd_GETX 58 -OM Fwd_GETS 77 -OM Fwd_DMA 0 <-- -OM Ack 57 -OM All_acks 4673 +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [0 ] 0 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [0 ] 0 +MM L2_Replacement [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 117 -IS Exclusive_Data 8201 +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [0 ] 0 +OO L2_Replacement [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +MI L1_GETS [0 ] 0 +MI L1_GETX [0 ] 0 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI L2_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 - --- L1Cache 4 --- - - Event Counts - -Load 99795 -Ifetch 0 -Store 53955 -L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22437 -Fwd_GETS 41296 -Fwd_DMA 0 -Inv 103 -Ack 4715 -Data 119 -Exclusive_Data 12950 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4613 -Use_Timeout 12961 +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 - - Transitions - -I Load 8468 -I Ifetch 0 <-- -I Store 4465 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 183 -S Ifetch 0 <-- -S Store 100 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 19 - -O Load 97 -O Ifetch 0 <-- -O Store 49 -O L1_Replacement 0 <-- -O Fwd_GETX 5 -O Fwd_GETS 4 -O Fwd_DMA 0 <-- - -M Load 132 -M Ifetch 0 <-- -M Store 65 -M L1_Replacement 0 <-- -M Fwd_GETX 37 -M Fwd_GETS 54 -M Fwd_DMA 0 <-- - -M_W Load 15376 -M_W Ifetch 0 <-- -M_W Store 8192 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1382 -M_W Fwd_GETS 2630 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 156 - -MM Load 11543 -MM Ifetch 0 <-- -MM Store 6269 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4521 -MM Fwd_GETS 8349 -MM Fwd_DMA 0 <-- - -MM_W Load 63996 -MM_W Ifetch 0 <-- -MM_W Store 34815 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16454 -MM_W Fwd_GETS 30219 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12805 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4614 -IM Data 0 <-- -IM Exclusive_Data 4586 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 29 -SM Data 0 <-- -SM Exclusive_Data 16 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 38 -OM Fwd_GETS 40 -OM Fwd_DMA 0 <-- -OM Ack 72 -OM All_acks 4613 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 119 -IS Exclusive_Data 8348 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 99739 -Ifetch 0 -Store 53481 -L1_Replacement 0 -Own_GETX 11 -Fwd_GETX 22829 -Fwd_GETS 40648 -Fwd_DMA 0 -Inv 102 -Ack 4616 -Data 118 -Exclusive_Data 12902 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4488 -Use_Timeout 12913 - - - Transitions - -I Load 8545 -I Ifetch 0 <-- -I Store 4332 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 143 -S Ifetch 0 <-- -S Store 107 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 11 - -O Load 59 -O Ifetch 0 <-- -O Store 49 -O L1_Replacement 0 <-- -O Fwd_GETX 1 -O Fwd_GETS 1 -O Fwd_DMA 0 <-- - -M Load 116 -M Ifetch 0 <-- -M Store 73 -M L1_Replacement 0 <-- -M Fwd_GETX 34 -M Fwd_GETS 50 -M Fwd_DMA 0 <-- - -M_W Load 15492 -M_W Ifetch 0 <-- -M_W Store 8268 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1474 -M_W Fwd_GETS 2608 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 157 - -MM Load 11554 -MM Ifetch 0 <-- -MM Store 6300 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4609 -MM Fwd_GETS 8220 -MM Fwd_DMA 0 <-- - -MM_W Load 63830 -MM_W Ifetch 0 <-- -MM_W Store 34352 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16673 -MM_W Fwd_GETS 29721 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12756 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4494 -IM Data 0 <-- -IM Exclusive_Data 4461 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 91 -SM Ack 29 -SM Data 0 <-- -SM Exclusive_Data 16 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 11 -OM Fwd_GETX 38 -OM Fwd_GETS 48 -OM Fwd_DMA 0 <-- -OM Ack 93 -OM All_acks 4488 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 118 -IS Exclusive_Data 8425 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 53654 -L1_Replacement 0 -Own_GETX 16 -Fwd_GETX 22688 -Fwd_GETS 40941 -Fwd_DMA 0 -Inv 98 -Ack 4732 -Data 112 -Exclusive_Data 12919 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4621 -Use_Timeout 12934 - - - Transitions - -I Load 8427 -I Ifetch 0 <-- -I Store 4464 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 142 -S Ifetch 0 <-- -S Store 98 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 14 - -O Load 101 -O Ifetch 0 <-- -O Store 59 -O L1_Replacement 0 <-- -O Fwd_GETX 2 -O Fwd_GETS 4 -O Fwd_DMA 0 <-- - -M Load 128 -M Ifetch 0 <-- -M Store 65 -M L1_Replacement 0 <-- -M Fwd_GETX 31 -M Fwd_GETS 61 -M Fwd_DMA 0 <-- - -M_W Load 15324 -M_W Ifetch 0 <-- -M_W Store 8157 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1433 -M_W Fwd_GETS 2557 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 157 - -MM Load 11583 -MM Ifetch 0 <-- -MM Store 6297 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4582 -MM Fwd_GETS 8260 -MM Fwd_DMA 0 <-- - -MM_W Load 64296 -MM_W Ifetch 0 <-- -MM_W Store 34514 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16597 -MM_W Fwd_GETS 29998 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12777 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4614 -IM Data 0 <-- -IM Exclusive_Data 4591 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 84 -SM Ack 29 -SM Data 0 <-- -SM Exclusive_Data 14 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 16 -OM Fwd_GETX 43 -OM Fwd_GETS 61 -OM Fwd_DMA 0 <-- -OM Ack 89 -OM All_acks 4621 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 112 -IS Exclusive_Data 8314 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 98992 -Ifetch 0 -Store 53546 -L1_Replacement 0 -Own_GETX 16 -Fwd_GETX 22318 -Fwd_GETS 40836 -Fwd_DMA 0 -Inv 116 -Ack 4785 -Data 125 -Exclusive_Data 12839 -Writeback_Ack 0 -Writeback_Ack_Data 0 -Writeback_Nack 0 -All_acks 4665 -Use_Timeout 12854 - - - Transitions - -I Load 8316 -I Ifetch 0 <-- -I Store 4506 -I L1_Replacement 0 <-- -I Inv 0 <-- - -S Load 205 -S Ifetch 0 <-- -S Store 104 -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 21 - -O Load 96 -O Ifetch 0 <-- -O Store 55 -O L1_Replacement 0 <-- -O Fwd_GETX 4 -O Fwd_GETS 4 -O Fwd_DMA 0 <-- - -M Load 145 -M Ifetch 0 <-- -M Store 63 -M L1_Replacement 0 <-- -M Fwd_GETX 32 -M Fwd_GETS 59 -M Fwd_DMA 0 <-- - -M_W Load 14823 -M_W Ifetch 0 <-- -M_W Store 8036 -M_W L1_Replacement 0 <-- -M_W Own_GETX 0 <-- -M_W Fwd_GETX 1327 -M_W Fwd_GETS 2573 -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 154 - -MM Load 11394 -MM Ifetch 0 <-- -MM Store 6188 -MM L1_Replacement 0 <-- -MM Fwd_GETX 4510 -MM Fwd_GETS 8253 -MM Fwd_DMA 0 <-- - -MM_W Load 64013 -MM_W Ifetch 0 <-- -MM_W Store 34594 -MM_W L1_Replacement 0 <-- -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 16406 -MM_W Fwd_GETS 29893 -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 12700 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Inv 0 <-- -IM Ack 4682 -IM Data 0 <-- -IM Exclusive_Data 4640 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 95 -SM Ack 18 -SM Data 0 <-- -SM Exclusive_Data 9 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Own_GETX 16 -OM Fwd_GETX 39 -OM Fwd_GETS 54 -OM Fwd_DMA 0 <-- -OM Ack 85 -OM All_acks 4665 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Inv 0 <-- -IS Data 125 -IS Exclusive_Data 8190 - -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 0 <-- -MI Writeback_Nack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- - - Event Counts - -L1_GETS 2730499 -L1_GETX 1517781 -L1_PUTO 0 -L1_PUTX 0 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 2 -Data 2 -Data_Exclusive 0 -L1_WBCLEANDATA 0 -L1_WBDIRTYDATA 0 -Writeback_Ack 0 -Writeback_Nack 0 -Unblock 933 -Exclusive_Unblock 103229 -L2_Replacement 0 - - - Transitions - -NP L1_GETS 0 <-- -NP L1_GETX 2 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- - -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- - -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- - -ILX L1_GETS 66548 -ILX L1_GETX 36681 -ILX L1_PUTO 0 <-- -ILX L1_PUTX 0 <-- -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- - -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- - -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- - -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- - -ILOSX L1_GETS 464 -ILOSX L1_GETX 469 -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- - -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- - -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- - -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- - -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- - -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- - -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 0 <-- - -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- - -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- - -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- - -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- - -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- - -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- - -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- - -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- - -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- - -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- - -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- - -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- - -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- - -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- - -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- - -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- - -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- - -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- - -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 0 <-- -ILXW L1_WBDIRTYDATA 0 <-- -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- - -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- - -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- - -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- - -IFLOXX L1_GETS 2656172 -IFLOXX L1_GETX 1471349 -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 469 -IFLOXX Exclusive_Unblock 102758 -IFLOXX L2_Replacement 0 <-- - -IFLOSX L1_GETS 3369 -IFLOSX L1_GETX 4420 -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 464 -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- - -IFLXO L1_GETS 3686 -IFLXO L1_GETX 4665 -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 469 -IFLXO L2_Replacement 0 <-- - -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 0 <-- -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 0 <-- -IGS Unblock 0 <-- -IGS Exclusive_Unblock 0 <-- -IGS L2_Replacement 0 <-- - -IGM L1_GETS 244 -IGM L1_GETX 183 -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 2 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- - -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- - -IGMO L1_GETS 16 -IGMO L1_GETX 12 -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 0 <-- -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 2 -IGMO Exclusive_Unblock 2 -IGMO L2_Replacement 0 <-- - -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- - -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- - -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- - -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- - -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- - -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- - -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 0 <-- -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 0 <-- -MM L2_Replacement 0 <-- - -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- - -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 0 <-- -OO L2_Replacement 0 <-- - -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- - -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- - -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- - -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- - -MI L1_GETS 0 <-- -MI L1_GETX 0 <-- -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI L2_Replacement 0 <-- - -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- - -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- - -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -2558,201 +1429,200 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 2 -GETS 0 -PUTX 0 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 2 -Clean_Writeback 0 -Dirty_Writeback 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [1 ] 1 +GETS [1 ] 1 +PUTX [0 ] 0 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [2 ] 2 +Clean_Writeback [0 ] 0 +Dirty_Writeback [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 2 -I GETS 0 <-- -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [1 ] 1 +I GETS [1 ] 1 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -M GETX 0 <-- -M GETS 0 <-- -M PUTX 0 <-- -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [0 ] 0 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 0 <-- -IS Memory_Data 0 <-- -IS Memory_Ack 0 <-- -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [1 ] 1 +IS Memory_Data [1 ] 1 +IS Memory_Ack [0 ] 0 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 2 -MM Memory_Data 2 -MM Memory_Ack 0 <-- -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [1 ] 1 +MM Memory_Data [1 ] 1 +MM Memory_Ack [0 ] 0 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 0 <-- -MI Dirty_Writeback 0 <-- -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [0 ] 0 +MI Dirty_Writeback [0 ] 0 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @333700 -system.cpu3: completed 10000 read accesses @335770 -system.cpu4: completed 10000 read accesses @336327 -system.cpu1: completed 10000 read accesses @339698 -system.cpu2: completed 10000 read accesses @344150 -system.cpu6: completed 10000 read accesses @345138 -system.cpu7: completed 10000 read accesses @345167 -system.cpu0: completed 10000 read accesses @349190 -system.cpu6: completed 20000 read accesses @673266 -system.cpu5: completed 20000 read accesses @676289 -system.cpu7: completed 20000 read accesses @679722 -system.cpu3: completed 20000 read accesses @681408 -system.cpu4: completed 20000 read accesses @681933 -system.cpu2: completed 20000 read accesses @683973 -system.cpu0: completed 20000 read accesses @686720 -system.cpu1: completed 20000 read accesses @692941 -system.cpu4: completed 30000 read accesses @1007235 -system.cpu6: completed 30000 read accesses @1011621 -system.cpu7: completed 30000 read accesses @1013787 -system.cpu3: completed 30000 read accesses @1022376 -system.cpu1: completed 30000 read accesses @1026321 -system.cpu0: completed 30000 read accesses @1027922 -system.cpu5: completed 30000 read accesses @1030676 -system.cpu2: completed 30000 read accesses @1030823 -system.cpu6: completed 40000 read accesses @1348685 -system.cpu3: completed 40000 read accesses @1353011 -system.cpu4: completed 40000 read accesses @1356076 -system.cpu7: completed 40000 read accesses @1357286 -system.cpu1: completed 40000 read accesses @1359706 -system.cpu5: completed 40000 read accesses @1367254 -system.cpu2: completed 40000 read accesses @1373741 -system.cpu0: completed 40000 read accesses @1379957 -system.cpu4: completed 50000 read accesses @1688392 -system.cpu7: completed 50000 read accesses @1689568 -system.cpu6: completed 50000 read accesses @1689754 -system.cpu3: completed 50000 read accesses @1696699 -system.cpu1: completed 50000 read accesses @1706109 -system.cpu5: completed 50000 read accesses @1712886 -system.cpu2: completed 50000 read accesses @1716788 -system.cpu0: completed 50000 read accesses @1719320 -system.cpu7: completed 60000 read accesses @2028845 -system.cpu6: completed 60000 read accesses @2029028 -system.cpu3: completed 60000 read accesses @2030491 -system.cpu1: completed 60000 read accesses @2034867 -system.cpu4: completed 60000 read accesses @2042771 -system.cpu5: completed 60000 read accesses @2052491 -system.cpu2: completed 60000 read accesses @2054050 -system.cpu0: completed 60000 read accesses @2059964 -system.cpu1: completed 70000 read accesses @2366182 -system.cpu3: completed 70000 read accesses @2371740 -system.cpu6: completed 70000 read accesses @2378180 -system.cpu7: completed 70000 read accesses @2384422 -system.cpu4: completed 70000 read accesses @2385664 -system.cpu5: completed 70000 read accesses @2386969 -system.cpu0: completed 70000 read accesses @2391802 -system.cpu2: completed 70000 read accesses @2394315 -system.cpu1: completed 80000 read accesses @2697050 -system.cpu3: completed 80000 read accesses @2711777 -system.cpu5: completed 80000 read accesses @2712887 -system.cpu6: completed 80000 read accesses @2716967 -system.cpu7: completed 80000 read accesses @2729293 -system.cpu4: completed 80000 read accesses @2732109 -system.cpu0: completed 80000 read accesses @2735916 -system.cpu2: completed 80000 read accesses @2746698 -system.cpu5: completed 90000 read accesses @3042585 -system.cpu1: completed 90000 read accesses @3050146 -system.cpu4: completed 90000 read accesses @3051611 -system.cpu6: completed 90000 read accesses @3054450 -system.cpu3: completed 90000 read accesses @3060838 -system.cpu7: completed 90000 read accesses @3073385 -system.cpu0: completed 90000 read accesses @3084850 -system.cpu2: completed 90000 read accesses @3085570 -system.cpu6: completed 100000 read accesses @3383480 +system.cpu7: completed 10000 read accesses @332709 +system.cpu0: completed 10000 read accesses @339643 +system.cpu2: completed 10000 read accesses @339727 +system.cpu4: completed 10000 read accesses @340107 +system.cpu5: completed 10000 read accesses @341985 +system.cpu6: completed 10000 read accesses @343587 +system.cpu1: completed 10000 read accesses @347174 +system.cpu3: completed 10000 read accesses @348569 +system.cpu6: completed 20000 read accesses @670862 +system.cpu2: completed 20000 read accesses @675484 +system.cpu5: completed 20000 read accesses @679766 +system.cpu0: completed 20000 read accesses @680732 +system.cpu1: completed 20000 read accesses @681315 +system.cpu7: completed 20000 read accesses @687829 +system.cpu4: completed 20000 read accesses @691514 +system.cpu3: completed 20000 read accesses @696912 +system.cpu6: completed 30000 read accesses @1007800 +system.cpu2: completed 30000 read accesses @1010870 +system.cpu7: completed 30000 read accesses @1016124 +system.cpu0: completed 30000 read accesses @1017337 +system.cpu1: completed 30000 read accesses @1019165 +system.cpu5: completed 30000 read accesses @1035228 +system.cpu3: completed 30000 read accesses @1036256 +system.cpu4: completed 30000 read accesses @1042892 +system.cpu6: completed 40000 read accesses @1346068 +system.cpu2: completed 40000 read accesses @1350404 +system.cpu0: completed 40000 read accesses @1351547 +system.cpu1: completed 40000 read accesses @1360816 +system.cpu5: completed 40000 read accesses @1370364 +system.cpu7: completed 40000 read accesses @1370605 +system.cpu3: completed 40000 read accesses @1372316 +system.cpu4: completed 40000 read accesses @1386525 +system.cpu2: completed 50000 read accesses @1687076 +system.cpu0: completed 50000 read accesses @1688352 +system.cpu6: completed 50000 read accesses @1691655 +system.cpu1: completed 50000 read accesses @1703337 +system.cpu5: completed 50000 read accesses @1706376 +system.cpu7: completed 50000 read accesses @1709239 +system.cpu3: completed 50000 read accesses @1713068 +system.cpu4: completed 50000 read accesses @1728635 +system.cpu6: completed 60000 read accesses @2024490 +system.cpu0: completed 60000 read accesses @2028776 +system.cpu2: completed 60000 read accesses @2028921 +system.cpu1: completed 60000 read accesses @2036418 +system.cpu3: completed 60000 read accesses @2048805 +system.cpu7: completed 60000 read accesses @2049279 +system.cpu5: completed 60000 read accesses @2058079 +system.cpu4: completed 60000 read accesses @2061995 +system.cpu6: completed 70000 read accesses @2359127 +system.cpu0: completed 70000 read accesses @2369305 +system.cpu2: completed 70000 read accesses @2375719 +system.cpu7: completed 70000 read accesses @2376668 +system.cpu1: completed 70000 read accesses @2378652 +system.cpu3: completed 70000 read accesses @2384680 +system.cpu5: completed 70000 read accesses @2407919 +system.cpu4: completed 70000 read accesses @2412900 +system.cpu6: completed 80000 read accesses @2694787 +system.cpu2: completed 80000 read accesses @2705386 +system.cpu1: completed 80000 read accesses @2713513 +system.cpu0: completed 80000 read accesses @2713590 +system.cpu7: completed 80000 read accesses @2714927 +system.cpu3: completed 80000 read accesses @2729358 +system.cpu5: completed 80000 read accesses @2757669 +system.cpu4: completed 80000 read accesses @2758017 +system.cpu6: completed 90000 read accesses @3035671 +system.cpu1: completed 90000 read accesses @3047670 +system.cpu2: completed 90000 read accesses @3048712 +system.cpu0: completed 90000 read accesses @3052284 +system.cpu7: completed 90000 read accesses @3055140 +system.cpu3: completed 90000 read accesses @3075495 +system.cpu5: completed 90000 read accesses @3096844 +system.cpu4: completed 90000 read accesses @3098877 +system.cpu6: completed 100000 read accesses @3378223 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:39:50 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:38:22 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:38:50 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3383480 because maximum number of loads reached +Exiting @ tick 3378223 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340176 # Number of bytes of host memory used -host_seconds 30.43 # Real time elapsed on the host -host_tick_rate 111176 # Simulator tick rate (ticks/s) +host_mem_usage 342344 # Number of bytes of host memory used +host_seconds 31.75 # Real time elapsed on the host +host_tick_rate 106391 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003383 # Number of seconds simulated -sim_ticks 3383480 # Number of ticks simulated +sim_seconds 0.003378 # Number of seconds simulated +sim_ticks 3378223 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99022 # number of read accesses completed -system.cpu0.num_writes 53581 # number of write accesses completed +system.cpu0.num_reads 99361 # number of read accesses completed +system.cpu0.num_writes 54096 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99831 # number of read accesses completed -system.cpu1.num_writes 53533 # number of write accesses completed +system.cpu1.num_reads 99698 # number of read accesses completed +system.cpu1.num_writes 53887 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98646 # number of read accesses completed -system.cpu2.num_writes 53693 # number of write accesses completed +system.cpu2.num_reads 99686 # number of read accesses completed +system.cpu2.num_writes 53574 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99440 # number of read accesses completed -system.cpu3.num_writes 53404 # number of write accesses completed +system.cpu3.num_reads 98809 # number of read accesses completed +system.cpu3.num_writes 53477 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99794 # number of read accesses completed -system.cpu4.num_writes 53954 # number of write accesses completed +system.cpu4.num_reads 98071 # number of read accesses completed +system.cpu4.num_writes 52985 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99737 # number of read accesses completed -system.cpu5.num_writes 53481 # number of write accesses completed +system.cpu5.num_reads 98432 # number of read accesses completed +system.cpu5.num_writes 53087 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 53654 # number of write accesses completed +system.cpu6.num_writes 53735 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 98991 # number of read accesses completed -system.cpu7.num_writes 53546 # number of write accesses completed +system.cpu7.num_reads 99604 # number of read accesses completed +system.cpu7.num_writes 53526 # number of write accesses completed ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,14 @@ [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.l1_cntrl0.sequencer.port[0] [system.cpu1] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.l1_cntrl1.sequencer.port[0] [system.cpu2] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.l1_cntrl2.sequencer.port[0] [system.cpu3] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.l1_cntrl3.sequencer.port[0] [system.cpu4] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.l1_cntrl4.sequencer.port[0] [system.cpu5] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.l1_cntrl5.sequencer.port[0] [system.cpu6] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.l1_cntrl6.sequencer.port[0] [system.cpu7] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,51 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.l1_cntrl7.sequencer.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 [system.funcmem] type=PhysicalMemory @@ -139,6 +191,420 @@ zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl1.sequencer.dcache +L1IcacheMemory=system.l1_cntrl1.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl1.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl1.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.l1_cntrl1.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl2.sequencer.dcache +L1IcacheMemory=system.l1_cntrl2.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl2.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl2.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.l1_cntrl2.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl3.sequencer.dcache +L1IcacheMemory=system.l1_cntrl3.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl3.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl3.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.l1_cntrl3.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl4.sequencer.dcache +L1IcacheMemory=system.l1_cntrl4.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl4.sequencer +transitions_per_cycle=32 +version=4 + +[system.l1_cntrl4.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl4.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl4.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.l1_cntrl4.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl5.sequencer.dcache +L1IcacheMemory=system.l1_cntrl5.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl5.sequencer +transitions_per_cycle=32 +version=5 + +[system.l1_cntrl5.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl5.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl5.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.l1_cntrl5.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl6.sequencer.dcache +L1IcacheMemory=system.l1_cntrl6.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl6.sequencer +transitions_per_cycle=32 +version=6 + +[system.l1_cntrl6.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl6.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl6.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.l1_cntrl6.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl7.sequencer.dcache +L1IcacheMemory=system.l1_cntrl7.sequencer.icache +N_tokens=9 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl7.sequencer +transitions_per_cycle=32 +version=7 + +[system.l1_cntrl7.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl7.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl7.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.l1_cntrl7.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=9 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + [system.physmem] type=PhysicalMemory file= @@ -147,7 +613,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort [system.ruby] type=RubySystem @@ -188,532 +654,90 @@ children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 ext_links9 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 int_links9 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 system.ruby.network.topology.ext_links9 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 system.ruby.network.topology.int_links9 +name=Crossbar num_int_nodes=11 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l1_cntrl1 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer -transitions_per_cycle=32 -version=1 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.l1_cntrl2 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer -transitions_per_cycle=32 -version=2 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links3] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node +ext_node=system.l1_cntrl3 int_node=3 latency=1 weight=1 -[system.ruby.network.topology.ext_links3.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer -transitions_per_cycle=32 -version=3 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links4] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node +ext_node=system.l1_cntrl4 int_node=4 latency=1 weight=1 -[system.ruby.network.topology.ext_links4.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer -transitions_per_cycle=32 -version=4 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links5] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node +ext_node=system.l1_cntrl5 int_node=5 latency=1 weight=1 -[system.ruby.network.topology.ext_links5.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer -transitions_per_cycle=32 -version=5 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links6] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node +ext_node=system.l1_cntrl6 int_node=6 latency=1 weight=1 -[system.ruby.network.topology.ext_links6.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer -transitions_per_cycle=32 -version=6 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links7] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node +ext_node=system.l1_cntrl7 int_node=7 latency=1 weight=1 -[system.ruby.network.topology.ext_links7.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -N_tokens=9 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer -transitions_per_cycle=32 -version=7 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links8] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node +ext_node=system.l2_cntrl0 int_node=8 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory -N_tokens=9 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links9] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links9.ext_node +ext_node=system.dir_cntrl0 int_node=9 latency=1 weight=1 -[system.ruby.network.topology.ext_links9.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links9.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links9.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links9.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:40:04 +Real time: Aug/05/2010 10:44:38 Profiler Stats -------------- -Elapsed_time_in_seconds: 34 -Elapsed_time_in_minutes: 0.566667 -Elapsed_time_in_hours: 0.00944444 -Elapsed_time_in_days: 0.000393519 +Elapsed_time_in_seconds: 28 +Elapsed_time_in_minutes: 0.466667 +Elapsed_time_in_hours: 0.00777778 +Elapsed_time_in_days: 0.000324074 -Virtual_time_in_seconds: 35 -Virtual_time_in_minutes: 0.583333 -Virtual_time_in_hours: 0.00972222 -Virtual_time_in_days: 0.000405093 +Virtual_time_in_seconds: 24.73 +Virtual_time_in_minutes: 0.412167 +Virtual_time_in_hours: 0.00686944 +Virtual_time_in_days: 0.000286227 -Ruby_current_time: 3238178 +Ruby_current_time: 2588247 Ruby_start_time: 0 -Ruby_cycles: 3238178 +Ruby_cycles: 2588247 -mbytes_resident: 31.2969 -mbytes_total: 332.305 -resident_ratio: 0.094193 +mbytes_resident: 32.832 +mbytes_total: 32.8359 +resident_ratio: 1 -ruby_cycles_executed: [ 3238179 3238179 3238179 3238179 3238179 3238179 3238179 3238179 ] +ruby_cycles_executed: [ 2588248 2588248 2588248 2588248 2588248 2588248 2588248 2588248 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -67,13 +67,32 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1212936 average: 1.98562 | standard deviation: 0.119047 | 0 17440 1195496 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1205118 average: 1.99416 | standard deviation: 0.0761867 | 0 7036 1198082 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 8 max: 1024 count: 1212921 average: 40.7149 | standard deviation: 150.899 | 1141490 0 116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 68318 1609 231 251 277 280 196 67 26 21 0 1 0 0 5 14 8 1 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 8 max: 1024 count: 788284 average: 40.6125 | standard deviation: 150.71 | 742060 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 44290 1039 145 159 184 181 128 48 20 11 0 0 0 0 4 5 4 1 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 8 max: 950 count: 424637 average: 40.905 | standard deviation: 151.251 | 399430 0 116 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 24028 570 86 92 93 99 68 19 6 10 0 1 0 0 1 9 4 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 8 max: 1010 count: 1205103 average: 32.3608 | standard deviation: 136.128 | 1147971 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56601 423 25 12 4 10 4 10 0 2 0 0 0 0 1 4 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 8 max: 1010 count: 783747 average: 32.331 | standard deviation: 136.069 | 746645 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36778 266 18 8 3 6 2 7 0 2 0 0 0 0 0 3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4 max: 763 count: 421356 average: 32.4163 | standard deviation: 136.239 | 401326 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19194 629 114 43 0 7 2 2 0 1 4 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 1147971 average: 2 | standard deviation: 0 | 0 0 1147971 ] +miss_latency_Directory: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 8 max: 1010 count: 57130 average: 642.421 | standard deviation: 13.8853 | 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 56601 423 25 12 4 10 4 10 0 2 0 0 0 0 1 4 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_first_response_to_completion: [binsize: 8 max: 887 count: 6 average: 764.333 | standard deviation: 101.837 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_wCC_Times: 57124 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 369 count: 2 average: 314 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 746645 average: 2 | standard deviation: 0 | 0 0 746645 ] +miss_latency_LD_Directory: [binsize: 2 max: 259 count: 1 average: 259 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 8 max: 1010 count: 37101 average: 642.726 | standard deviation: 4.60803 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 36778 266 18 8 3 6 2 7 0 2 0 0 0 0 0 3 0 0 0 0 0 0 0 2 0 0 0 0 0 0 2 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 401326 average: 2 | standard deviation: 0 | 0 0 401326 ] +miss_latency_ST_Directory: [binsize: 2 max: 369 count: 1 average: 369 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 763 count: 20029 average: 641.858 | standard deviation: 22.5862 | 0 0 0 0 26 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 19194 629 114 43 0 7 2 2 0 1 4 0 0 2 0 3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,10 +122,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 34 +user_time: 23 system_time: 0 -page_reclaims: 9009 -page_faults: 0 +page_reclaims: 7323 +page_faults: 1909 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -114,3070 +133,907 @@ Network Stats ------------- +total_msg_count_Request_Control: 342876 2743008 +total_msg_count_Response_Data: 171318 12334896 +total_msg_count_ResponseLocal_Data: 42 3024 +total_msg_count_Response_Control: 171315 1370520 +total_msg_count_Broadcast_Control: 857190 6857520 +total_msg_count_Persistent_Control: 2284140 18273120 +total_msgs: 3826881 total_bytes: 41582088 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.151519 - links_utilized_percent_switch_0_link_0: 0.110184 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.192854 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.151709 + links_utilized_percent_switch_0_link_0: 0.110337 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.19308 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 17866 142928 [ 0 17866 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 8916 71328 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 17828 142624 [ 0 0 0 17828 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 50005 400040 [ 0 50005 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 7141 57128 [ 0 7141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 7137 513864 [ 0 0 0 0 7137 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 7139 57112 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Broadcast_Control: 7141 57128 [ 0 7141 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 14276 114208 [ 0 0 0 14276 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151526 - links_utilized_percent_switch_1_link_0: 0.110191 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.192862 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.1517 + links_utilized_percent_switch_1_link_0: 0.110337 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.193063 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 62515 500120 [ 0 62515 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 17860 142880 [ 0 17860 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 8917 71336 [ 0 0 0 0 8917 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Persistent_Control: 17829 142632 [ 0 0 0 17829 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 50004 400032 [ 0 50004 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 7142 57136 [ 0 7142 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 7138 57104 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Broadcast_Control: 7142 57136 [ 0 7142 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Persistent_Control: 14275 114200 [ 0 0 0 14275 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.151534 - links_utilized_percent_switch_2_link_0: 0.11019 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.192879 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.151716 + links_utilized_percent_switch_2_link_0: 0.110341 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.19309 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 62516 500128 [ 0 62516 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 17858 142864 [ 0 17858 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 8912 641664 [ 0 0 0 0 8912 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_ResponseLocal_Data: 11 792 [ 0 0 0 0 11 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 8918 71344 [ 0 0 0 0 8918 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Persistent_Control: 17832 142656 [ 0 0 0 17832 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 50003 400024 [ 0 50003 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 7143 57144 [ 0 7143 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 7138 57104 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Broadcast_Control: 7143 57144 [ 0 7143 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Persistent_Control: 14278 114224 [ 0 0 0 14278 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.151566 - links_utilized_percent_switch_3_link_0: 0.110202 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.192929 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.15175 + links_utilized_percent_switch_3_link_0: 0.110349 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.193152 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Request_Control: 62513 500104 [ 0 62513 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseLocal_Data: 14 1008 [ 0 0 0 0 14 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 17864 142912 [ 0 17864 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 8917 642024 [ 0 0 0 0 8917 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_ResponseLocal_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 50000 400000 [ 0 50000 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 7146 57168 [ 0 7146 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 7139 57112 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Broadcast_Control: 7146 57168 [ 0 7146 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 14276 114208 [ 0 0 0 14276 0 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.151524 - links_utilized_percent_switch_4_link_0: 0.110187 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.192862 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.151747 + links_utilized_percent_switch_4_link_0: 0.110349 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.193146 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 17866 142928 [ 0 17866 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 8914 71312 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 50001 400008 [ 0 50001 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 7145 57160 [ 0 7145 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 7138 57104 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Broadcast_Control: 7145 57160 [ 0 7145 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Persistent_Control: 14276 114208 [ 0 0 0 14276 0 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.151513 - links_utilized_percent_switch_5_link_0: 0.110184 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.192843 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.151695 + links_utilized_percent_switch_5_link_0: 0.110333 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.193057 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Request_Control: 62514 500112 [ 0 62514 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 8 64 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 17862 142896 [ 0 17862 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Persistent_Control: 17826 142608 [ 0 0 0 17826 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 50006 400048 [ 0 50006 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 7140 57120 [ 0 7140 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 7136 513792 [ 0 0 0 0 7136 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 7138 57104 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Broadcast_Control: 7140 57120 [ 0 7140 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Persistent_Control: 14276 114208 [ 0 0 0 14276 0 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.151473 - links_utilized_percent_switch_6_link_0: 0.110172 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.192775 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.15173 + links_utilized_percent_switch_6_link_0: 0.110341 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.193119 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Request_Control: 62522 500176 [ 0 62522 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_6_link_0_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 17846 142768 [ 0 17846 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 8909 641448 [ 0 0 0 0 8909 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 8919 71352 [ 0 0 0 0 8919 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Persistent_Control: 17830 142640 [ 0 0 0 17830 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 49999 399992 [ 0 49999 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 7147 57176 [ 0 7147 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 7138 57104 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Broadcast_Control: 7147 57176 [ 0 7147 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Persistent_Control: 14276 114208 [ 0 0 0 14276 0 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.151555 - links_utilized_percent_switch_7_link_0: 0.1102 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.192911 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.151717 + links_utilized_percent_switch_7_link_0: 0.110341 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.193094 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Request_Control: 62511 500088 [ 0 62511 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 8914 641808 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 17868 142944 [ 0 17868 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 8920 642240 [ 0 0 0 0 8920 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_ResponseLocal_Data: 5 360 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 8915 71320 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Persistent_Control: 17828 142624 [ 0 0 0 17828 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 7137 513864 [ 0 0 0 0 7137 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 50004 400032 [ 0 50004 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 7142 57136 [ 0 7142 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 7137 57096 [ 0 0 0 0 7137 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Broadcast_Control: 7142 57136 [ 0 7142 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Persistent_Control: 14274 114192 [ 0 0 0 14274 0 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.110233 - links_utilized_percent_switch_8_link_0: 0.110149 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.110317 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.110361 + links_utilized_percent_switch_8_link_0: 0.110327 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.110395 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 71445 571560 [ 0 71445 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Response_Control: 71275 570200 [ 0 0 0 0 71275 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 57146 457168 [ 0 57146 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Response_Control: 57090 456720 [ 0 0 0 0 57090 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 57146 457168 [ 0 0 57146 0 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 2 switch_9_outlinks: 2 -links_utilized_percent_switch_9: 0.0413315 - links_utilized_percent_switch_9_link_0: 0.0826352 bw: 640000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 2.77934e-05 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.0413951 + links_utilized_percent_switch_9_link_0: 0.0827553 bw: 640000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 3.47726e-05 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 57146 457168 [ 0 0 57146 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_9_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 switch_10_inlinks: 10 switch_10_outlinks: 10 -links_utilized_percent_switch_10: 0.407695 - links_utilized_percent_switch_10_link_0: 0.413208 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_1: 0.413234 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_2: 0.413228 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_3: 0.413285 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_4: 0.413225 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_5: 0.413211 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_6: 0.413155 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_7: 0.413271 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_8: 0.440595 bw: 160000 base_latency: 1 - links_utilized_percent_switch_10_link_9: 0.330541 bw: 160000 base_latency: 1 +links_utilized_percent_switch_10: 0.408261 + links_utilized_percent_switch_10_link_0: 0.413768 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 0.413772 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_2: 0.413782 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_3: 0.413817 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_4: 0.413817 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_5: 0.413755 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_6: 0.413784 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_7: 0.413788 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_8: 0.441308 bw: 160000 base_latency: 1 + links_utilized_percent_switch_10_link_9: 0.331021 bw: 160000 base_latency: 1 - outgoing_messages_switch_10_link_0_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_ResponseLocal_Data: 6 432 [ 0 0 0 0 6 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_0_Persistent_Control: 124797 998376 [ 0 0 0 124797 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Request_Control: 62515 500120 [ 0 62515 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_1_Persistent_Control: 124796 998368 [ 0 0 0 124796 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Request_Control: 62516 500128 [ 0 62516 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Data: 8916 641952 [ 0 0 0 0 8916 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_ResponseLocal_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_2_Persistent_Control: 124793 998344 [ 0 0 0 124793 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Request_Control: 62513 500104 [ 0 62513 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_ResponseLocal_Data: 14 1008 [ 0 0 0 0 14 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Broadcast_Control: 50005 400040 [ 0 50005 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Persistent_Control: 99931 799448 [ 0 0 0 99931 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Broadcast_Control: 50004 400032 [ 0 50004 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Persistent_Control: 99932 799456 [ 0 0 0 99932 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Data: 7139 514008 [ 0 0 0 0 7139 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_ResponseLocal_Data: 1 72 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Broadcast_Control: 50003 400024 [ 0 50003 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_2_Persistent_Control: 99929 799432 [ 0 0 0 99929 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_3_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_3_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Request_Control: 62512 500096 [ 0 62512 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_ResponseLocal_Data: 9 648 [ 0 0 0 0 9 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Response_Control: 10 80 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_4_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Request_Control: 62514 500112 [ 0 62514 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Data: 8913 641736 [ 0 0 0 0 8913 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_ResponseLocal_Data: 8 576 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Response_Control: 8 64 [ 0 0 0 0 8 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_5_Persistent_Control: 124799 998392 [ 0 0 0 124799 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Request_Control: 62522 500176 [ 0 62522 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Data: 8915 641880 [ 0 0 0 0 8915 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Broadcast_Control: 50000 400000 [ 0 50000 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_3_Persistent_Control: 99931 799448 [ 0 0 0 99931 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_ResponseLocal_Data: 4 288 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Broadcast_Control: 50001 400008 [ 0 50001 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_4_Persistent_Control: 99931 799448 [ 0 0 0 99931 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Broadcast_Control: 50006 400048 [ 0 50006 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_5_Persistent_Control: 99931 799448 [ 0 0 0 99931 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Data: 7138 513936 [ 0 0 0 0 7138 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_10_link_6_ResponseLocal_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Response_Control: 4 32 [ 0 0 0 0 4 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_6_Persistent_Control: 124795 998360 [ 0 0 0 124795 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Request_Control: 62511 500088 [ 0 62511 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Data: 8914 641808 [ 0 0 0 0 8914 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_ResponseLocal_Data: 12 864 [ 0 0 0 0 12 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Response_Control: 7 56 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_7_Persistent_Control: 124797 998376 [ 0 0 0 124797 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Request_Control: 71445 571560 [ 0 71445 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Response_Control: 71275 570200 [ 0 0 0 0 71275 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_8_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Request_Control: 71445 571560 [ 0 0 71445 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_10_link_9_Persistent_Control: 142625 1141000 [ 0 0 0 142625 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Response_Control: 5 40 [ 0 0 0 0 5 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Broadcast_Control: 49999 399992 [ 0 49999 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_6_Persistent_Control: 99931 799448 [ 0 0 0 99931 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Response_Data: 7137 513864 [ 0 0 0 0 7137 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_ResponseLocal_Data: 3 216 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Broadcast_Control: 50004 400032 [ 0 50004 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_7_Persistent_Control: 99933 799464 [ 0 0 0 99933 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Request_Control: 57146 457168 [ 0 57146 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Response_Control: 57090 456720 [ 0 0 0 0 57090 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_8_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Request_Control: 57146 457168 [ 0 0 57146 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_9_Persistent_Control: 114207 913656 [ 0 0 0 114207 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 7141 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 7141 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.dcache_request_type_LD: 64.5148% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 35.4852% - --- L1Cache 0 --- + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 7141 100% + + --- L1Cache --- - Event Counts - -Load 99985 -Ifetch 0 -Store 54267 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 19 -Data_All_Tokens 8902 -Ack 0 -Ack_All_Tokens 10 -Transient_GETX 0 -Transient_Local_GETX 22004 -Transient_GETS 0 -Transient_Local_GETS 40508 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25124 -Persistent_GETS 46317 -Own_Lock_or_Unlock 71183 -Request_Timeout 9369 -Use_TimeoutStarverX 2 -Use_TimeoutStarverS 5 -Use_TimeoutNoStarvers 8905 +Load [97292 96951 97054 97172 99896 100001 97710 97682 ] 783758 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [52328 52356 52770 52096 53779 53776 52049 52205 ] 421359 +Atomic [0 0 0 0 0 0 0 0 ] 0 +L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +Data_Shared [0 0 0 0 0 0 0 0 ] 0 +Data_Owner [6 2 7 1 2 2 3 5 ] 28 +Data_All_Tokens [7136 7136 7133 7139 7137 7137 7137 7137 ] 57092 +Ack [0 1 0 0 0 0 0 1 ] 2 +Ack_All_Tokens [2 0 5 0 0 2 2 2 ] 13 +Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETX [17534 17484 17475 17532 17499 17554 17577 17576 ] 140231 +Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETS [32467 32522 32524 32472 32506 32450 32426 32424 ] 259791 +Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Persistent_GETX [20893 21036 20946 21165 20347 20342 20766 20532 ] 166027 +Persistent_GETS [38612 39094 38873 39189 37808 37562 38347 37811 ] 307296 +Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +Own_Lock_or_Unlock [54702 54077 54388 53853 56052 56303 55094 55864 ] 440333 +Request_Timeout [7264 7170 7163 7227 7138 7155 7146 7179 ] 57442 +Use_TimeoutStarverX [11 34 20 35 0 1 10 2 ] 113 +Use_TimeoutStarverS [23 69 36 72 0 1 20 0 ] 221 +Use_TimeoutNoStarvers [7104 7033 7082 7032 7137 7136 7109 7137 ] 56770 +Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP Load [2 2 2 2 2 1 1 2 ] 14 +NP Ifetch [0 0 0 0 0 0 0 0 ] 0 +NP Store [0 0 0 0 0 1 1 0 ] 2 +NP Atomic [0 0 0 0 0 0 0 0 ] 0 +NP Data_Shared [0 0 0 0 0 0 0 0 ] 0 +NP Data_Owner [0 0 0 0 0 0 0 0 ] 0 +NP Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +NP Ack [0 0 0 0 0 0 0 0 ] 0 +NP Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +NP Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +NP Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -I Load 9 -I Ifetch 0 <-- -I Store 1 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 6 +I Load [3 1 1 1 1 0 1 2 ] 10 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [0 1 1 0 1 0 0 1 ] 4 +I Atomic [0 0 0 0 0 0 0 0 ] 0 +I L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I Data_Shared [0 0 0 0 0 0 0 0 ] 0 +I Data_Owner [0 0 0 0 0 0 0 0 ] 0 +I Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +I Ack [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +I Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I Own_Lock_or_Unlock [0 1 1 0 1 0 0 1 ] 4 -S Load 6 -S Ifetch 0 <-- -S Store 3 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S Load [0 1 0 0 0 0 0 0 ] 1 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [1 1 0 0 2 0 0 1 ] 5 +S Atomic [0 0 0 0 0 0 0 0 ] 0 +S L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S Data_Shared [0 0 0 0 0 0 0 0 ] 0 +S Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +S Ack [0 0 0 0 0 0 0 0 ] 0 +S Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +S Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +S Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +S Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -O Load 17 -O Ifetch 0 <-- -O Store 10 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 9 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 +O Load [7 1 11 0 0 2 3 4 ] 28 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [2 0 5 0 0 2 2 2 ] 13 +O Atomic [0 0 0 0 0 0 0 0 ] 0 +O L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +O Data_Shared [0 0 0 0 0 0 0 0 ] 0 +O Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Ack [0 0 0 0 0 0 0 0 ] 0 +O Ack_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +O Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETX [3 2 2 1 2 0 1 3 ] 14 +O Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +O Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +O Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +O Own_Lock_or_Unlock [4 1 5 1 1 1 1 2 ] 16 -M Load 134 -M Ifetch 0 <-- -M Store 70 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 4 -M Persistent_GETS 13 -M Own_Lock_or_Unlock 65 +M Load [38 58 35 74 54 58 41 41 ] 399 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [25 22 21 26 35 35 19 25 ] 208 +M Atomic [0 0 0 0 0 0 0 0 ] 0 +M L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +M Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +M Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +M Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +M Persistent_GETX [2 4 3 3 2 3 3 2 ] 22 +M Persistent_GETS [4 1 3 3 4 2 5 5 ] 27 +M Own_Lock_or_Unlock [20 23 17 23 29 25 19 18 ] 174 -MM Load 39402 -MM Ifetch 0 <-- -MM Store 21439 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3111 -MM Persistent_GETS 5777 -MM Own_Lock_or_Unlock 8638 +MM Load [37270 36906 37150 36946 39880 39731 37483 37441 ] 302807 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [19949 20057 20064 19924 21256 21373 19899 19929 ] 162451 +MM Atomic [0 0 0 0 0 0 0 0 ] 0 +MM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +MM Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +MM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +MM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +MM Persistent_GETX [2505 2461 2386 2473 2546 2494 2501 2501 ] 19867 +MM Persistent_GETS [4593 4567 4690 4553 4585 4637 4599 4629 ] 36853 +MM Own_Lock_or_Unlock [6798 6423 6530 6356 7082 7089 6709 7021 ] 54008 -M_W Load 10158 -M_W Ifetch 0 <-- -M_W Store 5618 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1506 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2887 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 21 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 87 +M_W Load [8734 8618 8211 8461 8560 8528 8699 8603 ] 68414 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [4608 4561 4553 4607 4563 4620 4656 4650 ] 36818 +M_W Atomic [0 0 0 0 0 0 0 0 ] 0 +M_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_Local_GETX [1185 1155 1152 1166 1144 1224 1201 1220 ] 9447 +M_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +M_W Transient_Local_GETS [2193 2192 2097 2191 2145 2151 2201 2204 ] 17374 +M_W Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +M_W Persistent_GETS [0 1 1 0 0 0 0 0 ] 2 +M_W Own_Lock_or_Unlock [2 0 0 0 0 2 1 1 ] 6 +M_W Use_TimeoutStarverX [0 0 0 0 0 0 0 0 ] 0 +M_W Use_TimeoutStarverS [0 0 0 0 0 0 0 0 ] 0 +M_W Use_TimeoutNoStarvers [31 27 27 32 41 40 27 32 ] 257 +M_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 -MM_W Load 44523 -MM_W Ifetch 0 <-- -MM_W Store 23933 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 964 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1719 -MM_W Persistent_GETX 2 -MM_W Persistent_GETS 5 -MM_W Own_Lock_or_Unlock 160 -MM_W Use_TimeoutStarverX 2 -MM_W Use_TimeoutStarverS 5 -MM_W Use_TimeoutNoStarvers 8818 +MM_W Load [46593 46773 47052 47050 46783 47015 46793 46896 ] 374955 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [25247 25167 25574 25038 25391 25269 25019 25144 ] 201849 +MM_W Atomic [0 0 0 0 0 0 0 0 ] 0 +MM_W L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_Local_GETX [695 728 751 704 691 664 689 698 ] 5620 +MM_W Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +MM_W Transient_Local_GETS [1314 1312 1310 1331 1308 1329 1274 1310 ] 10488 +MM_W Persistent_GETX [10 34 20 35 0 1 10 2 ] 112 +MM_W Persistent_GETS [21 68 35 71 0 1 19 0 ] 215 +MM_W Own_Lock_or_Unlock [75 37 28 0 24 18 48 83 ] 313 +MM_W Use_TimeoutStarverX [11 34 20 35 0 1 10 2 ] 113 +MM_W Use_TimeoutStarverS [23 69 36 72 0 1 20 0 ] 221 +MM_W Use_TimeoutNoStarvers [7073 7006 7055 7000 7096 7096 7082 7105 ] 56513 +MM_W Use_TimeoutNoStarvers_NoMig [0 0 0 0 0 0 0 0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3191 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 273 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 439 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5569 -IM Persistent_GETS 10313 -IM Own_Lock_or_Unlock 3193 -IM Request_Timeout 2198 +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM Atomic [0 0 0 0 0 0 0 0 ] 0 +IM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IM Data_Owner [1 0 0 0 0 0 0 0 ] 1 +IM Data_All_Tokens [2493 2548 2551 2497 2533 2477 2452 2451 ] 20002 +IM Ack [0 1 0 0 0 0 0 1 ] 2 +IM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETX [224 232 220 252 256 225 234 210 ] 1853 +IM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETS [418 424 433 400 434 435 405 378 ] 3327 +IM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Persistent_GETX [4262 4428 4420 4259 4297 4187 4206 4255 ] 34314 +IM Persistent_GETS [8050 8224 8108 7972 8058 7980 7667 7734 ] 63793 +IM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM Own_Lock_or_Unlock [1916 1881 2010 1900 2533 2476 2142 2231 ] 17089 +IM Request_Timeout [1575 1584 1634 1629 1553 1499 1532 1535 ] 12541 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 6 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM Atomic [0 0 0 0 0 0 0 0 ] 0 +SM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +SM Data_Owner [0 0 0 0 0 0 0 0 ] 0 +SM Data_All_Tokens [3 0 2 3 0 0 1 4 ] 13 +SM Ack [0 0 0 0 0 0 0 0 ] 0 +SM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETX [1 1 1 0 4 2 4 1 ] 14 +SM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETS [0 0 0 0 0 0 0 1 ] 1 +SM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 +SM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 10 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 4 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 2 -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM Atomic [0 0 0 0 0 0 0 0 ] 0 +OM L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM Data_Shared [0 0 0 0 0 0 0 0 ] 0 +OM Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +OM Ack [0 0 0 0 0 0 0 0 ] 0 +OM Ack_All_Tokens [2 0 5 0 0 2 2 2 ] 13 +OM Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETX [1 0 4 0 0 1 2 2 ] 10 +OM Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Persistent_GETX [1 0 0 0 0 0 0 0 ] 1 +OM Persistent_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +OM Own_Lock_or_Unlock [0 0 0 0 0 1 1 1 ] 3 +OM Request_Timeout [0 0 0 0 0 0 0 0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 19 -IS Data_All_Tokens 5705 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 460 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 816 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10015 -IS Persistent_GETS 18534 -IS Own_Lock_or_Unlock 5746 -IS Request_Timeout 3986 +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS Atomic [0 0 0 0 0 0 0 0 ] 0 +IS L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IS Data_Owner [5 2 7 1 2 2 3 5 ] 27 +IS Data_All_Tokens [4637 4588 4580 4638 4604 4660 4683 4682 ] 37072 +IS Ack [0 0 0 0 0 0 0 0 ] 0 +IS Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETX [371 394 453 404 440 401 384 408 ] 3255 +IS Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETS [776 747 755 739 761 756 789 750 ] 6073 +IS Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Persistent_GETX [8009 7908 7890 7968 7783 8047 8077 8050 ] 63732 +IS Persistent_GETS [14815 14743 14645 14762 14499 14671 14936 15023 ] 118094 +IS Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS Own_Lock_or_Unlock [3616 3273 3597 3475 4609 4668 4151 4306 ] 31695 +IS Request_Timeout [2911 2786 2887 3008 2850 2936 3006 2961 ] 23345 -I_L Load 5716 -I_L Ifetch 0 <-- -I_L Store 3183 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 1 -I_L Persistent_GETS 2 -I_L Own_Lock_or_Unlock 0 <-- +I_L Load [4641 4588 4586 4638 4604 4662 4685 4685 ] 37089 +I_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +I_L Store [2493 2547 2549 2498 2529 2474 2448 2449 ] 19987 +I_L Atomic [0 0 0 0 0 0 0 0 ] 0 +I_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +I_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +I_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +I_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +I_L Ack [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Persistent_GETX [52 123 118 130 3 0 69 2 ] 497 +I_L Persistent_GETS [82 228 215 280 0 2 150 3 ] 960 +I_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +I_L Own_Lock_or_Unlock [0 0 0 0 0 0 0 0 ] 0 -S_L Load 19 -S_L Ifetch 0 <-- -S_L Store 9 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 4 +S_L Load [4 3 6 0 12 4 4 8 ] 41 +S_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +S_L Store [3 0 3 3 2 2 5 4 ] 22 +S_L Atomic [0 0 0 0 0 0 0 0 ] 0 +S_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +S_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +S_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +S_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +S_L Ack [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +S_L Persistent_GETS [0 0 0 1 0 0 0 0 ] 1 +S_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +S_L Own_Lock_or_Unlock [1 1 0 0 2 0 0 1 ] 5 -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6647 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12472 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2218 -IM_L Persistent_GETS 4302 -IM_L Own_Lock_or_Unlock 19065 -IM_L Request_Timeout 1174 +IM_L Load [0 0 0 0 0 0 0 0 ] 0 +IM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM_L Store [0 0 0 0 0 0 0 0 ] 0 +IM_L Atomic [0 0 0 0 0 0 0 0 ] 0 +IM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +IM_L Data_All_Tokens [1 0 0 0 0 0 1 0 ] 2 +IM_L Ack [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETX [5327 5332 5228 5204 5356 5182 5185 5148 ] 41962 +IM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETS [9633 9957 10074 9775 9839 9670 9525 9555 ] 78028 +IM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IM_L Persistent_GETX [2034 2164 2204 2138 2021 1899 2110 2009 ] 16579 +IM_L Persistent_GETS [3881 3885 3969 4085 3669 3475 3921 3650 ] 30535 +IM_L Own_Lock_or_Unlock [14805 15199 15077 14729 14884 14641 14320 14438 ] 118093 +IM_L Request_Timeout [958 965 917 896 980 992 921 926 ] 7555 -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 9 -SM_L Request_Timeout 0 <-- +SM_L Load [0 0 0 0 0 0 0 0 ] 0 +SM_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM_L Store [0 0 0 0 0 0 0 0 ] 0 +SM_L Atomic [0 0 0 0 0 0 0 0 ] 0 +SM_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +SM_L Data_All_Tokens [0 0 0 0 0 0 0 0 ] 0 +SM_L Ack [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETS [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Persistent_GETX [0 0 0 0 0 0 0 0 ] 0 +SM_L Persistent_GETS [0 0 0 0 0 0 1 0 ] 1 +SM_L Persistent_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +SM_L Own_Lock_or_Unlock [3 0 3 3 2 2 5 4 ] 22 +SM_L Request_Timeout [0 0 0 0 0 0 0 0 ] 0 -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12134 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22172 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4204 -IS_L Persistent_GETS 7371 -IS_L Own_Lock_or_Unlock 34263 -IS_L Request_Timeout 2011 +IS_L Load [0 0 0 0 0 0 0 0 ] 0 +IS_L Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS_L Store [0 0 0 0 0 0 0 0 ] 0 +IS_L Atomic [0 0 0 0 0 0 0 0 ] 0 +IS_L L1_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_Shared [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_Owner [0 0 0 0 0 0 0 0 ] 0 +IS_L Data_All_Tokens [2 0 0 1 0 0 0 0 ] 3 +IS_L Ack [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_GETX [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETX [9727 9640 9664 9801 9606 9855 9877 9886 ] 78056 +IS_L Transient_GETS [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETS [18133 17890 17855 18036 18019 18109 18232 18226 ] 144500 +IS_L Transient_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 0 0 0 0 0 0 0 ] 0 +IS_L Persistent_GETX [4018 3914 3905 4159 3695 3711 3790 3711 ] 30903 +IS_L Persistent_GETS [7166 7377 7207 7462 6993 6794 7049 6767 ] 56815 +IS_L Own_Lock_or_Unlock [27462 27238 27120 27366 26885 27380 27697 27757 ] 218905 +IS_L Request_Timeout [1820 1835 1725 1694 1755 1728 1687 1757 ] 14001 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.icache + system.l1_cntrl1.sequencer.icache_total_misses: 0 + system.l1_cntrl1.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.icache_total_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.dcache + system.l1_cntrl1.sequencer.dcache_total_misses: 7142 + system.l1_cntrl1.sequencer.dcache_total_demand_misses: 7142 + system.l1_cntrl1.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl1.sequencer.dcache_request_type_LD: 65.2898% + system.l1_cntrl1.sequencer.dcache_request_type_ST: 34.7102% - --- L1Cache 1 --- + system.l1_cntrl1.sequencer.dcache_access_mode_type_SupervisorMode: 7142 100% + +Cache Stats: system.l1_cntrl2.sequencer.icache + system.l1_cntrl2.sequencer.icache_total_misses: 0 + system.l1_cntrl2.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.icache_total_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl2.sequencer.dcache + system.l1_cntrl2.sequencer.dcache_total_misses: 7143 + system.l1_cntrl2.sequencer.dcache_total_demand_misses: 7143 + system.l1_cntrl2.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl2.sequencer.dcache_request_type_LD: 65.6167% + system.l1_cntrl2.sequencer.dcache_request_type_ST: 34.3833% + + system.l1_cntrl2.sequencer.dcache_access_mode_type_SupervisorMode: 7143 100% + +Cache Stats: system.l1_cntrl3.sequencer.icache + system.l1_cntrl3.sequencer.icache_total_misses: 0 + system.l1_cntrl3.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.icache_total_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl3.sequencer.dcache + system.l1_cntrl3.sequencer.dcache_total_misses: 7146 + system.l1_cntrl3.sequencer.dcache_total_demand_misses: 7146 + system.l1_cntrl3.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl3.sequencer.dcache_request_type_LD: 65.6171% + system.l1_cntrl3.sequencer.dcache_request_type_ST: 34.3829% + + system.l1_cntrl3.sequencer.dcache_access_mode_type_SupervisorMode: 7146 100% + +Cache Stats: system.l1_cntrl4.sequencer.icache + system.l1_cntrl4.sequencer.icache_total_misses: 0 + system.l1_cntrl4.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.icache_total_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl4.sequencer.dcache + system.l1_cntrl4.sequencer.dcache_total_misses: 7145 + system.l1_cntrl4.sequencer.dcache_total_demand_misses: 7145 + system.l1_cntrl4.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl4.sequencer.dcache_request_type_LD: 65.0245% + system.l1_cntrl4.sequencer.dcache_request_type_ST: 34.9755% + + system.l1_cntrl4.sequencer.dcache_access_mode_type_SupervisorMode: 7145 100% + +Cache Stats: system.l1_cntrl5.sequencer.icache + system.l1_cntrl5.sequencer.icache_total_misses: 0 + system.l1_cntrl5.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.icache_total_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl5.sequencer.dcache + system.l1_cntrl5.sequencer.dcache_total_misses: 7140 + system.l1_cntrl5.sequencer.dcache_total_demand_misses: 7140 + system.l1_cntrl5.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl5.sequencer.dcache_request_type_LD: 64.2997% + system.l1_cntrl5.sequencer.dcache_request_type_ST: 35.7003% + + system.l1_cntrl5.sequencer.dcache_access_mode_type_SupervisorMode: 7140 100% + +Cache Stats: system.l1_cntrl6.sequencer.icache + system.l1_cntrl6.sequencer.icache_total_misses: 0 + system.l1_cntrl6.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.icache_total_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl6.sequencer.dcache + system.l1_cntrl6.sequencer.dcache_total_misses: 7147 + system.l1_cntrl6.sequencer.dcache_total_demand_misses: 7147 + system.l1_cntrl6.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl6.sequencer.dcache_request_type_LD: 64.2088% + system.l1_cntrl6.sequencer.dcache_request_type_ST: 35.7912% + + system.l1_cntrl6.sequencer.dcache_access_mode_type_SupervisorMode: 7147 100% + +Cache Stats: system.l1_cntrl7.sequencer.icache + system.l1_cntrl7.sequencer.icache_total_misses: 0 + system.l1_cntrl7.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.icache_total_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_hw_prefetches: 0 + + +Cache Stats: system.l1_cntrl7.sequencer.dcache + system.l1_cntrl7.sequencer.dcache_total_misses: 7142 + system.l1_cntrl7.sequencer.dcache_total_demand_misses: 7142 + system.l1_cntrl7.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_hw_prefetches: 0 + + system.l1_cntrl7.sequencer.dcache_request_type_LD: 64.9818% + system.l1_cntrl7.sequencer.dcache_request_type_ST: 35.0182% + + system.l1_cntrl7.sequencer.dcache_access_mode_type_SupervisorMode: 7142 100% + +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 57146 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 57146 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 + + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 64.9442% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 35.0558% + + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 57146 100% + + --- L2Cache --- - Event Counts - -Load 100000 -Ifetch 0 -Store 53572 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 16 -Data_All_Tokens 8907 -Ack 1 -Ack_All_Tokens 6 -Transient_GETX 0 -Transient_Local_GETX 22102 -Transient_GETS 0 -Transient_Local_GETS 40413 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25285 -Persistent_GETS 46227 -Own_Lock_or_Unlock 71112 -Request_Timeout 9838 -Use_TimeoutStarverX 9 -Use_TimeoutStarverS 21 -Use_TimeoutNoStarvers 8883 +L1_GETS [37113 ] 37113 +L1_GETS_Last_Token [0 ] 0 +L1_GETX [20033 ] 20033 +L1_INV [57090 ] 57090 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [0 ] 0 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [0 ] 0 +Writeback_All_Tokens [0 ] 0 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [23704 ] 23704 +Persistent_GETS [43849 ] 43849 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [46654 ] 46654 - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- +NP L1_GETS [24 ] 24 +NP L1_GETX [30 ] 30 +NP L1_INV [14 ] 14 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [0 ] 0 +NP Writeback_All_Tokens [0 ] 0 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [46654 ] 46654 -I Load 9 -I Ifetch 0 <-- -I Store 2 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 3 +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [0 ] 0 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [0 ] 0 +I Writeback_All_Tokens [0 ] 0 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S Load 2 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [0 ] 0 +S L1_GETX [0 ] 0 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [0 ] 0 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O Load 13 -O Ifetch 0 <-- -O Store 6 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 10 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [0 ] 0 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [0 ] 0 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M Load 93 -M Ifetch 0 <-- -M Store 64 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 6 -M Persistent_GETS 11 -M Own_Lock_or_Unlock 57 +M L1_GETS [0 ] 0 +M L1_GETX [0 ] 0 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -MM Load 39210 -MM Ifetch 0 <-- -MM Store 21060 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3114 -MM Persistent_GETS 5751 -MM Own_Lock_or_Unlock 8567 +I_L L1_GETS [37089 ] 37089 +I_L L1_GETX [20003 ] 20003 +I_L L1_INV [57076 ] 57076 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [0 ] 0 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [0 ] 0 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [23704 ] 23704 +I_L Persistent_GETS [43849 ] 43849 +I_L Own_Lock_or_Unlock [0 ] 0 -M_W Load 10349 -M_W Ifetch 0 <-- -M_W Store 5722 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1545 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2943 -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 3 -M_W Own_Lock_or_Unlock 28 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 81 +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -MM_W Load 44502 -MM_W Ifetch 0 <-- -MM_W Store 23617 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 909 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1723 -MM_W Persistent_GETX 8 -MM_W Persistent_GETS 17 -MM_W Own_Lock_or_Unlock 204 -MM_W Use_TimeoutStarverX 8 -MM_W Use_TimeoutStarverS 20 -MM_W Use_TimeoutNoStarvers 8802 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3094 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 276 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 403 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5339 -IM Persistent_GETS 9988 -IM Own_Lock_or_Unlock 3091 -IM Request_Timeout 2203 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 7 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 4 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 6 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 3 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 1 -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 16 -IS Data_All_Tokens 5804 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 494 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 774 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10327 -IS Persistent_GETS 18778 -IS Own_Lock_or_Unlock 5808 -IS Request_Timeout 4283 - -I_L Load 5812 -I_L Ifetch 0 <-- -I_L Store 3088 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 3 -I_L Persistent_GETS 12 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 10 -S_L Ifetch 0 <-- -S_L Store 10 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 2 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6495 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12038 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2303 -IM_L Persistent_GETS 4177 -IM_L Own_Lock_or_Unlock 18413 -IM_L Request_Timeout 1186 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 10 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 1 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12365 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22531 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4185 -IS_L Persistent_GETS 7489 -IS_L Own_Lock_or_Unlock 34916 -IS_L Request_Timeout 2166 - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 2 --- - - Event Counts - -Load 97643 -Ifetch 0 -Store 52893 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 17 -Data_All_Tokens 8906 -Ack 0 -Ack_All_Tokens 5 -Transient_GETX 0 -Transient_Local_GETX 22043 -Transient_GETS 0 -Transient_Local_GETS 40473 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25456 -Persistent_GETS 46651 -Own_Lock_or_Unlock 70517 -Request_Timeout 9275 -Use_TimeoutStarverX 56 -Use_TimeoutStarverS 71 -Use_TimeoutNoStarvers 8784 - - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 10 -I Ifetch 0 <-- -I Store 3 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 4 - -S Load 5 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 2 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 15 -O Ifetch 0 <-- -O Store 5 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 11 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 12 - -M Load 132 -M Ifetch 0 <-- -M Store 98 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 8 -M Persistent_GETS 8 -M Own_Lock_or_Unlock 72 - -MM Load 37025 -MM Ifetch 0 <-- -MM Store 20285 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3092 -MM Persistent_GETS 5676 -MM Own_Lock_or_Unlock 8197 - -M_W Load 10300 -M_W Ifetch 0 <-- -M_W Store 5629 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1553 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2883 -M_W Persistent_GETX 1 -M_W Persistent_GETS 4 -M_W Own_Lock_or_Unlock 5 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 114 - -MM_W Load 44391 -MM_W Ifetch 0 <-- -MM_W Store 23713 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 954 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1765 -MM_W Persistent_GETX 53 -MM_W Persistent_GETS 65 -MM_W Own_Lock_or_Unlock 81 -MM_W Use_TimeoutStarverX 56 -MM_W Use_TimeoutStarverS 70 -MM_W Use_TimeoutNoStarvers 8670 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 1 -IM Data_All_Tokens 3154 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 224 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 423 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5527 -IM Persistent_GETS 10268 -IM Own_Lock_or_Unlock 3022 -IM Request_Timeout 2254 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 6 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 1 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 5 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 5 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 1 -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 16 -IS Data_All_Tokens 5742 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 500 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 764 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10135 -IS Persistent_GETS 18799 -IS Own_Lock_or_Unlock 5489 -IS Request_Timeout 3965 - -I_L Load 5750 -I_L Ifetch 0 <-- -I_L Store 3152 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 123 -I_L Persistent_GETS 171 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 14 -S_L Ifetch 0 <-- -S_L Store 6 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 3 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 2 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6723 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12190 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2287 -IM_L Persistent_GETS 4214 -IM_L Own_Lock_or_Unlock 18945 -IM_L Request_Timeout 1051 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 6 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12070 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22448 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4229 -IS_L Persistent_GETS 7442 -IS_L Own_Lock_or_Unlock 34681 -IS_L Request_Timeout 2005 - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 3 --- - - Event Counts - -Load 97533 -Ifetch 0 -Store 52364 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 13 -Data_All_Tokens 8914 -Ack 0 -Ack_All_Tokens 3 -Transient_GETX 0 -Transient_Local_GETX 22082 -Transient_GETS 0 -Transient_Local_GETS 40431 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25737 -Persistent_GETS 47104 -Own_Lock_or_Unlock 69783 -Request_Timeout 9632 -Use_TimeoutStarverX 49 -Use_TimeoutStarverS 101 -Use_TimeoutNoStarvers 8767 - - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 7 -I Ifetch 0 <-- -I Store 5 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 5 - -S Load 7 -S Ifetch 0 <-- -S Store 5 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 2 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 9 -O Ifetch 0 <-- -O Store 3 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 10 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 8 - -M Load 118 -M Ifetch 0 <-- -M Store 59 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 12 -M Persistent_GETS 18 -M Own_Lock_or_Unlock 64 - -MM Load 36793 -MM Ifetch 0 <-- -MM Store 19758 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3077 -MM Persistent_GETS 5660 -MM Own_Lock_or_Unlock 8127 - -M_W Load 10555 -M_W Ifetch 0 <-- -M_W Store 5696 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1567 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2900 -M_W Persistent_GETX 3 -M_W Persistent_GETS 5 -M_W Own_Lock_or_Unlock 9 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 89 - -MM_W Load 44219 -MM_W Ifetch 0 <-- -MM_W Store 23722 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 940 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1718 -MM_W Persistent_GETX 45 -MM_W Persistent_GETS 91 -MM_W Own_Lock_or_Unlock 175 -MM_W Use_TimeoutStarverX 48 -MM_W Use_TimeoutStarverS 99 -MM_W Use_TimeoutNoStarvers 8678 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3110 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 239 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 407 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5351 -IM Persistent_GETS 10228 -IM Own_Lock_or_Unlock 2723 -IM Request_Timeout 2247 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 14 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 4 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 3 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 1 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 13 -IS Data_All_Tokens 5784 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 483 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 809 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10327 -IS Persistent_GETS 18763 -IS Own_Lock_or_Unlock 5094 -IS Request_Timeout 4257 - -I_L Load 5794 -I_L Ifetch 0 <-- -I_L Store 3103 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 107 -I_L Persistent_GETS 171 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 29 -S_L Ifetch 0 <-- -S_L Store 13 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 7 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 2 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6465 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12190 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2323 -IM_L Persistent_GETS 4335 -IM_L Own_Lock_or_Unlock 18680 -IM_L Request_Timeout 1090 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 1 -SM_L Own_Lock_or_Unlock 13 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 4 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12371 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22406 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4492 -IS_L Persistent_GETS 7828 -IS_L Own_Lock_or_Unlock 34878 -IS_L Request_Timeout 2038 - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 4 --- - - Event Counts - -Load 98571 -Ifetch 0 -Store 53174 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 15 -Data_All_Tokens 8907 -Ack 1 -Ack_All_Tokens 9 -Transient_GETX 0 -Transient_Local_GETX 22035 -Transient_GETS 0 -Transient_Local_GETS 40477 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25723 -Persistent_GETS 47221 -Own_Lock_or_Unlock 69680 -Request_Timeout 9073 -Use_TimeoutStarverX 45 -Use_TimeoutStarverS 64 -Use_TimeoutNoStarvers 8807 - - - Transitions - -NP Load 0 <-- -NP Ifetch 0 <-- -NP Store 2 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 5 -I Ifetch 0 <-- -I Store 2 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 - -S Load 5 -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 1 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 12 -O Ifetch 0 <-- -O Store 9 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 6 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 13 - -M Load 162 -M Ifetch 0 <-- -M Store 90 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 10 -M Persistent_GETS 15 -M Own_Lock_or_Unlock 81 - -MM Load 37823 -MM Ifetch 0 <-- -MM Store 20386 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3131 -MM Persistent_GETS 5651 -MM Own_Lock_or_Unlock 8286 - -M_W Load 10724 -M_W Ifetch 0 <-- -M_W Store 5626 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1492 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2942 -M_W Persistent_GETX 1 -M_W Persistent_GETS 2 -M_W Own_Lock_or_Unlock 5 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 115 - -MM_W Load 44076 -MM_W Ifetch 0 <-- -MM_W Store 23896 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 938 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1714 -MM_W Persistent_GETX 42 -MM_W Persistent_GETS 58 -MM_W Own_Lock_or_Unlock 118 -MM_W Use_TimeoutStarverX 45 -MM_W Use_TimeoutStarverS 64 -MM_W Use_TimeoutNoStarvers 8692 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3153 -IM Ack 1 -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 249 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 476 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5499 -IM Persistent_GETS 10272 -IM Own_Lock_or_Unlock 2790 -IM Request_Timeout 2276 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 9 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 5 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 9 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 3 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 15 -IS Data_All_Tokens 5739 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 480 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 773 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10010 -IS Persistent_GETS 18635 -IS Own_Lock_or_Unlock 5061 -IS Request_Timeout 3939 - -I_L Load 5752 -I_L Ifetch 0 <-- -I_L Store 3149 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 91 -I_L Persistent_GETS 129 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 12 -S_L Ifetch 0 <-- -S_L Store 13 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 1 -S_L Own_Lock_or_Unlock 2 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 4 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6730 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12189 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2467 -IM_L Persistent_GETS 4316 -IM_L Own_Lock_or_Unlock 18915 -IM_L Request_Timeout 976 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 1 -SM_L Own_Lock_or_Unlock 13 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12131 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22383 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4472 -IS_L Persistent_GETS 8141 -IS_L Own_Lock_or_Unlock 34394 -IS_L Request_Timeout 1882 - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 5 --- - - Event Counts - -Load 98263 -Ifetch 0 -Store 52643 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 14 -Data_All_Tokens 8907 -Ack 0 -Ack_All_Tokens 8 -Transient_GETX 0 -Transient_Local_GETX 22057 -Transient_GETS 0 -Transient_Local_GETS 40457 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 25924 -Persistent_GETS 47474 -Own_Lock_or_Unlock 69226 -Request_Timeout 9210 -Use_TimeoutStarverX 95 -Use_TimeoutStarverS 180 -Use_TimeoutNoStarvers 8640 - - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 1 -I Ifetch 0 <-- -I Store 7 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 - -S Load 6 -S Ifetch 0 <-- -S Store 2 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 2 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 14 -O Ifetch 0 <-- -O Store 8 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 6 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 12 - -M Load 146 -M Ifetch 0 <-- -M Store 82 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 10 -M Persistent_GETS 14 -M Own_Lock_or_Unlock 78 - -MM Load 37545 -MM Ifetch 0 <-- -MM Store 19800 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 2939 -MM Persistent_GETS 5677 -MM Own_Lock_or_Unlock 8010 - -M_W Load 10319 -M_W Ifetch 0 <-- -M_W Store 5652 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1615 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2853 -M_W Persistent_GETX 6 -M_W Persistent_GETS 10 -M_W Own_Lock_or_Unlock 3 -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 106 - -MM_W Load 44434 -MM_W Ifetch 0 <-- -MM_W Store 23955 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 922 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1731 -MM_W Persistent_GETX 89 -MM_W Persistent_GETS 167 -MM_W Own_Lock_or_Unlock 63 -MM_W Use_TimeoutStarverX 94 -MM_W Use_TimeoutStarverS 178 -MM_W Use_TimeoutNoStarvers 8534 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3137 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 242 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 440 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5536 -IM Persistent_GETS 10252 -IM Own_Lock_or_Unlock 2638 -IM Request_Timeout 2133 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 8 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 1 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 8 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 6 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 14 -IS Data_All_Tokens 5759 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 469 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 783 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10207 -IS Persistent_GETS 18677 -IS Own_Lock_or_Unlock 4838 -IS Request_Timeout 3962 - -I_L Load 5775 -I_L Ifetch 0 <-- -I_L Store 3124 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 124 -I_L Persistent_GETS 249 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 22 -S_L Ifetch 0 <-- -S_L Store 12 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 4 -S_L Own_Lock_or_Unlock 4 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6599 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12205 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2385 -IM_L Persistent_GETS 4323 -IM_L Own_Lock_or_Unlock 18911 -IM_L Request_Timeout 1095 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 2 -SM_L Own_Lock_or_Unlock 12 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 2 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12190 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22444 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4628 -IS_L Persistent_GETS 8099 -IS_L Own_Lock_or_Unlock 34655 -IS_L Request_Timeout 2020 - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 6 --- - - Event Counts - -Load 98465 -Ifetch 0 -Store 52806 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 12 -Data_All_Tokens 8905 -Ack 0 -Ack_All_Tokens 4 -Transient_GETX 0 -Transient_Local_GETX 22067 -Transient_GETS 0 -Transient_Local_GETS 40455 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 26105 -Persistent_GETS 47891 -Own_Lock_or_Unlock 68628 -Request_Timeout 9116 -Use_TimeoutStarverX 83 -Use_TimeoutStarverS 130 -Use_TimeoutNoStarvers 8696 - - - Transitions - -NP Load 2 -NP Ifetch 0 <-- -NP Store 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 8 -I Ifetch 0 <-- -I Store 4 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 2 - -S Load 4 -S Ifetch 0 <-- -S Store 4 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 4 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 17 -O Ifetch 0 <-- -O Store 4 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 8 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 10 - -M Load 180 -M Ifetch 0 <-- -M Store 84 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 9 -M Persistent_GETS 10 -M Own_Lock_or_Unlock 73 - -MM Load 37625 -MM Ifetch 0 <-- -MM Store 20185 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 3113 -MM Persistent_GETS 5564 -MM Own_Lock_or_Unlock 8005 - -M_W Load 10787 -M_W Ifetch 0 <-- -M_W Store 5661 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1617 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2872 -M_W Persistent_GETX 2 -M_W Persistent_GETS 6 -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 2 -M_W Use_TimeoutNoStarvers 103 - -MM_W Load 44046 -MM_W Ifetch 0 <-- -MM_W Store 23732 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 944 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1688 -MM_W Persistent_GETX 81 -MM_W Persistent_GETS 120 -MM_W Own_Lock_or_Unlock 32 -MM_W Use_TimeoutStarverX 83 -MM_W Use_TimeoutStarverS 128 -MM_W Use_TimeoutNoStarvers 8593 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3136 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 272 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 429 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5413 -IM Persistent_GETS 10166 -IM Own_Lock_or_Unlock 2512 -IM Request_Timeout 2230 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 2 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 4 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 1 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 12 -IS Data_All_Tokens 5763 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 453 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 781 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10124 -IS Persistent_GETS 18788 -IS Own_Lock_or_Unlock 4600 -IS Request_Timeout 4029 - -I_L Load 5769 -I_L Ifetch 0 <-- -I_L Store 3128 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 155 -I_L Persistent_GETS 290 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 27 -S_L Ifetch 0 <-- -S_L Store 4 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 6 -S_L Own_Lock_or_Unlock 8 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 1 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6488 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12321 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2578 -IM_L Persistent_GETS 4664 -IM_L Own_Lock_or_Unlock 18705 -IM_L Request_Timeout 985 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 4 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 3 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12274 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22364 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4630 -IS_L Persistent_GETS 8277 -IS_L Own_Lock_or_Unlock 34677 -IS_L Request_Timeout 1872 - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L1Cache 7 --- - - Event Counts - -Load 97834 -Ifetch 0 -Store 52922 -L1_Replacement 0 -Data_Shared 0 -Data_Owner 12 -Data_All_Tokens 8914 -Ack 0 -Ack_All_Tokens 7 -Transient_GETX 0 -Transient_Local_GETX 22087 -Transient_GETS 0 -Transient_Local_GETS 40424 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 26278 -Persistent_GETS 48035 -Own_Lock_or_Unlock 68312 -Request_Timeout 9299 -Use_TimeoutStarverX 114 -Use_TimeoutStarverS 189 -Use_TimeoutNoStarvers 8618 - - - Transitions - -NP Load 1 -NP Ifetch 0 <-- -NP Store 1 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 0 <-- - -I Load 6 -I Ifetch 0 <-- -I Store 1 -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 1 - -S Load 6 -S Ifetch 0 <-- -S Store 4 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 2 -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O Load 8 -O Ifetch 0 <-- -O Store 7 -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 5 -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 11 - -M Load 162 -M Ifetch 0 <-- -M Store 84 -M L1_Replacement 0 <-- -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 4 -M Persistent_GETS 19 -M Own_Lock_or_Unlock 67 - -MM Load 36988 -MM Ifetch 0 <-- -MM Store 20238 -MM L1_Replacement 0 <-- -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 2995 -MM Persistent_GETS 5599 -MM Own_Lock_or_Unlock 7907 - -M_W Load 10805 -M_W Ifetch 0 <-- -M_W Store 5688 -M_W L1_Replacement 0 <-- -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 1572 -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 2937 -M_W Persistent_GETX 7 -M_W Persistent_GETS 6 -M_W Own_Lock_or_Unlock 0 <-- -M_W Use_TimeoutStarverX 1 -M_W Use_TimeoutStarverS 1 -M_W Use_TimeoutNoStarvers 107 - -MM_W Load 44028 -MM_W Ifetch 0 <-- -MM_W Store 23788 -MM_W L1_Replacement 0 <-- -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 967 -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 1650 -MM_W Persistent_GETX 107 -MM_W Persistent_GETS 173 -MM_W Own_Lock_or_Unlock 0 <-- -MM_W Use_TimeoutStarverX 113 -MM_W Use_TimeoutStarverS 188 -MM_W Use_TimeoutNoStarvers 8511 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 0 <-- -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 3101 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 259 -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 412 -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 5450 -IM Persistent_GETS 10069 -IM Own_Lock_or_Unlock 2398 -IM Request_Timeout 2209 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 12 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 6 -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 3 -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 7 -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 4 -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 0 <-- -IS Data_Shared 0 <-- -IS Data_Owner 12 -IS Data_All_Tokens 5791 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 471 -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 784 -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 10205 -IS Persistent_GETS 18777 -IS Own_Lock_or_Unlock 4518 -IS Request_Timeout 4152 - -I_L Load 5803 -I_L Ifetch 0 <-- -I_L Store 3097 -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 156 -I_L Persistent_GETS 291 -I_L Own_Lock_or_Unlock 0 <-- - -S_L Load 27 -S_L Ifetch 0 <-- -S_L Store 14 -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 5 -S_L Own_Lock_or_Unlock 6 - -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 4 -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 6464 -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 12152 -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 2631 -IM_L Persistent_GETS 4457 -IM_L Own_Lock_or_Unlock 18612 -IM_L Request_Timeout 1035 - -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 2 -SM_L Own_Lock_or_Unlock 14 -SM_L Request_Timeout 0 <-- - -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 6 -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 12337 -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 22486 -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 4723 -IS_L Persistent_GETS 8637 -IS_L Own_Lock_or_Unlock 34778 -IS_L Request_Timeout 1903 - -Cache Stats: system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links8.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - - --- L2Cache 0 --- - - Event Counts - -L1_GETS 46234 -L1_GETS_Last_Token 0 -L1_GETX 25211 -L1_INV 71275 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 0 -Writeback_Tokens 0 -Writeback_Shared_Data 0 -Writeback_All_Tokens 0 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 29383 -Persistent_GETS 53856 -Own_Lock_or_Unlock 59385 - - - Transitions - -NP L1_GETS 63 -NP L1_GETX 127 -NP L1_INV 80 -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 0 <-- -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 0 <-- -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 59385 - -I L1_GETS 0 <-- -I L1_GETS_Last_Token 0 <-- -I L1_GETX 0 <-- -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 0 <-- -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 0 <-- -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- - -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- - -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 0 <-- -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 0 <-- -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- - -M L1_GETS 0 <-- -M L1_GETX 0 <-- -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 0 <-- - -I_L L1_GETS 46171 -I_L L1_GETX 25084 -I_L L1_INV 71195 -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 0 <-- -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 29383 -I_L Persistent_GETS 53856 -I_L Own_Lock_or_Unlock 0 <-- - -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- - -Memory controller: system.ruby.network.topology.ext_links9.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -3197,215 +1053,278 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 25384 -GETS 46466 -Lockdown 83239 -Unlockdown 59385 -Own_Lock_or_Unlock 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack_Owner 0 -Ack_Owner_All_Tokens 0 -Tokens 0 -Ack_All_Tokens 0 -Request_Timeout 0 -Memory_Data 2 -Memory_Ack 0 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [20057 ] 20057 +GETS [37494 ] 37494 +Lockdown [67553 ] 67553 +Unlockdown [46654 ] 46654 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack_Owner [0 ] 0 +Ack_Owner_All_Tokens [0 ] 0 +Tokens [0 ] 0 +Ack_All_Tokens [0 ] 0 +Request_Timeout [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 2 -O GETS 0 <-- -O Lockdown 0 <-- -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- +O GETX [1 ] 1 +O GETS [1 ] 1 +O Lockdown [0 ] 0 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX 184 -NO GETS 63 -NO Lockdown 59387 -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 0 <-- -NO Data_All_Tokens 0 <-- -NO Ack_Owner 0 <-- -NO Ack_Owner_All_Tokens 0 <-- -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NO GETX [45 ] 45 +NO GETS [23 ] 23 +NO Lockdown [46655 ] 46655 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [0 ] 0 +NO Data_All_Tokens [0 ] 0 +NO Ack_Owner [0 ] 0 +NO Ack_Owner_All_Tokens [0 ] 0 +NO Tokens [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -L GETX 25025 -L GETS 46171 -L Lockdown 23852 -L Unlockdown 59385 -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 0 <-- -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- +L GETX [19987 ] 19987 +L GETS [37089 ] 37089 +L Lockdown [20898 ] 20898 +L Unlockdown [46654 ] 46654 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [0 ] 0 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [0 ] 0 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W Lockdown 0 <-- -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W Lockdown [0 ] 0 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [0 ] 0 +O_W Memory_Ack [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX 0 <-- -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 0 <-- -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 0 <-- -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [0 ] 0 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [0 ] 0 +L_O_W Memory_Ack [0 ] 0 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 0 <-- -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [0 ] 0 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX 173 -NO_W GETS 232 -NO_W Lockdown 0 <-- -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 2 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- +NO_W GETX [24 ] 24 +NO_W GETS [381 ] 381 +NO_W Lockdown [0 ] 0 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [2 ] 2 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu1: completed 10000 read accesses @320533 -system.cpu0: completed 10000 read accesses @324255 -system.cpu5: completed 10000 read accesses @329816 -system.cpu4: completed 10000 read accesses @330370 -system.cpu2: completed 10000 read accesses @330850 -system.cpu3: completed 10000 read accesses @330898 -system.cpu6: completed 10000 read accesses @330981 -system.cpu7: completed 10000 read accesses @332669 -system.cpu1: completed 20000 read accesses @645951 -system.cpu6: completed 20000 read accesses @654684 -system.cpu0: completed 20000 read accesses @655122 -system.cpu5: completed 20000 read accesses @655139 -system.cpu4: completed 20000 read accesses @658112 -system.cpu7: completed 20000 read accesses @659630 -system.cpu3: completed 20000 read accesses @662399 -system.cpu2: completed 20000 read accesses @662745 -system.cpu1: completed 30000 read accesses @971498 -system.cpu0: completed 30000 read accesses @979665 -system.cpu6: completed 30000 read accesses @980753 -system.cpu4: completed 30000 read accesses @986046 -system.cpu5: completed 30000 read accesses @986992 -system.cpu7: completed 30000 read accesses @990004 -system.cpu2: completed 30000 read accesses @992746 -system.cpu3: completed 30000 read accesses @994289 -system.cpu1: completed 40000 read accesses @1295713 -system.cpu0: completed 40000 read accesses @1304844 -system.cpu6: completed 40000 read accesses @1311609 -system.cpu4: completed 40000 read accesses @1313210 -system.cpu5: completed 40000 read accesses @1315669 -system.cpu7: completed 40000 read accesses @1321203 -system.cpu3: completed 40000 read accesses @1325768 -system.cpu2: completed 40000 read accesses @1327431 -system.cpu1: completed 50000 read accesses @1620139 -system.cpu0: completed 50000 read accesses @1624207 -system.cpu6: completed 50000 read accesses @1642053 -system.cpu5: completed 50000 read accesses @1643779 -system.cpu4: completed 50000 read accesses @1647677 -system.cpu7: completed 50000 read accesses @1653016 -system.cpu3: completed 50000 read accesses @1659224 -system.cpu2: completed 50000 read accesses @1659858 -system.cpu1: completed 60000 read accesses @1944324 -system.cpu0: completed 60000 read accesses @1947039 -system.cpu5: completed 60000 read accesses @1971722 -system.cpu6: completed 60000 read accesses @1971958 -system.cpu4: completed 60000 read accesses @1978467 -system.cpu3: completed 60000 read accesses @1984371 -system.cpu7: completed 60000 read accesses @1986116 -system.cpu2: completed 60000 read accesses @1990627 -system.cpu1: completed 70000 read accesses @2268077 -system.cpu0: completed 70000 read accesses @2271308 -system.cpu6: completed 70000 read accesses @2299743 -system.cpu5: completed 70000 read accesses @2302988 -system.cpu4: completed 70000 read accesses @2306754 -system.cpu3: completed 70000 read accesses @2313390 -system.cpu7: completed 70000 read accesses @2318502 -system.cpu2: completed 70000 read accesses @2323657 -system.cpu1: completed 80000 read accesses @2590310 -system.cpu0: completed 80000 read accesses @2594700 -system.cpu5: completed 80000 read accesses @2629321 -system.cpu6: completed 80000 read accesses @2631814 -system.cpu4: completed 80000 read accesses @2636634 -system.cpu7: completed 80000 read accesses @2643921 -system.cpu2: completed 80000 read accesses @2656705 -system.cpu3: completed 80000 read accesses @2656992 -system.cpu0: completed 90000 read accesses @2911654 -system.cpu1: completed 90000 read accesses @2922192 -system.cpu5: completed 90000 read accesses @2956637 -system.cpu4: completed 90000 read accesses @2959893 -system.cpu6: completed 90000 read accesses @2961119 -system.cpu7: completed 90000 read accesses @2975550 -system.cpu2: completed 90000 read accesses @2985342 -system.cpu3: completed 90000 read accesses @2990681 -system.cpu1: completed 100000 read accesses @3238178 +system.cpu1: completed 10000 read accesses @259577 +system.cpu0: completed 10000 read accesses @261691 +system.cpu2: completed 10000 read accesses @262448 +system.cpu4: completed 10000 read accesses @265626 +system.cpu3: completed 10000 read accesses @266344 +system.cpu5: completed 10000 read accesses @266516 +system.cpu6: completed 10000 read accesses @267684 +system.cpu7: completed 10000 read accesses @268638 +system.cpu1: completed 20000 read accesses @519100 +system.cpu0: completed 20000 read accesses @521736 +system.cpu2: completed 20000 read accesses @529201 +system.cpu3: completed 20000 read accesses @532255 +system.cpu5: completed 20000 read accesses @532404 +system.cpu4: completed 20000 read accesses @532424 +system.cpu7: completed 20000 read accesses @535360 +system.cpu6: completed 20000 read accesses @536664 +system.cpu1: completed 30000 read accesses @774266 +system.cpu0: completed 30000 read accesses @780038 +system.cpu2: completed 30000 read accesses @794686 +system.cpu3: completed 30000 read accesses @796805 +system.cpu4: completed 30000 read accesses @799281 +system.cpu5: completed 30000 read accesses @800130 +system.cpu7: completed 30000 read accesses @801781 +system.cpu6: completed 30000 read accesses @804162 +system.cpu1: completed 40000 read accesses @1035943 +system.cpu0: completed 40000 read accesses @1039358 +system.cpu2: completed 40000 read accesses @1059277 +system.cpu3: completed 40000 read accesses @1060199 +system.cpu4: completed 40000 read accesses @1064627 +system.cpu7: completed 40000 read accesses @1067088 +system.cpu5: completed 40000 read accesses @1067587 +system.cpu6: completed 40000 read accesses @1068391 +system.cpu1: completed 50000 read accesses @1295510 +system.cpu0: completed 50000 read accesses @1297797 +system.cpu3: completed 50000 read accesses @1325540 +system.cpu2: completed 50000 read accesses @1326017 +system.cpu4: completed 50000 read accesses @1331456 +system.cpu7: completed 50000 read accesses @1333668 +system.cpu6: completed 50000 read accesses @1333852 +system.cpu5: completed 50000 read accesses @1335024 +system.cpu1: completed 60000 read accesses @1553527 +system.cpu0: completed 60000 read accesses @1555899 +system.cpu3: completed 60000 read accesses @1589626 +system.cpu2: completed 60000 read accesses @1591245 +system.cpu4: completed 60000 read accesses @1597413 +system.cpu7: completed 60000 read accesses @1598551 +system.cpu5: completed 60000 read accesses @1599840 +system.cpu6: completed 60000 read accesses @1602447 +system.cpu1: completed 70000 read accesses @1813006 +system.cpu0: completed 70000 read accesses @1815385 +system.cpu3: completed 70000 read accesses @1856089 +system.cpu2: completed 70000 read accesses @1860231 +system.cpu4: completed 70000 read accesses @1861345 +system.cpu7: completed 70000 read accesses @1865247 +system.cpu5: completed 70000 read accesses @1865658 +system.cpu6: completed 70000 read accesses @1870905 +system.cpu1: completed 80000 read accesses @2073465 +system.cpu0: completed 80000 read accesses @2073474 +system.cpu3: completed 80000 read accesses @2122890 +system.cpu2: completed 80000 read accesses @2123622 +system.cpu4: completed 80000 read accesses @2125318 +system.cpu5: completed 80000 read accesses @2131953 +system.cpu7: completed 80000 read accesses @2132039 +system.cpu6: completed 80000 read accesses @2134601 +system.cpu1: completed 90000 read accesses @2330638 +system.cpu0: completed 90000 read accesses @2331942 +system.cpu3: completed 90000 read accesses @2386875 +system.cpu2: completed 90000 read accesses @2387490 +system.cpu4: completed 90000 read accesses @2392144 +system.cpu7: completed 90000 read accesses @2398307 +system.cpu5: completed 90000 read accesses @2400565 +system.cpu6: completed 90000 read accesses @2400679 +system.cpu1: completed 100000 read accesses @2588247 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:58:42 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:39:30 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:44:10 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 3238178 because maximum number of loads reached +Exiting @ tick 2588247 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 340284 # Number of bytes of host memory used -host_seconds 34.80 # Real time elapsed on the host -host_tick_rate 93055 # Simulator tick rate (ticks/s) +host_mem_usage 342420 # Number of bytes of host memory used +host_seconds 28.03 # Real time elapsed on the host +host_tick_rate 92334 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.003238 # Number of seconds simulated -sim_ticks 3238178 # Number of ticks simulated +sim_seconds 0.002588 # Number of seconds simulated +sim_ticks 2588247 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99983 # number of read accesses completed -system.cpu0.num_writes 54267 # number of write accesses completed +system.cpu0.num_reads 99895 # number of read accesses completed +system.cpu0.num_writes 53778 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed system.cpu1.num_reads 100000 # number of read accesses completed -system.cpu1.num_writes 53571 # number of write accesses completed +system.cpu1.num_writes 53776 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 97642 # number of read accesses completed -system.cpu2.num_writes 52892 # number of write accesses completed +system.cpu2.num_reads 97709 # number of read accesses completed +system.cpu2.num_writes 52049 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 97531 # number of read accesses completed -system.cpu3.num_writes 52364 # number of write accesses completed +system.cpu3.num_reads 97680 # number of read accesses completed +system.cpu3.num_writes 52205 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 98570 # number of read accesses completed -system.cpu4.num_writes 53173 # number of write accesses completed +system.cpu4.num_reads 97290 # number of read accesses completed +system.cpu4.num_writes 52328 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 98261 # number of read accesses completed -system.cpu5.num_writes 52643 # number of write accesses completed +system.cpu5.num_reads 96950 # number of read accesses completed +system.cpu5.num_writes 52355 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98464 # number of read accesses completed -system.cpu6.num_writes 52805 # number of write accesses completed +system.cpu6.num_reads 97052 # number of read accesses completed +system.cpu6.num_writes 52770 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 97833 # number of read accesses completed -system.cpu7.num_writes 52922 # number of write accesses completed +system.cpu7.num_reads 97171 # number of read accesses completed +system.cpu7.num_writes 52095 # number of write accesses completed ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,14 @@ [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.l1_cntrl0.sequencer.port[0] [system.cpu1] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.l1_cntrl1.sequencer.port[0] [system.cpu2] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.l1_cntrl2.sequencer.port[0] [system.cpu3] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.l1_cntrl3.sequencer.port[0] [system.cpu4] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.l1_cntrl4.sequencer.port[0] [system.cpu5] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.l1_cntrl5.sequencer.port[0] [system.cpu6] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.l1_cntrl6.sequencer.port[0] [system.cpu7] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,58 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.l1_cntrl7.sequencer.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 [system.funcmem] type=PhysicalMemory @@ -139,6 +198,430 @@ zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl1.sequencer.dcache +L1IcacheMemory=system.l1_cntrl1.sequencer.icache +L2cacheMemory=system.l1_cntrl1.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl1.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl1.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.l1_cntrl1.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl2.sequencer.dcache +L1IcacheMemory=system.l1_cntrl2.sequencer.icache +L2cacheMemory=system.l1_cntrl2.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl2.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl2.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.l1_cntrl2.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl3.sequencer.dcache +L1IcacheMemory=system.l1_cntrl3.sequencer.icache +L2cacheMemory=system.l1_cntrl3.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl3.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl3.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.l1_cntrl3.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl4.sequencer.dcache +L1IcacheMemory=system.l1_cntrl4.sequencer.icache +L2cacheMemory=system.l1_cntrl4.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl4.sequencer +transitions_per_cycle=32 +version=4 + +[system.l1_cntrl4.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl4.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl4.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl4.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.l1_cntrl4.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl5.sequencer.dcache +L1IcacheMemory=system.l1_cntrl5.sequencer.icache +L2cacheMemory=system.l1_cntrl5.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl5.sequencer +transitions_per_cycle=32 +version=5 + +[system.l1_cntrl5.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl5.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl5.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl5.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.l1_cntrl5.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl6.sequencer.dcache +L1IcacheMemory=system.l1_cntrl6.sequencer.icache +L2cacheMemory=system.l1_cntrl6.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl6.sequencer +transitions_per_cycle=32 +version=6 + +[system.l1_cntrl6.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl6.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl6.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl6.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.l1_cntrl6.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl7.sequencer.dcache +L1IcacheMemory=system.l1_cntrl7.sequencer.icache +L2cacheMemory=system.l1_cntrl7.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl7.sequencer +transitions_per_cycle=32 +version=7 + +[system.l1_cntrl7.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl7.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl7.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl7.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.l1_cntrl7.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -147,7 +630,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort [system.ruby] type=RubySystem @@ -188,523 +671,82 @@ children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 +name=Crossbar num_int_nodes=10 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l1_cntrl1 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer -transitions_per_cycle=32 -version=1 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.l1_cntrl2 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer -transitions_per_cycle=32 -version=2 - -[system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links3] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node +ext_node=system.l1_cntrl3 int_node=3 latency=1 weight=1 -[system.ruby.network.topology.ext_links3.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer -transitions_per_cycle=32 -version=3 - -[system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links4] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node +ext_node=system.l1_cntrl4 int_node=4 latency=1 weight=1 -[system.ruby.network.topology.ext_links4.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer -transitions_per_cycle=32 -version=4 - -[system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links5] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node +ext_node=system.l1_cntrl5 int_node=5 latency=1 weight=1 -[system.ruby.network.topology.ext_links5.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer -transitions_per_cycle=32 -version=5 - -[system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links6] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node +ext_node=system.l1_cntrl6 int_node=6 latency=1 weight=1 -[system.ruby.network.topology.ext_links6.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer -transitions_per_cycle=32 -version=6 - -[system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links7] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node +ext_node=system.l1_cntrl7 int_node=7 latency=1 weight=1 -[system.ruby.network.topology.ext_links7.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer -transitions_per_cycle=32 -version=7 - -[system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links8] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node +ext_node=system.dir_cntrl0 int_node=8 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links8.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:41:16 +Real time: Aug/05/2010 14:45:41 Profiler Stats -------------- -Elapsed_time_in_seconds: 42 -Elapsed_time_in_minutes: 0.7 -Elapsed_time_in_hours: 0.0116667 -Elapsed_time_in_days: 0.000486111 +Elapsed_time_in_seconds: 38 +Elapsed_time_in_minutes: 0.633333 +Elapsed_time_in_hours: 0.0105556 +Elapsed_time_in_days: 0.000439815 -Virtual_time_in_seconds: 41.62 -Virtual_time_in_minutes: 0.693667 -Virtual_time_in_hours: 0.0115611 -Virtual_time_in_days: 0.000481713 +Virtual_time_in_seconds: 33.77 +Virtual_time_in_minutes: 0.562833 +Virtual_time_in_hours: 0.00938056 +Virtual_time_in_days: 0.000390856 -Ruby_current_time: 4339943 +Ruby_current_time: 3296793 Ruby_start_time: 0 -Ruby_cycles: 4339943 +Ruby_cycles: 3296793 -mbytes_resident: 31.0664 -mbytes_total: 331.992 -resident_ratio: 0.0935875 +mbytes_resident: 32.5469 +mbytes_total: 32.5508 +resident_ratio: 1 -ruby_cycles_executed: [ 4339944 4339944 4339944 4339944 4339944 4339944 4339944 4339944 ] +ruby_cycles_executed: [ 3296794 3296794 3296794 3296794 3296794 3296794 3296794 3296794 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,13 +66,32 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1220000 average: 1.95591 | standard deviation: 0.205285 | 0 53784 1166216 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1220328 average: 1.93818 | standard deviation: 0.240827 | 0 75439 1144889 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 32 max: 3607 count: 1219984 average: 54.9119 | standard deviation: 182.333 | 1064696 314 18737 8292 796 30614 532 5225 780 21798 1270 3844 11788 1197 5096 303 6413 275 5252 3545 375 4450 257 2872 2476 991 1837 556 2218 197 1865 604 1071 1361 228 1048 137 1046 570 388 599 212 546 244 393 212 323 210 211 245 53 220 76 196 114 49 122 38 113 45 62 37 35 59 19 37 14 22 34 5 16 10 13 8 11 4 10 3 6 9 1 4 1 2 3 2 1 4 6 0 0 4 0 1 1 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 3607 count: 792479 average: 51.7896 | standard deviation: 176.738 | 697175 1 11915 5038 177 19519 38 3208 50 13951 594 2378 7373 537 3179 11 4092 52 3231 2247 136 2884 69 1753 1510 586 1132 311 1374 79 1212 349 631 823 98 659 55 644 326 227 369 127 356 145 261 103 206 116 136 148 29 125 41 120 76 32 78 18 76 27 35 22 21 42 12 26 10 12 19 1 9 7 5 4 6 2 4 1 2 4 0 2 1 1 1 0 1 3 6 0 0 3 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 16 max: 3187 count: 427505 average: 60.6998 | standard deviation: 192.141 | 367521 0 0 313 6757 65 402 2852 317 302 297 10798 219 275 1248 769 238 492 7574 273 204 472 1357 109 352 4063 435 225 185 1732 53 239 2238 83 155 68 1856 165 56 1242 93 146 1291 275 136 52 936 183 83 883 266 139 145 560 172 73 479 365 36 82 427 226 56 199 408 32 55 483 84 46 80 309 63 19 348 54 52 192 102 59 13 217 74 11 119 71 54 45 75 57 18 91 105 12 31 63 60 15 28 69 15 9 79 16 18 17 57 19 5 33 9 8 26 18 13 7 25 12 5 13 13 14 8 7 14 0 4 13 3 4 3 8 1 3 9 1 2 13 1 3 3 4 3 0 5 3 3 1 1 4 0 2 5 1 1 1 3 1 3 2 0 1 2 0 0 0 1 0 0 2 1 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ] +miss_latency: [binsize: 4 max: 441 count: 1220312 average: 41.2183 | standard deviation: 90.123 | 996122 0 0 0 0 0 0 0 6171 31 71 54 147 1410 9870 215 0 0 605 609 263 931 287 750 6016 6958 5 1 13 152 531 3781 424 727 2329 12612 1550 7 42 223 585 4722 4107 536 1085 7395 10765 52 139 587 788 4884 7440 219 459 2244 15668 2732 440 1207 2665 3127 7013 1702 94 603 7660 13175 1248 2185 3571 2308 4923 1723 26 192 2877 26054 7148 2663 2802 2325 1173 877 41 4 52 998 1647 3 0 0 0 0 0 0 2 47 371 19 1 0 0 0 0 0 0 0 14 14 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 441 count: 793540 average: 22.1779 | standard deviation: 65.0031 | 709224 0 0 0 0 0 0 0 0 0 0 5 77 1303 9718 22 0 0 0 0 0 1 26 314 5295 5608 0 0 0 0 0 0 7 83 1248 9777 52 0 0 0 0 0 3 30 334 5152 5725 1 0 0 0 0 0 6 79 1247 9883 100 0 0 0 0 1 1 14 350 5286 6015 8 0 0 0 0 1 7 107 1808 14409 200 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4 max: 437 count: 426772 average: 76.622 | standard deviation: 115.932 | 286898 0 0 0 0 0 0 0 6171 31 71 49 70 107 152 193 0 0 605 609 263 930 261 436 721 1350 5 1 13 152 531 3781 417 644 1081 2835 1498 7 42 223 585 4722 4104 506 751 2243 5040 51 139 587 788 4884 7440 213 380 997 5785 2632 440 1207 2665 3127 7012 1701 80 253 2374 7160 1240 2185 3571 2308 4923 1722 19 85 1069 11645 6948 2663 2802 2325 1167 877 41 4 52 998 1647 3 0 0 0 0 0 0 2 47 371 19 0 0 0 0 0 0 0 0 14 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 2 count: 996122 average: 2 | standard deviation: 0 | 0 0 996122 ] +miss_latency_Directory: [binsize: 2 max: 358 count: 2 average: 303 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 4 max: 441 count: 224188 average: 215.472 | standard deviation: 83.7366 | 0 0 0 0 0 0 0 0 6171 31 71 54 147 1410 9870 215 0 0 605 609 263 931 287 750 6016 6958 5 1 13 152 531 3781 424 727 2329 12612 1550 7 42 223 585 4722 4107 536 1085 7395 10765 52 139 587 788 4884 7440 219 459 2244 15668 2732 440 1207 2665 3127 7012 1702 94 603 7660 13175 1248 2185 3571 2308 4923 1723 26 192 2877 26054 7148 2663 2802 2325 1173 877 41 4 52 998 1647 2 0 0 0 0 0 0 2 47 371 19 1 0 0 0 0 0 0 0 14 14 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 4 max: 417 count: 224188 average: 64.3931 | standard deviation: 96.3956 | 139874 0 0 0 0 5 77 1303 9718 22 0 0 0 0 0 1 26 314 5295 5608 0 0 0 0 0 0 7 83 1248 9777 52 0 0 0 0 0 3 30 334 5152 5725 1 0 0 0 0 0 6 79 1247 9883 100 0 0 0 0 0 1 14 350 5286 6015 8 0 0 0 0 1 7 107 1808 14409 200 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 4 max: 411 count: 224188 average: 127.378 | standard deviation: 116.102 | 84314 0 6200 15 96 59 102 129 243 0 0 0 1204 63 1022 233 344 572 1157 585 0 8 125 143 1634 2742 527 825 1690 3256 4 20 99 171 2222 6974 416 589 1229 4764 1768 66 280 1067 1750 7444 3353 278 557 2732 6227 265 743 1903 1796 6588 4926 77 145 765 6652 2794 1630 2917 3880 2843 3742 429 34 287 4582 13709 2401 2777 2812 1132 1617 273 3 11 257 2139 295 0 0 0 0 0 0 1 12 181 244 2 0 0 0 0 0 0 0 3 23 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 24 count: 224188 average: 23.6239 | standard deviation: 0.484405 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 84314 139874 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 2 count: 224188 average: 0.0775153 | standard deviation: 0.269254 | 206921 17156 111 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 2 count: 2 average: 2 | standard deviation: 0 | 0 0 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 8 count: 2 average: 8 | standard deviation: 0 | 0 0 0 0 0 0 0 0 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 24 count: 2 average: 24 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 324 count: 2 average: 269 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 2 count: 709224 average: 2 | standard deviation: 0 | 0 0 709224 ] +miss_latency_LD_Directory: [binsize: 2 max: 248 count: 1 average: 248 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 441 count: 84315 average: 191.904 | standard deviation: 86.8085 | 0 0 0 0 0 0 0 0 0 0 0 5 77 1303 9718 22 0 0 0 0 0 1 26 314 5295 5608 0 0 0 0 0 0 7 83 1248 9777 52 0 0 0 0 0 3 30 334 5152 5725 1 0 0 0 0 0 6 79 1247 9883 100 0 0 0 0 0 1 14 350 5286 6015 8 0 0 0 0 1 7 107 1808 14409 200 0 0 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 2 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 2 count: 286898 average: 2 | standard deviation: 0 | 0 0 286898 ] +miss_latency_ST_Directory: [binsize: 2 max: 358 count: 1 average: 358 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache_wCC: [binsize: 4 max: 437 count: 139873 average: 229.679 | standard deviation: 78.4816 | 0 0 0 0 0 0 0 0 6171 31 71 49 70 107 152 193 0 0 605 609 263 930 261 436 721 1350 5 1 13 152 531 3781 417 644 1081 2835 1498 7 42 223 585 4722 4104 506 751 2243 5040 51 139 587 788 4884 7440 213 380 997 5785 2632 440 1207 2665 3127 7012 1701 80 253 2374 7160 1240 2185 3571 2308 4923 1722 19 85 1069 11645 6948 2663 2802 2325 1167 877 41 4 52 998 1647 2 0 0 0 0 0 0 2 47 371 19 0 0 0 0 0 0 0 0 14 12 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -102,10 +121,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 41 -system_time: 0 -page_reclaims: 8947 -page_faults: 0 +user_time: 32 +system_time: 1 +page_reclaims: 7249 +page_faults: 1887 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,1882 +132,731 @@ Network Stats ------------- +total_msg_count_Request_Control: 724119 5792952 +total_msg_count_Response_Data: 603223 43432056 +total_msg_count_Response_Control: 2519982 20159856 +total_msg_count_Broadcast_Control: 2098155 16785240 +total_msg_count_Unblock_Control: 672567 5380536 +total_msgs: 6618046 total_bytes: 91550640 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.251482 - links_utilized_percent_switch_0_link_0: 0.123013 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.379951 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.346902 + links_utilized_percent_switch_0_link_0: 0.182629 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.511176 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 19379 1395288 [ 0 0 0 0 19379 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 116856 934848 [ 0 0 0 0 116856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Forwarded_Control: 135827 1086616 [ 0 0 0 135827 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 19464 155712 [ 0 0 19464 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 19380 1395360 [ 0 0 0 0 19380 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 116447 931576 [ 0 0 0 0 116447 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 19462 155696 [ 0 0 0 0 0 19462 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Request_Control: 2110 16880 [ 0 0 0 2110 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 27987 2015064 [ 0 0 0 0 27987 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 105344 842752 [ 0 0 0 0 105344 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Broadcast_Control: 122336 978688 [ 0 0 0 122336 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 28086 224688 [ 0 0 28086 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 19554 1407888 [ 0 0 0 0 19554 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 104892 839136 [ 0 0 0 0 104892 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 28084 224672 [ 0 0 0 0 0 28084 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.251327 - links_utilized_percent_switch_1_link_0: 0.122954 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.3797 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.346935 + links_utilized_percent_switch_1_link_0: 0.182399 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.51147 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 19361 1393992 [ 0 0 0 0 19361 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 116804 934432 [ 0 0 0 0 116804 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Forwarded_Control: 135837 1086696 [ 0 0 0 135837 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 19454 155632 [ 0 0 19454 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 19354 1393488 [ 0 0 0 0 19354 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 116483 931864 [ 0 0 0 0 116483 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 19452 155616 [ 0 0 0 0 0 19452 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 2150 17200 [ 0 0 0 2150 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 27920 2010240 [ 0 0 0 0 27920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 105292 842336 [ 0 0 0 0 105292 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Broadcast_Control: 122344 978752 [ 0 0 0 122344 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 28015 224120 [ 0 0 28015 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 19590 1410480 [ 0 0 0 0 19590 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 104904 839232 [ 0 0 0 0 104904 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 28013 224104 [ 0 0 0 0 0 28013 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.250111 - links_utilized_percent_switch_2_link_0: 0.122199 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.378023 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.346526 + links_utilized_percent_switch_2_link_0: 0.182718 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.510334 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 19177 1380744 [ 0 0 0 0 19177 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 115650 925200 [ 0 0 0 0 115650 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Forwarded_Control: 136028 1088224 [ 0 0 0 136028 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 19263 154104 [ 0 0 19263 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 19196 1382112 [ 0 0 0 0 19196 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 116832 934656 [ 0 0 0 0 116832 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 19261 154088 [ 0 0 0 0 0 19261 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 2081 16648 [ 0 0 0 2081 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 28063 2020536 [ 0 0 0 0 28063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 104844 838752 [ 0 0 0 0 104844 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Broadcast_Control: 122416 979328 [ 0 0 0 122416 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 28143 225144 [ 0 0 28143 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 19464 1401408 [ 0 0 0 0 19464 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 105033 840264 [ 0 0 0 0 105033 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 28141 225128 [ 0 0 0 0 0 28141 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.25008 - links_utilized_percent_switch_3_link_0: 0.122428 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.377733 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.347161 + links_utilized_percent_switch_3_link_0: 0.182304 bw: 640000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.512017 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 19237 1385064 [ 0 0 0 0 19237 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 115954 927632 [ 0 0 0 0 115954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Forwarded_Control: 135976 1087808 [ 0 0 0 135976 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 19315 154520 [ 0 0 19315 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 19158 1379376 [ 0 0 0 0 19158 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 116818 934544 [ 0 0 0 0 116818 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 19313 154504 [ 0 0 0 0 0 19313 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Request_Control: 2226 17808 [ 0 0 0 2226 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 27908 2009376 [ 0 0 0 0 27908 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 105031 840248 [ 0 0 0 0 105031 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Broadcast_Control: 122387 979096 [ 0 0 0 122387 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 28000 224000 [ 0 0 28000 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 19624 1412928 [ 0 0 0 0 19624 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 104989 839912 [ 0 0 0 0 104989 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 27998 223984 [ 0 0 0 0 0 27998 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.251163 - links_utilized_percent_switch_4_link_0: 0.122805 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.379521 bw: 160000 base_latency: 1 +links_utilized_percent_switch_4: 0.346623 + links_utilized_percent_switch_4_link_0: 0.182204 bw: 640000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.511042 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 19329 1391688 [ 0 0 0 0 19329 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Control: 116534 932272 [ 0 0 0 0 116534 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Forwarded_Control: 135880 1087040 [ 0 0 0 135880 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Request_Control: 19411 155288 [ 0 0 19411 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 19340 1392480 [ 0 0 0 0 19340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Control: 116540 932320 [ 0 0 0 0 116540 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Unblock_Control: 19409 155272 [ 0 0 0 0 0 19409 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Request_Control: 2144 17152 [ 0 0 0 2144 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 27880 2007360 [ 0 0 0 0 27880 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Control: 105115 840920 [ 0 0 0 0 105115 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Broadcast_Control: 122372 978976 [ 0 0 0 122372 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Request_Control: 27967 223736 [ 0 0 27967 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 19564 1408608 [ 0 0 0 0 19564 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Control: 104952 839616 [ 0 0 0 0 104952 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Unblock_Control: 27965 223720 [ 0 0 0 0 0 27965 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.251317 - links_utilized_percent_switch_5_link_0: 0.122856 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.379778 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.346078 + links_utilized_percent_switch_5_link_0: 0.182267 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.509889 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 19339 1392408 [ 0 0 0 0 19339 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Control: 116636 933088 [ 0 0 0 0 116636 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Forwarded_Control: 135863 1086904 [ 0 0 0 135863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Request_Control: 19427 155416 [ 0 0 19427 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 19366 1394352 [ 0 0 0 0 19366 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Control: 116497 931976 [ 0 0 0 0 116497 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Unblock_Control: 19425 155400 [ 0 0 0 0 0 19425 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Request_Control: 2101 16808 [ 0 0 0 2101 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 27942 2011824 [ 0 0 0 0 27942 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Control: 104696 837568 [ 0 0 0 0 104696 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Broadcast_Control: 122441 979528 [ 0 0 0 122441 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Request_Control: 28030 224240 [ 0 0 28030 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 19450 1400400 [ 0 0 0 0 19450 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Control: 105092 840736 [ 0 0 0 0 105092 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Unblock_Control: 28028 224224 [ 0 0 0 0 0 28028 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.250843 - links_utilized_percent_switch_6_link_0: 0.122534 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.379151 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.346586 + links_utilized_percent_switch_6_link_0: 0.182215 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.510957 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 19266 1387152 [ 0 0 0 0 19266 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Control: 116086 928688 [ 0 0 0 0 116086 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Forwarded_Control: 135953 1087624 [ 0 0 0 135953 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Request_Control: 19338 154704 [ 0 0 19338 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 19309 1390248 [ 0 0 0 0 19309 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Control: 116644 933152 [ 0 0 0 0 116644 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Unblock_Control: 19336 154688 [ 0 0 0 0 0 19336 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Request_Control: 2171 17368 [ 0 0 0 2171 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 27898 2008656 [ 0 0 0 0 27898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Control: 104920 839360 [ 0 0 0 0 104920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Broadcast_Control: 122407 979256 [ 0 0 0 122407 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Request_Control: 28000 224000 [ 0 0 28000 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 19541 1406952 [ 0 0 0 0 19541 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Control: 105037 840296 [ 0 0 0 0 105037 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Unblock_Control: 27998 223984 [ 0 0 0 0 0 27998 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.252566 - links_utilized_percent_switch_7_link_0: 0.123671 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.381461 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.346356 + links_utilized_percent_switch_7_link_0: 0.18203 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.510683 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 19539 1406808 [ 0 0 0 0 19539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Control: 117871 942968 [ 0 0 0 0 117871 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Forwarded_Control: 135659 1085272 [ 0 0 0 135659 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Request_Control: 19631 157048 [ 0 0 19631 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 19523 1405656 [ 0 0 0 0 19523 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Control: 116136 929088 [ 0 0 0 0 116136 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Unblock_Control: 19630 157040 [ 0 0 0 0 0 19630 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Request_Control: 2185 17480 [ 0 0 0 2185 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 27858 2005776 [ 0 0 0 0 27858 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Control: 104750 838000 [ 0 0 0 0 104750 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Broadcast_Control: 122436 979488 [ 0 0 0 122436 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Request_Control: 27964 223712 [ 0 0 27964 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 19522 1405584 [ 0 0 0 0 19522 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Control: 105099 840792 [ 0 0 0 0 105099 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Unblock_Control: 27962 223696 [ 0 0 0 0 0 27962 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 -links_utilized_percent_switch_8: 0.134192 - links_utilized_percent_switch_8_link_0: 0.0894571 bw: 640000 base_latency: 1 - links_utilized_percent_switch_8_link_1: 0.178927 bw: 160000 base_latency: 1 +links_utilized_percent_switch_8: 0.204109 + links_utilized_percent_switch_8_link_0: 0.170011 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_1: 0.238206 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Request_Control: 155303 1242424 [ 0 0 155303 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_0_Unblock_Control: 155288 1242304 [ 0 0 0 0 0 155288 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Request_Control: 224205 1793640 [ 0 0 224205 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Unblock_Control: 224189 1793512 [ 0 0 0 0 0 224189 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Request_Control: 17168 137344 [ 0 0 0 17168 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Forwarded_Control: 155289 1242312 [ 0 0 0 155289 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Broadcast_Control: 139877 1119016 [ 0 0 0 139877 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 -links_utilized_percent_switch_9: 0.47641 - links_utilized_percent_switch_9_link_0: 0.49205 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.491815 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.488798 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.48971 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.491222 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.491441 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.490137 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.494685 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.357828 bw: 160000 base_latency: 1 +links_utilized_percent_switch_9: 0.723902 + links_utilized_percent_switch_9_link_0: 0.730518 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.729597 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.730874 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.729218 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.728816 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.729066 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.72886 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.728121 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 0.680046 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 19379 1395288 [ 0 0 0 0 19379 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Control: 116856 934848 [ 0 0 0 0 116856 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Forwarded_Control: 135827 1086616 [ 0 0 0 135827 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 19361 1393992 [ 0 0 0 0 19361 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Control: 116804 934432 [ 0 0 0 0 116804 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Forwarded_Control: 135837 1086696 [ 0 0 0 135837 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 19177 1380744 [ 0 0 0 0 19177 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Control: 115650 925200 [ 0 0 0 0 115650 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Forwarded_Control: 136028 1088224 [ 0 0 0 136028 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 19237 1385064 [ 0 0 0 0 19237 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Control: 115954 927632 [ 0 0 0 0 115954 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Forwarded_Control: 135976 1087808 [ 0 0 0 135976 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 19329 1391688 [ 0 0 0 0 19329 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Control: 116534 932272 [ 0 0 0 0 116534 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Forwarded_Control: 135880 1087040 [ 0 0 0 135880 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 19340 1392480 [ 0 0 0 0 19340 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Control: 116642 933136 [ 0 0 0 0 116642 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Forwarded_Control: 135863 1086904 [ 0 0 0 135863 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 19266 1387152 [ 0 0 0 0 19266 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Control: 116086 928688 [ 0 0 0 0 116086 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Forwarded_Control: 135953 1087624 [ 0 0 0 135953 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 19539 1406808 [ 0 0 0 0 19539 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Control: 117871 942968 [ 0 0 0 0 117871 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Forwarded_Control: 135659 1085272 [ 0 0 0 135659 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Request_Control: 155303 1242424 [ 0 0 155303 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Unblock_Control: 155288 1242304 [ 0 0 0 0 0 155288 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Request_Control: 2110 16880 [ 0 0 0 2110 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 27987 2015064 [ 0 0 0 0 27987 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Control: 105344 842752 [ 0 0 0 0 105344 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Broadcast_Control: 122336 978688 [ 0 0 0 122336 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Request_Control: 2150 17200 [ 0 0 0 2150 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 27920 2010240 [ 0 0 0 0 27920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Control: 105292 842336 [ 0 0 0 0 105292 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Broadcast_Control: 122344 978752 [ 0 0 0 122344 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Request_Control: 2081 16648 [ 0 0 0 2081 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 28063 2020536 [ 0 0 0 0 28063 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Control: 104844 838752 [ 0 0 0 0 104844 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Broadcast_Control: 122416 979328 [ 0 0 0 122416 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Request_Control: 2226 17808 [ 0 0 0 2226 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 27908 2009376 [ 0 0 0 0 27908 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Control: 105031 840248 [ 0 0 0 0 105031 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Broadcast_Control: 122387 979096 [ 0 0 0 122387 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Request_Control: 2144 17152 [ 0 0 0 2144 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 27880 2007360 [ 0 0 0 0 27880 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Control: 105115 840920 [ 0 0 0 0 105115 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Broadcast_Control: 122372 978976 [ 0 0 0 122372 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Request_Control: 2101 16808 [ 0 0 0 2101 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 27942 2011824 [ 0 0 0 0 27942 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Control: 104696 837568 [ 0 0 0 0 104696 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Broadcast_Control: 122441 979528 [ 0 0 0 122441 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Request_Control: 2171 17368 [ 0 0 0 2171 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 27898 2008656 [ 0 0 0 0 27898 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Control: 104920 839360 [ 0 0 0 0 104920 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Broadcast_Control: 122407 979256 [ 0 0 0 122407 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Request_Control: 2185 17480 [ 0 0 0 2185 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 27858 2005776 [ 0 0 0 0 27858 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Control: 104750 838000 [ 0 0 0 0 104750 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Broadcast_Control: 122436 979488 [ 0 0 0 122436 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Request_Control: 224205 1793640 [ 0 0 224205 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Unblock_Control: 224189 1793512 [ 0 0 0 0 0 224189 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 28086 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 28086 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 61.7242% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 38.2758% + system.l1_cntrl0.sequencer.dcache_request_type_LD: 37.5418% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 62.4582% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19464 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19464 average: 1 | standard deviation: 0 | 0 19464 ] + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 28086 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 19464 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 28086 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 28086 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 61.7242% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 38.2758% + system.l1_cntrl0.L2cacheMemory_request_type_LD: 37.5418% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 62.4582% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19464 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19464 average: 1 | standard deviation: 0 | 0 19464 ] + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 28086 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 99315 -Ifetch 0 -Store 53538 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52535 -Other_GETS 83292 -Ack 116277 -Shared_Ack 579 -Data 284 -Shared_Data 730 -Exclusive_Data 18365 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 730 -All_acks_no_sharers 18732 +Load [98925 99000 98940 99084 99094 99232 99267 100000 ] 793542 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [53558 53066 53475 53312 53669 53355 53241 53109 ] 426785 +L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +Other_GETX [122370 122439 122406 122434 122335 122342 122414 122385 ] 979125 +Other_GETS [2 2 1 2 1 2 2 2 ] 14 +Merged_GETS [2144 2101 2171 2185 2110 2150 2081 2226 ] 17168 +Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +Invalidate [0 0 0 0 0 0 0 0 ] 0 +Ack [105115 104696 104920 104750 105344 105292 104844 105031 ] 839992 +Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +Data [2062 2020 2025 2037 2082 2076 2092 2039 ] 16433 +Shared_Data [10460 10593 10528 10521 10543 10480 10680 10509 ] 84314 +Exclusive_Data [15358 15329 15345 15300 15362 15364 15291 15360 ] 122709 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 +All_acks [10460 10593 10528 10521 10543 10480 10680 10509 ] 84314 +All_acks_no_sharers [17505 17435 17470 17441 17541 17533 17461 17490 ] 139876 - Transitions - -I Load 12014 -I Ifetch 0 <-- -I Store 6365 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- +I Load [10460 10593 10530 10521 10544 10481 10680 10509 ] 84318 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [5711 5615 5595 5571 5732 5747 5541 5624 ] 45136 +I L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +I L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +I Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +I Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +I Other_GETX [0 0 0 0 0 0 0 0 ] 0 +I Other_GETS [0 0 0 0 0 0 0 0 ] 0 +I Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +I Invalidate [0 0 0 0 0 0 0 0 ] 0 -S Load 1350 -S Ifetch 0 <-- -S Store 707 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 23 -S Other_GETS 26 +S Load [17849 18137 18139 18213 17864 17796 18072 18379 ] 144449 +S Ifetch [0 0 0 0 0 0 0 0 ] 0 +S Store [9670 9741 9724 9705 9726 9662 9861 9669 ] 77758 +S L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +S L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +S Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +S Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +S Other_GETX [790 852 804 816 817 818 819 840 ] 6556 +S Other_GETS [0 0 0 0 0 0 0 0 ] 0 +S Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +S Invalidate [0 0 0 0 0 0 0 0 ] 0 -O Load 765 -O Ifetch 0 <-- -O Store 378 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 4 +O Load [3743 3801 3857 3875 3919 4029 3726 4208 ] 31158 +O Ifetch [0 0 0 0 0 0 0 0 ] 0 +O Store [2126 2081 2151 2167 2084 2125 2061 2198 ] 16993 +O L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +O L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +O Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +O Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +O Other_GETX [18 20 20 18 26 25 20 28 ] 175 +O Other_GETS [0 0 0 0 0 0 0 0 ] 0 +O Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +O Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +O Invalidate [0 0 0 0 0 0 0 0 ] 0 -M Load 19541 -M Ifetch 0 <-- -M Store 10690 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 380 +M Load [0 0 0 0 2 0 0 0 ] 2 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [0 0 1 0 1 0 0 0 ] 2 +M L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +M L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +M Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +M Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +M Other_GETX [0 0 0 0 0 0 0 0 ] 0 +M Other_GETS [0 0 0 0 0 0 0 0 ] 0 +M Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +M Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +M Invalidate [0 0 0 0 0 0 0 0 ] 0 -MM Load 65645 -MM Ifetch 0 <-- -MM Store 35398 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6950 -MM Other_GETS 11190 +MM Load [66873 66469 66414 66475 66765 66926 66789 66904 ] 533615 +MM Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM Store [36051 35629 36004 35869 36126 35821 35778 35618 ] 286896 +MM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MM Trigger_L2_to_L1D [0 0 0 0 0 0 0 0 ] 0 +MM Trigger_L2_to_L1I [0 0 0 0 0 0 0 0 ] 0 +MM Other_GETX [15361 15334 15299 15256 15431 15382 15380 15263 ] 122706 +MM Other_GETS [0 0 0 0 0 1 0 0 ] 1 +MM Merged_GETS [2144 2101 2171 2185 2110 2150 2081 2226 ] 17168 +MM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MM Invalidate [0 0 0 0 0 0 0 0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 16962 -IM Other_GETS 26097 -IM Ack 21942 -IM Data 196 -IM Exclusive_Data 7083 +IM Load [0 0 0 0 0 0 0 0 ] 0 +IM Ifetch [0 0 0 0 0 0 0 0 ] 0 +IM Store [0 0 0 0 0 0 0 0 ] 0 +IM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IM Other_GETX [61490 61405 61518 61636 61221 61518 61238 61606 ] 491632 +IM Other_GETS [0 0 0 0 0 0 1 0 ] 1 +IM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IM Invalidate [0 0 0 0 0 0 0 0 ] 0 +IM Ack [50176 50308 50728 50420 50286 50583 50159 50245 ] 402905 +IM Data [1309 1286 1287 1274 1284 1304 1313 1266 ] 10323 +IM Exclusive_Data [15358 15329 15344 15300 15361 15364 15291 15360 ] 122707 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 619 -SM Other_GETS 540 -SM Ack 244 -SM Data 88 +SM Load [0 0 0 0 0 0 0 0 ] 0 +SM Ifetch [0 0 0 0 0 0 0 0 ] 0 +SM Store [0 0 0 0 0 0 0 0 ] 0 +SM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +SM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +SM Other_GETX [8917 9006 8986 8942 8928 8890 9082 8896 ] 71647 +SM Other_GETS [0 0 0 0 0 0 0 0 ] 0 +SM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +SM Invalidate [0 0 0 0 0 0 0 0 ] 0 +SM Ack [2184 2171 2263 2265 2457 2450 2354 2320 ] 18464 +SM Data [753 734 738 763 798 772 779 773 ] 6110 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 295 -OM Other_GETS 347 -OM Ack 581 -OM All_acks 0 <-- -OM All_acks_no_sharers 83 +OM Load [0 0 0 0 0 0 0 0 ] 0 +OM Ifetch [0 0 0 0 0 0 0 0 ] 0 +OM Store [0 0 0 0 0 0 0 0 ] 0 +OM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OM Other_GETX [2041 1995 2051 2063 1987 2032 1983 2107 ] 16259 +OM Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OM Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OM Invalidate [0 0 0 0 0 0 0 0 ] 0 +OM Ack [595 602 700 728 679 651 546 637 ] 5138 +OM All_acks [0 0 0 0 0 0 0 0 ] 0 +OM All_acks_no_sharers [85 86 100 104 97 93 78 91 ] 734 -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 912 -ISM All_acks_no_sharers 284 +ISM Load [0 0 0 0 0 0 0 0 ] 0 +ISM Ifetch [0 0 0 0 0 0 0 0 ] 0 +ISM Store [0 0 0 0 0 0 0 0 ] 0 +ISM L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +ISM L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +ISM Ack [6377 6081 6050 6109 6276 6126 6327 6060 ] 49406 +ISM All_acks_no_sharers [2062 2020 2025 2037 2082 2076 2092 2039 ] 16433 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 34227 -M_W All_acks_no_sharers 11282 +M_W Load [0 0 0 0 0 0 0 0 ] 0 +M_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +M_W Store [0 0 0 0 0 0 0 0 ] 0 +M_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +M_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +M_W Ack [0 0 4 0 0 0 0 0 ] 4 +M_W All_acks_no_sharers [0 0 1 0 1 0 0 0 ] 2 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21105 -MM_W All_acks_no_sharers 7083 +MM_W Load [0 0 0 0 0 0 0 0 ] 0 +MM_W Ifetch [0 0 0 0 0 0 0 0 ] 0 +MM_W Store [0 0 0 0 0 0 0 0 ] 0 +MM_W L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MM_W L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MM_W Ack [45783 45534 45173 45228 45639 45482 45458 45769 ] 364066 +MM_W All_acks_no_sharers [15358 15329 15344 15300 15361 15364 15291 15360 ] 122707 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27472 -IS Other_GETS 44708 -IS Ack 35359 -IS Shared_Ack 275 -IS Data 0 <-- -IS Shared_Data 730 -IS Exclusive_Data 11282 +IS Load [0 0 0 0 0 0 0 0 ] 0 +IS Ifetch [0 0 0 0 0 0 0 0 ] 0 +IS Store [0 0 0 0 0 0 0 0 ] 0 +IS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IS Other_GETX [33753 33827 33728 33703 33925 33677 33892 33645 ] 270150 +IS Other_GETS [2 2 1 2 1 1 1 2 ] 12 +IS Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IS Invalidate [0 0 0 0 0 0 0 0 ] 0 +IS Ack [0 0 2 0 7 0 0 0 ] 9 +IS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +IS Data [0 0 0 0 0 0 0 0 ] 0 +IS Shared_Data [10460 10593 10528 10521 10543 10480 10680 10509 ] 84314 +IS Exclusive_Data [0 0 1 0 1 0 0 0 ] 2 -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1907 -SS Shared_Ack 304 -SS All_acks 730 -SS All_acks_no_sharers 0 <-- +SS Load [0 0 0 0 0 0 0 0 ] 0 +SS Ifetch [0 0 0 0 0 0 0 0 ] 0 +SS Store [0 0 0 0 0 0 0 0 ] 0 +SS L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +SS L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +SS Ack [0 0 0 0 0 0 0 0 ] 0 +SS Shared_Ack [0 0 0 0 0 0 0 0 ] 0 +SS All_acks [10460 10593 10528 10521 10543 10480 10680 10509 ] 84314 +SS All_acks_no_sharers [0 0 0 0 0 0 0 0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- +OI Load [0 0 0 0 0 0 0 0 ] 0 +OI Ifetch [0 0 0 0 0 0 0 0 ] 0 +OI Store [0 0 0 0 0 0 0 0 ] 0 +OI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETX [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OI Invalidate [0 0 0 0 0 0 0 0 ] 0 +OI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- +MI Load [0 0 0 0 0 0 0 0 ] 0 +MI Ifetch [0 0 0 0 0 0 0 0 ] 0 +MI Store [0 0 0 0 0 0 0 0 ] 0 +MI L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MI L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MI Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MI Invalidate [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- +II Load [0 0 0 0 0 0 0 0 ] 0 +II Ifetch [0 0 0 0 0 0 0 0 ] 0 +II Store [0 0 0 0 0 0 0 0 ] 0 +II L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +II L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +II Other_GETX [0 0 0 0 0 0 0 0 ] 0 +II Other_GETS [0 0 0 0 0 0 0 0 ] 0 +II Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +II Invalidate [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +IT Load [0 0 0 0 0 0 0 0 ] 0 +IT Ifetch [0 0 0 0 0 0 0 0 ] 0 +IT Store [0 0 0 0 0 0 0 0 ] 0 +IT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +IT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +IT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +IT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +IT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +IT Invalidate [0 0 0 0 0 0 0 0 ] 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +ST Load [0 0 0 0 0 0 0 0 ] 0 +ST Ifetch [0 0 0 0 0 0 0 0 ] 0 +ST Store [0 0 0 0 0 0 0 0 ] 0 +ST L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +ST L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +ST Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETX [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETS [0 0 0 0 0 0 0 0 ] 0 +ST Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +ST Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +ST Invalidate [0 0 0 0 0 0 0 0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_demand_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_total_hw_prefetches: 0 +OT Load [0 0 0 0 0 0 0 0 ] 0 +OT Ifetch [0 0 0 0 0 0 0 0 ] 0 +OT Store [0 0 0 0 0 0 0 0 ] 0 +OT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +OT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +OT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +OT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +OT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +OT Invalidate [0 0 0 0 0 0 0 0 ] 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_LD: 60.7587% - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_type_ST: 39.2413% +MT Load [0 0 0 0 0 0 0 0 ] 0 +MT Ifetch [0 0 0 0 0 0 0 0 ] 0 +MT Store [0 0 0 0 0 0 0 0 ] 0 +MT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MT Invalidate [0 0 0 0 0 0 0 0 ] 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19454 100% - system.ruby.network.topology.ext_links1.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19454 average: 1 | standard deviation: 0 | 0 19454 ] +MMT Load [0 0 0 0 0 0 0 0 ] 0 +MMT Ifetch [0 0 0 0 0 0 0 0 ] 0 +MMT Store [0 0 0 0 0 0 0 0 ] 0 +MMT L2_Replacement [0 0 0 0 0 0 0 0 ] 0 +MMT L1_to_L2 [0 0 0 0 0 0 0 0 ] 0 +MMT Complete_L2_to_L1 [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETX [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETS [0 0 0 0 0 0 0 0 ] 0 +MMT Merged_GETS [0 0 0 0 0 0 0 0 ] 0 +MMT Other_GETS_No_Mig [0 0 0 0 0 0 0 0 ] 0 +MMT Invalidate [0 0 0 0 0 0 0 0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 19454 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.icache + system.l1_cntrl1.sequencer.icache_total_misses: 0 + system.l1_cntrl1.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl1.sequencer.icache_total_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_LD: 60.7587% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_type_ST: 39.2413% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19454 100% - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19454 average: 1 | standard deviation: 0 | 0 19454 ] +Cache Stats: system.l1_cntrl1.sequencer.dcache + system.l1_cntrl1.sequencer.dcache_total_misses: 28015 + system.l1_cntrl1.sequencer.dcache_total_demand_misses: 28015 + system.l1_cntrl1.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.dcache_total_hw_prefetches: 0 - --- L1Cache 1 --- - - Event Counts - -Load 99091 -Ifetch 0 -Store 53648 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52351 -Other_GETS 83486 -Ack 116231 -Shared_Ack 573 -Data 284 -Shared_Data 719 -Exclusive_Data 18358 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 719 -All_acks_no_sharers 18733 + system.l1_cntrl1.sequencer.dcache_request_type_LD: 37.4121% + system.l1_cntrl1.sequencer.dcache_request_type_ST: 62.5879% - - Transitions - -I Load 11820 -I Ifetch 0 <-- -I Store 6576 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- + system.l1_cntrl1.sequencer.dcache_access_mode_type_SupervisorMode: 28015 100% -S Load 1335 -S Ifetch 0 <-- -S Store 697 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 22 -S Other_GETS 20 +Cache Stats: system.l1_cntrl1.L2cacheMemory + system.l1_cntrl1.L2cacheMemory_total_misses: 28015 + system.l1_cntrl1.L2cacheMemory_total_demand_misses: 28015 + system.l1_cntrl1.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl1.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.L2cacheMemory_total_hw_prefetches: 0 -O Load 610 -O Ifetch 0 <-- -O Store 361 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 3 + system.l1_cntrl1.L2cacheMemory_request_type_LD: 37.4121% + system.l1_cntrl1.L2cacheMemory_request_type_ST: 62.5879% -M Load 19135 -M Ifetch 0 <-- -M Store 10524 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 214 -M Other_GETS 361 + system.l1_cntrl1.L2cacheMemory_access_mode_type_SupervisorMode: 28015 100% -MM Load 66191 -MM Ifetch 0 <-- -MM Store 35490 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6927 -MM Other_GETS 11231 +Cache Stats: system.l1_cntrl2.sequencer.icache + system.l1_cntrl2.sequencer.icache_total_misses: 0 + system.l1_cntrl2.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl2.sequencer.icache_total_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_hw_prefetches: 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17561 -IM Other_GETS 27274 -IM Ack 22346 -IM Data 200 -IM Exclusive_Data 7259 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 613 -SM Other_GETS 531 -SM Ack 230 -SM Data 84 +Cache Stats: system.l1_cntrl2.sequencer.dcache + system.l1_cntrl2.sequencer.dcache_total_misses: 28143 + system.l1_cntrl2.sequencer.dcache_total_demand_misses: 28143 + system.l1_cntrl2.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.dcache_total_hw_prefetches: 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 270 -OM Other_GETS 348 -OM Ack 637 -OM All_acks 0 <-- -OM All_acks_no_sharers 91 + system.l1_cntrl2.sequencer.dcache_request_type_LD: 37.949% + system.l1_cntrl2.sequencer.dcache_request_type_ST: 62.051% -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 920 -ISM All_acks_no_sharers 284 + system.l1_cntrl2.sequencer.dcache_access_mode_type_SupervisorMode: 28143 100% -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33416 -M_W All_acks_no_sharers 11099 +Cache Stats: system.l1_cntrl2.L2cacheMemory + system.l1_cntrl2.L2cacheMemory_total_misses: 28143 + system.l1_cntrl2.L2cacheMemory_total_demand_misses: 28143 + system.l1_cntrl2.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl2.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.L2cacheMemory_total_hw_prefetches: 0 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21763 -MM_W All_acks_no_sharers 7259 + system.l1_cntrl2.L2cacheMemory_request_type_LD: 37.949% + system.l1_cntrl2.L2cacheMemory_request_type_ST: 62.051% -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26744 -IS Other_GETS 43718 -IS Ack 35027 -IS Shared_Ack 279 -IS Data 0 <-- -IS Shared_Data 719 -IS Exclusive_Data 11099 + system.l1_cntrl2.L2cacheMemory_access_mode_type_SupervisorMode: 28143 100% -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1892 -SS Shared_Ack 294 -SS All_acks 719 -SS All_acks_no_sharers 0 <-- +Cache Stats: system.l1_cntrl3.sequencer.icache + system.l1_cntrl3.sequencer.icache_total_misses: 0 + system.l1_cntrl3.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl3.sequencer.icache_total_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_hw_prefetches: 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- +Cache Stats: system.l1_cntrl3.sequencer.dcache + system.l1_cntrl3.sequencer.dcache_total_misses: 28000 + system.l1_cntrl3.sequencer.dcache_total_demand_misses: 28000 + system.l1_cntrl3.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_total_hw_prefetches: 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- + system.l1_cntrl3.sequencer.dcache_request_type_LD: 37.5321% + system.l1_cntrl3.sequencer.dcache_request_type_ST: 62.4679% -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.l1_cntrl3.sequencer.dcache_access_mode_type_SupervisorMode: 28000 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Cache Stats: system.l1_cntrl3.L2cacheMemory + system.l1_cntrl3.L2cacheMemory_total_misses: 28000 + system.l1_cntrl3.L2cacheMemory_total_demand_misses: 28000 + system.l1_cntrl3.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl3.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.L2cacheMemory_total_hw_prefetches: 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_demand_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.l1_cntrl3.L2cacheMemory_request_type_LD: 37.5321% + system.l1_cntrl3.L2cacheMemory_request_type_ST: 62.4679% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_LD: 61.5325% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_type_ST: 38.4675% + system.l1_cntrl3.L2cacheMemory_access_mode_type_SupervisorMode: 28000 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19263 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19263 average: 1 | standard deviation: 0 | 0 19263 ] +Cache Stats: system.l1_cntrl4.sequencer.icache + system.l1_cntrl4.sequencer.icache_total_misses: 0 + system.l1_cntrl4.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl4.sequencer.icache_total_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_hw_prefetches: 0 -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_demand_misses: 19263 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_LD: 61.5325% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_type_ST: 38.4675% +Cache Stats: system.l1_cntrl4.sequencer.dcache + system.l1_cntrl4.sequencer.dcache_total_misses: 27967 + system.l1_cntrl4.sequencer.dcache_total_demand_misses: 27967 + system.l1_cntrl4.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19263 100% - system.ruby.network.topology.ext_links2.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19263 average: 1 | standard deviation: 0 | 0 19263 ] + system.l1_cntrl4.sequencer.dcache_request_type_LD: 37.4012% + system.l1_cntrl4.sequencer.dcache_request_type_ST: 62.5988% - --- L1Cache 2 --- - - Event Counts - -Load 98496 -Ifetch 0 -Store 52751 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52575 -Other_GETS 83453 -Ack 115139 -Shared_Ack 511 -Data 296 -Shared_Data 707 -Exclusive_Data 18174 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 707 -All_acks_no_sharers 18554 + system.l1_cntrl4.sequencer.dcache_access_mode_type_SupervisorMode: 27967 100% - - Transitions - -I Load 11853 -I Ifetch 0 <-- -I Store 6345 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- +Cache Stats: system.l1_cntrl4.L2cacheMemory + system.l1_cntrl4.L2cacheMemory_total_misses: 27967 + system.l1_cntrl4.L2cacheMemory_total_demand_misses: 27967 + system.l1_cntrl4.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl4.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl4.L2cacheMemory_total_hw_prefetches: 0 -S Load 1284 -S Ifetch 0 <-- -S Store 693 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 14 -S Other_GETS 24 + system.l1_cntrl4.L2cacheMemory_request_type_LD: 37.4012% + system.l1_cntrl4.L2cacheMemory_request_type_ST: 62.5988% -O Load 671 -O Ifetch 0 <-- -O Store 372 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 2 + system.l1_cntrl4.L2cacheMemory_access_mode_type_SupervisorMode: 27967 100% -M Load 19735 -M Ifetch 0 <-- -M Store 10526 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 246 -M Other_GETS 372 +Cache Stats: system.l1_cntrl5.sequencer.icache + system.l1_cntrl5.sequencer.icache_total_misses: 0 + system.l1_cntrl5.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl5.sequencer.icache_total_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_hw_prefetches: 0 -MM Load 64953 -MM Ifetch 0 <-- -MM Store 34815 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6748 -MM Other_GETS 11188 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17422 -IM Other_GETS 26671 -IM Ack 21637 -IM Data 202 -IM Exclusive_Data 7030 +Cache Stats: system.l1_cntrl5.sequencer.dcache + system.l1_cntrl5.sequencer.dcache_total_misses: 28030 + system.l1_cntrl5.sequencer.dcache_total_demand_misses: 28030 + system.l1_cntrl5.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.dcache_total_hw_prefetches: 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 599 -SM Other_GETS 537 -SM Ack 292 -SM Data 94 + system.l1_cntrl5.sequencer.dcache_request_type_LD: 37.7917% + system.l1_cntrl5.sequencer.dcache_request_type_ST: 62.2083% -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 288 -OM Other_GETS 352 -OM Ack 588 -OM All_acks 0 <-- -OM All_acks_no_sharers 84 + system.l1_cntrl5.sequencer.dcache_access_mode_type_SupervisorMode: 28030 100% -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 871 -ISM All_acks_no_sharers 296 +Cache Stats: system.l1_cntrl5.L2cacheMemory + system.l1_cntrl5.L2cacheMemory_total_misses: 28030 + system.l1_cntrl5.L2cacheMemory_total_demand_misses: 28030 + system.l1_cntrl5.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl5.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl5.L2cacheMemory_total_hw_prefetches: 0 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33302 -M_W All_acks_no_sharers 11144 + system.l1_cntrl5.L2cacheMemory_request_type_LD: 37.7917% + system.l1_cntrl5.L2cacheMemory_request_type_ST: 62.2083% -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21156 -MM_W All_acks_no_sharers 7030 + system.l1_cntrl5.L2cacheMemory_access_mode_type_SupervisorMode: 28030 100% -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27258 -IS Other_GETS 44307 -IS Ack 35532 -IS Shared_Ack 290 -IS Data 0 <-- -IS Shared_Data 707 -IS Exclusive_Data 11144 +Cache Stats: system.l1_cntrl6.sequencer.icache + system.l1_cntrl6.sequencer.icache_total_misses: 0 + system.l1_cntrl6.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl6.sequencer.icache_total_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_hw_prefetches: 0 -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1761 -SS Shared_Ack 221 -SS All_acks 707 -SS All_acks_no_sharers 0 <-- -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- +Cache Stats: system.l1_cntrl6.sequencer.dcache + system.l1_cntrl6.sequencer.dcache_total_misses: 28000 + system.l1_cntrl6.sequencer.dcache_total_demand_misses: 28000 + system.l1_cntrl6.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.dcache_total_hw_prefetches: 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- + system.l1_cntrl6.sequencer.dcache_request_type_LD: 37.6071% + system.l1_cntrl6.sequencer.dcache_request_type_ST: 62.3929% -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- + system.l1_cntrl6.sequencer.dcache_access_mode_type_SupervisorMode: 28000 100% -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl6.L2cacheMemory + system.l1_cntrl6.L2cacheMemory_total_misses: 28000 + system.l1_cntrl6.L2cacheMemory_total_demand_misses: 28000 + system.l1_cntrl6.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl6.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl6.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl6.L2cacheMemory_request_type_LD: 37.6071% + system.l1_cntrl6.L2cacheMemory_request_type_ST: 62.3929% -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_demand_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.l1_cntrl6.L2cacheMemory_access_mode_type_SupervisorMode: 28000 100% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_LD: 61.4134% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_type_ST: 38.5866% +Cache Stats: system.l1_cntrl7.sequencer.icache + system.l1_cntrl7.sequencer.icache_total_misses: 0 + system.l1_cntrl7.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl7.sequencer.icache_total_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19315 100% - system.ruby.network.topology.ext_links3.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19315 average: 1 | standard deviation: 0 | 0 19315 ] -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_demand_misses: 19315 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl7.sequencer.dcache + system.l1_cntrl7.sequencer.dcache_total_misses: 27964 + system.l1_cntrl7.sequencer.dcache_total_demand_misses: 27964 + system.l1_cntrl7.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_LD: 61.4134% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_type_ST: 38.5866% + system.l1_cntrl7.sequencer.dcache_request_type_LD: 37.6234% + system.l1_cntrl7.sequencer.dcache_request_type_ST: 62.3766% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19315 100% - system.ruby.network.topology.ext_links3.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19315 average: 1 | standard deviation: 0 | 0 19315 ] + system.l1_cntrl7.sequencer.dcache_access_mode_type_SupervisorMode: 27964 100% - --- L1Cache 3 --- - - Event Counts - -Load 98500 -Ifetch 0 -Store 53165 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52533 -Other_GETS 83443 -Ack 115416 -Shared_Ack 538 -Data 260 -Shared_Data 726 -Exclusive_Data 18251 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 726 -All_acks_no_sharers 18587 +Cache Stats: system.l1_cntrl7.L2cacheMemory + system.l1_cntrl7.L2cacheMemory_total_misses: 27964 + system.l1_cntrl7.L2cacheMemory_total_demand_misses: 27964 + system.l1_cntrl7.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl7.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl7.L2cacheMemory_total_hw_prefetches: 0 - - Transitions - -I Load 11862 -I Ifetch 0 <-- -I Store 6402 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- + system.l1_cntrl7.L2cacheMemory_request_type_LD: 37.6234% + system.l1_cntrl7.L2cacheMemory_request_type_ST: 62.3766% -S Load 1302 -S Ifetch 0 <-- -S Store 707 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 19 -S Other_GETS 14 + system.l1_cntrl7.L2cacheMemory_access_mode_type_SupervisorMode: 27964 100% -O Load 637 -O Ifetch 0 <-- -O Store 344 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 1 +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 -M Load 19387 -M Ifetch 0 <-- -M Store 10581 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 210 -M Other_GETS 344 -MM Load 65312 -MM Ifetch 0 <-- -MM Store 35131 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 7026 -MM Other_GETS 11007 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17035 -IM Other_GETS 26879 -IM Ack 22135 -IM Data 176 -IM Exclusive_Data 7116 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 623 -SM Other_GETS 550 -SM Ack 260 -SM Data 84 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 268 -OM Other_GETS 302 -OM Ack 532 -OM All_acks 0 <-- -OM All_acks_no_sharers 76 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 773 -ISM All_acks_no_sharers 260 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33558 -M_W All_acks_no_sharers 11135 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21088 -MM_W All_acks_no_sharers 7116 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27352 -IS Other_GETS 44346 -IS Ack 35080 -IS Shared_Ack 265 -IS Data 0 <-- -IS Shared_Data 726 -IS Exclusive_Data 11135 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1990 -SS Shared_Ack 273 -SS All_acks 726 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_demand_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_LD: 62.0061% - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_type_ST: 37.9939% - - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19411 100% - system.ruby.network.topology.ext_links4.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19411 average: 1 | standard deviation: 0 | 0 19411 ] - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_demand_misses: 19411 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_LD: 62.0061% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_type_ST: 37.9939% - - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19411 100% - system.ruby.network.topology.ext_links4.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19411 average: 1 | standard deviation: 0 | 0 19411 ] - - --- L1Cache 4 --- - - Event Counts - -Load 99038 -Ifetch 0 -Store 53408 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52611 -Other_GETS 83269 -Ack 115968 -Shared_Ack 566 -Data 266 -Shared_Data 702 -Exclusive_Data 18361 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 702 -All_acks_no_sharers 18707 - - - Transitions - -I Load 12036 -I Ifetch 0 <-- -I Store 6312 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1172 -S Ifetch 0 <-- -S Store 685 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 17 -S Other_GETS 16 - -O Load 670 -O Ifetch 0 <-- -O Store 378 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 1 - -M Load 20047 -M Ifetch 0 <-- -M Store 10741 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 380 - -MM Load 65113 -MM Ifetch 0 <-- -MM Store 35292 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6885 -MM Other_GETS 11230 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17299 -IM Other_GETS 26539 -IM Ack 21568 -IM Data 187 -IM Exclusive_Data 7028 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 606 -SM Other_GETS 507 -SM Ack 251 -SM Data 79 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 298 -OM Other_GETS 332 -OM Ack 560 -OM All_acks 0 <-- -OM All_acks_no_sharers 80 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 805 -ISM All_acks_no_sharers 266 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33929 -M_W All_acks_no_sharers 11333 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21140 -MM_W All_acks_no_sharers 7028 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27292 -IS Other_GETS 44264 -IS Ack 35919 -IS Shared_Ack 277 -IS Data 0 <-- -IS Shared_Data 702 -IS Exclusive_Data 11333 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1796 -SS Shared_Ack 289 -SS All_acks 702 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_demand_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_LD: 61.3219% - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_type_ST: 38.6781% - - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19427 100% - system.ruby.network.topology.ext_links5.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19427 average: 1 | standard deviation: 0 | 0 19427 ] - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_demand_misses: 19427 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_LD: 61.3219% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_type_ST: 38.6781% - - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19427 100% - system.ruby.network.topology.ext_links5.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19427 average: 1 | standard deviation: 0 | 0 19427 ] - - --- L1Cache 5 --- - - Event Counts - -Load 99160 -Ifetch 0 -Store 53567 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52471 -Other_GETS 83392 -Ack 116095 -Shared_Ack 541 -Data 284 -Shared_Data 711 -Exclusive_Data 18344 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 711 -All_acks_no_sharers 18714 - - - Transitions - -I Load 11913 -I Ifetch 0 <-- -I Store 6459 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1245 -S Ifetch 0 <-- -S Store 692 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 19 -S Other_GETS 19 - -O Load 710 -O Ifetch 0 <-- -O Store 363 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 3 - -M Load 19676 -M Ifetch 0 <-- -M Store 10615 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 221 -M Other_GETS 365 - -MM Load 65616 -MM Ifetch 0 <-- -MM Store 35438 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6917 -MM Other_GETS 11211 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17699 -IM Other_GETS 27330 -IM Ack 22142 -IM Data 204 -IM Exclusive_Data 7143 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 612 -SM Other_GETS 543 -SM Ack 216 -SM Data 80 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 277 -OM Other_GETS 370 -OM Ack 602 -OM All_acks 0 <-- -OM All_acks_no_sharers 86 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 875 -ISM All_acks_no_sharers 284 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33646 -M_W All_acks_no_sharers 11201 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21329 -MM_W All_acks_no_sharers 7143 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26724 -IS Other_GETS 43551 -IS Ack 35510 -IS Shared_Ack 315 -IS Data 0 <-- -IS Shared_Data 711 -IS Exclusive_Data 11201 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1775 -SS Shared_Ack 226 -SS All_acks 711 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_demand_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_LD: 61.2525% - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_type_ST: 38.7475% - - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19338 100% - system.ruby.network.topology.ext_links6.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19338 average: 1 | standard deviation: 0 | 0 19338 ] - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_demand_misses: 19338 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_LD: 61.2525% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_type_ST: 38.7475% - - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19338 100% - system.ruby.network.topology.ext_links6.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19338 average: 1 | standard deviation: 0 | 0 19338 ] - - --- L1Cache 6 --- - - Event Counts - -Load 98889 -Ifetch 0 -Store 53165 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52493 -Other_GETS 83460 -Ack 115539 -Shared_Ack 547 -Data 284 -Shared_Data 679 -Exclusive_Data 18303 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 679 -All_acks_no_sharers 18657 - - - Transitions - -I Load 11845 -I Ifetch 0 <-- -I Store 6480 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1308 -S Ifetch 0 <-- -S Store 654 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 25 -S Other_GETS 14 - -O Load 685 -O Ifetch 0 <-- -O Store 359 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 3 - -M Load 19489 -M Ifetch 0 <-- -M Store 10570 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 234 -M Other_GETS 361 - -MM Load 65562 -MM Ifetch 0 <-- -MM Store 35102 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6856 -MM Other_GETS 11206 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17237 -IM Other_GETS 26688 -IM Ack 21916 -IM Data 202 -IM Exclusive_Data 7138 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 572 -SM Other_GETS 482 -SM Ack 248 -SM Data 82 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 289 -OM Other_GETS 358 -OM Ack 490 -OM All_acks 0 <-- -OM All_acks_no_sharers 70 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 862 -ISM All_acks_no_sharers 284 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33944 -M_W All_acks_no_sharers 11165 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21506 -MM_W All_acks_no_sharers 7138 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 27278 -IS Other_GETS 44348 -IS Ack 34795 -IS Shared_Ack 261 -IS Data 0 <-- -IS Shared_Data 679 -IS Exclusive_Data 11165 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1778 -SS Shared_Ack 286 -SS All_acks 679 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_demand_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_LD: 60.9852% - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_type_ST: 39.0148% - - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 19631 100% - system.ruby.network.topology.ext_links7.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 1 count: 19631 average: 1 | standard deviation: 0 | 0 19631 ] - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_demand_misses: 19631 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_LD: 60.9852% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_type_ST: 39.0148% - - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 19631 100% - system.ruby.network.topology.ext_links7.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 1 count: 19631 average: 1 | standard deviation: 0 | 0 19631 ] - - --- L1Cache 7 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 54267 -L2_Replacement 0 -L1_to_L2 0 -L2_to_L1D 0 -L2_to_L1I 0 -Other_GETX 52326 -Other_GETS 83333 -Ack 117318 -Shared_Ack 553 -Data 310 -Shared_Data 736 -Exclusive_Data 18493 -Writeback_Ack 0 -Writeback_Nack 0 -All_acks 736 -All_acks_no_sharers 18894 - - - Transitions - -I Load 11972 -I Ifetch 0 <-- -I Store 6579 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- - -S Load 1355 -S Ifetch 0 <-- -S Store 716 -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 20 -S Other_GETS 14 - -O Load 691 -O Ifetch 0 <-- -O Store 364 -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 2 -O Other_GETS 3 - -M Load 19829 -M Ifetch 0 <-- -M Store 10657 -M L2_Replacement 0 <-- -M L1_to_L2 0 <-- -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 212 -M Other_GETS 366 - -MM Load 66154 -MM Ifetch 0 <-- -MM Store 35951 -MM L2_Replacement 0 <-- -MM L1_to_L2 0 <-- -MM L2_to_L1D 0 <-- -MM L2_to_L1I 0 <-- -MM Other_GETX 6984 -MM Other_GETS 11331 - -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 0 <-- -IM Other_GETX 17532 -IM Other_GETS 27148 -IM Ack 22400 -IM Data 215 -IM Exclusive_Data 7258 - -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 621 -SM Other_GETS 571 -SM Ack 271 -SM Data 95 - -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 273 -OM Other_GETS 352 -OM Ack 637 -OM All_acks 0 <-- -OM All_acks_no_sharers 91 - -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 950 -ISM All_acks_no_sharers 310 - -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 0 <-- -M_W Ack 33772 -M_W All_acks_no_sharers 11235 - -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 0 <-- -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 0 <-- -MM_W Ack 21787 -MM_W All_acks_no_sharers 7258 - -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 0 <-- -IS Other_GETX 26682 -IS Other_GETS 43548 -IS Ack 35649 -IS Shared_Ack 274 -IS Data 0 <-- -IS Shared_Data 736 -IS Exclusive_Data 11235 - -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 1852 -SS Shared_Ack 279 -SS All_acks 736 -SS All_acks_no_sharers 0 <-- - -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- - -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 0 <-- -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 0 <-- - -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- - -Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -2008,178 +876,282 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 2262622 -GETS 3542851 -PUT 0 -Unblock 155288 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 0 -Writeback_Exclusive_Dirty 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 2 -Memory_Ack 0 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [826938 ] 826938 +GETS [354468 ] 354468 +PUT [0 ] 0 +Unblock [0 ] 0 +UnblockS [84314 ] 84314 +UnblockM [139875 ] 139875 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [0 ] 0 +Writeback_Exclusive_Dirty [0 ] 0 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [17168 ] 17168 - Transitions - -NO GETX 59984 -NO GETS 95304 -NO PUT 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NX GETX [17168 ] 17168 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +NO GETX [122706 ] 122706 +NO GETS [1 ] 1 +NO PUT [0 ] 0 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -E GETX 2 -E GETS 0 <-- -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -NO_B GETX 2202461 -NO_B GETS 3447311 -NO_B PUT 0 <-- -NO_B Unblock 155288 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- +E GETX [1 ] 1 +E GETS [1 ] 1 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 -NO_B_W GETX 175 -NO_B_W GETS 236 -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 2 +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- +NO_B GETX [122707 ] 122707 +NO_B GETS [17168 ] 17168 +NO_B PUT [0 ] 0 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [2 ] 2 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- +NO_B_X GETX [466103 ] 466103 +NO_B_X GETS [270139 ] 270139 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [122705 ] 122705 +NO_B_X Pf_Replacement [0 ] 0 -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- +NO_B_S GETX [35862 ] 35862 +NO_B_S GETS [67146 ] 67146 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [17168 ] 17168 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- +NO_B_S_W GETX [62390 ] 62390 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [84314 ] 84314 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [17168 ] 17168 -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- +NO_B_W GETX [1 ] 1 +NO_B_W GETS [13 ] 13 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [2 ] 2 -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 -WB GETX 0 <-- -WB GETS 0 <-- -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 0 <-- -WB Writeback_Exclusive_Dirty 0 <-- -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -WB_E_W GETX 0 <-- -WB_E_W GETS 0 <-- -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 0 <-- +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [0 ] 0 +WB GETS [0 ] 0 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [0 ] 0 +WB Writeback_Exclusive_Dirty [0 ] 0 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [0 ] 0 +WB_E_W GETS [0 ] 0 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu0: completed 10000 read accesses @427647 -system.cpu1: completed 10000 read accesses @431729 -system.cpu6: completed 10000 read accesses @433789 -system.cpu7: completed 10000 read accesses @439540 -system.cpu2: completed 10000 read accesses @440839 -system.cpu5: completed 10000 read accesses @442985 -system.cpu4: completed 10000 read accesses @444200 -system.cpu3: completed 10000 read accesses @449590 -system.cpu0: completed 20000 read accesses @865314 -system.cpu6: completed 20000 read accesses @868247 -system.cpu1: completed 20000 read accesses @868279 -system.cpu4: completed 20000 read accesses @868705 -system.cpu7: completed 20000 read accesses @876211 -system.cpu3: completed 20000 read accesses @884081 -system.cpu2: completed 20000 read accesses @890953 -system.cpu5: completed 20000 read accesses @896667 -system.cpu7: completed 30000 read accesses @1294509 -system.cpu0: completed 30000 read accesses @1300229 -system.cpu4: completed 30000 read accesses @1308389 -system.cpu6: completed 30000 read accesses @1309605 -system.cpu1: completed 30000 read accesses @1314626 -system.cpu2: completed 30000 read accesses @1319614 -system.cpu3: completed 30000 read accesses @1333112 -system.cpu5: completed 30000 read accesses @1342297 -system.cpu0: completed 40000 read accesses @1732725 -system.cpu7: completed 40000 read accesses @1734274 -system.cpu6: completed 40000 read accesses @1739223 -system.cpu4: completed 40000 read accesses @1750291 -system.cpu2: completed 40000 read accesses @1757823 -system.cpu1: completed 40000 read accesses @1760314 -system.cpu3: completed 40000 read accesses @1761490 -system.cpu5: completed 40000 read accesses @1777684 -system.cpu7: completed 50000 read accesses @2168908 -system.cpu0: completed 50000 read accesses @2178119 -system.cpu3: completed 50000 read accesses @2188628 -system.cpu1: completed 50000 read accesses @2189157 -system.cpu6: completed 50000 read accesses @2193920 -system.cpu2: completed 50000 read accesses @2194930 -system.cpu4: completed 50000 read accesses @2196927 -system.cpu5: completed 50000 read accesses @2215126 -system.cpu7: completed 60000 read accesses @2604948 -system.cpu0: completed 60000 read accesses @2616657 -system.cpu4: completed 60000 read accesses @2617534 -system.cpu1: completed 60000 read accesses @2632147 -system.cpu6: completed 60000 read accesses @2638426 -system.cpu3: completed 60000 read accesses @2639965 -system.cpu2: completed 60000 read accesses @2642221 -system.cpu5: completed 60000 read accesses @2647795 -system.cpu7: completed 70000 read accesses @3047214 -system.cpu0: completed 70000 read accesses @3049033 -system.cpu4: completed 70000 read accesses @3063601 -system.cpu1: completed 70000 read accesses @3069586 -system.cpu2: completed 70000 read accesses @3071644 -system.cpu3: completed 70000 read accesses @3075127 -system.cpu6: completed 70000 read accesses @3078550 -system.cpu5: completed 70000 read accesses @3088269 -system.cpu7: completed 80000 read accesses @3486517 -system.cpu0: completed 80000 read accesses @3492714 -system.cpu4: completed 80000 read accesses @3505717 -system.cpu2: completed 80000 read accesses @3505856 -system.cpu3: completed 80000 read accesses @3506369 -system.cpu1: completed 80000 read accesses @3507148 -system.cpu6: completed 80000 read accesses @3520617 -system.cpu5: completed 80000 read accesses @3524191 -system.cpu7: completed 90000 read accesses @3917341 -system.cpu0: completed 90000 read accesses @3926523 -system.cpu4: completed 90000 read accesses @3938478 -system.cpu1: completed 90000 read accesses @3940606 -system.cpu5: completed 90000 read accesses @3950826 -system.cpu3: completed 90000 read accesses @3954179 -system.cpu6: completed 90000 read accesses @3956200 -system.cpu2: completed 90000 read accesses @3961428 -system.cpu7: completed 100000 read accesses @4339943 +system.cpu7: completed 10000 read accesses @329291 +system.cpu1: completed 10000 read accesses @329757 +system.cpu3: completed 10000 read accesses @330497 +system.cpu0: completed 10000 read accesses @330509 +system.cpu4: completed 10000 read accesses @332060 +system.cpu6: completed 10000 read accesses @333568 +system.cpu2: completed 10000 read accesses @334433 +system.cpu5: completed 10000 read accesses @335135 +system.cpu3: completed 20000 read accesses @659226 +system.cpu7: completed 20000 read accesses @659807 +system.cpu1: completed 20000 read accesses @664366 +system.cpu2: completed 20000 read accesses @664528 +system.cpu4: completed 20000 read accesses @666016 +system.cpu0: completed 20000 read accesses @666942 +system.cpu5: completed 20000 read accesses @668136 +system.cpu6: completed 20000 read accesses @670351 +system.cpu3: completed 30000 read accesses @986347 +system.cpu7: completed 30000 read accesses @993943 +system.cpu0: completed 30000 read accesses @995623 +system.cpu1: completed 30000 read accesses @995737 +system.cpu2: completed 30000 read accesses @998461 +system.cpu4: completed 30000 read accesses @999519 +system.cpu5: completed 30000 read accesses @1002067 +system.cpu6: completed 30000 read accesses @1005241 +system.cpu3: completed 40000 read accesses @1321302 +system.cpu1: completed 40000 read accesses @1327064 +system.cpu7: completed 40000 read accesses @1327199 +system.cpu0: completed 40000 read accesses @1327448 +system.cpu2: completed 40000 read accesses @1331772 +system.cpu4: completed 40000 read accesses @1333161 +system.cpu6: completed 40000 read accesses @1335046 +system.cpu5: completed 40000 read accesses @1338874 +system.cpu3: completed 50000 read accesses @1649836 +system.cpu1: completed 50000 read accesses @1660499 +system.cpu2: completed 50000 read accesses @1661834 +system.cpu7: completed 50000 read accesses @1663128 +system.cpu0: completed 50000 read accesses @1666375 +system.cpu4: completed 50000 read accesses @1667661 +system.cpu6: completed 50000 read accesses @1668836 +system.cpu5: completed 50000 read accesses @1673164 +system.cpu3: completed 60000 read accesses @1982027 +system.cpu1: completed 60000 read accesses @1993619 +system.cpu0: completed 60000 read accesses @1997073 +system.cpu7: completed 60000 read accesses @1997156 +system.cpu2: completed 60000 read accesses @1998573 +system.cpu4: completed 60000 read accesses @2001381 +system.cpu6: completed 60000 read accesses @2002211 +system.cpu5: completed 60000 read accesses @2005496 +system.cpu3: completed 70000 read accesses @2304178 +system.cpu1: completed 70000 read accesses @2324207 +system.cpu0: completed 70000 read accesses @2327147 +system.cpu7: completed 70000 read accesses @2328033 +system.cpu2: completed 70000 read accesses @2333147 +system.cpu4: completed 70000 read accesses @2333305 +system.cpu5: completed 70000 read accesses @2335251 +system.cpu6: completed 70000 read accesses @2339353 +system.cpu3: completed 80000 read accesses @2634076 +system.cpu1: completed 80000 read accesses @2657807 +system.cpu2: completed 80000 read accesses @2662450 +system.cpu0: completed 80000 read accesses @2662916 +system.cpu7: completed 80000 read accesses @2664258 +system.cpu4: completed 80000 read accesses @2667182 +system.cpu5: completed 80000 read accesses @2667901 +system.cpu6: completed 80000 read accesses @2674630 +system.cpu3: completed 90000 read accesses @2965765 +system.cpu1: completed 90000 read accesses @2989913 +system.cpu2: completed 90000 read accesses @2990917 +system.cpu7: completed 90000 read accesses @2994294 +system.cpu5: completed 90000 read accesses @2998903 +system.cpu4: completed 90000 read accesses @2998952 +system.cpu0: completed 90000 read accesses @2999994 +system.cpu6: completed 90000 read accesses @3004409 +system.cpu3: completed 100000 read accesses @3296793 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:59:19 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:40:34 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 14:43:33 +M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates +M5 started Aug 5 2010 14:45:03 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 4339943 because maximum number of loads reached +Exiting @ tick 3296793 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 339964 # Number of bytes of host memory used -host_seconds 41.43 # Real time elapsed on the host -host_tick_rate 104755 # Simulator tick rate (ticks/s) +host_mem_usage 342064 # Number of bytes of host memory used +host_seconds 38.58 # Real time elapsed on the host +host_tick_rate 85448 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.004340 # Number of seconds simulated -sim_ticks 4339943 # Number of ticks simulated +sim_seconds 0.003297 # Number of seconds simulated +sim_ticks 3296793 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99313 # number of read accesses completed -system.cpu0.num_writes 53538 # number of write accesses completed +system.cpu0.num_reads 99094 # number of read accesses completed +system.cpu0.num_writes 53667 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99089 # number of read accesses completed -system.cpu1.num_writes 53648 # number of write accesses completed +system.cpu1.num_reads 99231 # number of read accesses completed +system.cpu1.num_writes 53354 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 98494 # number of read accesses completed -system.cpu2.num_writes 52751 # number of write accesses completed +system.cpu2.num_reads 99267 # number of read accesses completed +system.cpu2.num_writes 53239 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 98499 # number of read accesses completed -system.cpu3.num_writes 53164 # number of write accesses completed +system.cpu3.num_reads 100000 # number of read accesses completed +system.cpu3.num_writes 53108 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99037 # number of read accesses completed -system.cpu4.num_writes 53407 # number of write accesses completed +system.cpu4.num_reads 98925 # number of read accesses completed +system.cpu4.num_writes 53556 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99159 # number of read accesses completed -system.cpu5.num_writes 53566 # number of write accesses completed +system.cpu5.num_reads 99000 # number of read accesses completed +system.cpu5.num_writes 53064 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 98888 # number of read accesses completed -system.cpu6.num_writes 53164 # number of write accesses completed +system.cpu6.num_reads 98939 # number of read accesses completed +system.cpu6.num_writes 53474 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 100000 # number of read accesses completed -system.cpu7.num_writes 54267 # number of write accesses completed +system.cpu7.num_reads 99084 # number of read accesses completed +system.cpu7.num_writes 53310 # number of write accesses completed ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,13 +5,14 @@ [system] type=System -children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 funcmem physmem ruby +children=cpu0 cpu1 cpu2 cpu3 cpu4 cpu5 cpu6 cpu7 dir_cntrl0 funcmem l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 l1_cntrl4 l1_cntrl5 l1_cntrl6 l1_cntrl7 physmem ruby mem_mode=timing physmem=system.physmem [system.cpu0] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -22,11 +23,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[0] -test=system.ruby.network.topology.ext_links0.ext_node.sequencer.port[0] +test=system.l1_cntrl0.sequencer.port[0] [system.cpu1] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -37,11 +39,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[1] -test=system.ruby.network.topology.ext_links1.ext_node.sequencer.port[0] +test=system.l1_cntrl1.sequencer.port[0] [system.cpu2] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -52,11 +55,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[2] -test=system.ruby.network.topology.ext_links2.ext_node.sequencer.port[0] +test=system.l1_cntrl2.sequencer.port[0] [system.cpu3] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -67,11 +71,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[3] -test=system.ruby.network.topology.ext_links3.ext_node.sequencer.port[0] +test=system.l1_cntrl3.sequencer.port[0] [system.cpu4] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -82,11 +87,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[4] -test=system.ruby.network.topology.ext_links4.ext_node.sequencer.port[0] +test=system.l1_cntrl4.sequencer.port[0] [system.cpu5] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -97,11 +103,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[5] -test=system.ruby.network.topology.ext_links5.ext_node.sequencer.port[0] +test=system.l1_cntrl5.sequencer.port[0] [system.cpu6] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -112,11 +119,12 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[6] -test=system.ruby.network.topology.ext_links6.ext_node.sequencer.port[0] +test=system.l1_cntrl6.sequencer.port[0] [system.cpu7] type=MemTest atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -127,7 +135,48 @@ progress_interval=10000 trace_addr=0 functional=system.funcmem.port[7] -test=system.ruby.network.topology.ext_links7.ext_node.sequencer.port[0] +test=system.l1_cntrl7.sequencer.port[0] + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 [system.funcmem] type=PhysicalMemory @@ -139,6 +188,278 @@ zero=false port=system.cpu0.functional system.cpu1.functional system.cpu2.functional system.cpu3.functional system.cpu4.functional system.cpu5.functional system.cpu6.functional system.cpu7.functional +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl0.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=0 +physMemPort=system.physmem.port[0] +port=system.cpu0.test + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl1.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl1.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl1.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=1 +physMemPort=system.physmem.port[1] +port=system.cpu1.test + +[system.l1_cntrl1.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl2.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl2.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl2.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=2 +physMemPort=system.physmem.port[2] +port=system.cpu2.test + +[system.l1_cntrl2.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl3.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl3.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl3.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=3 +physMemPort=system.physmem.port[3] +port=system.cpu3.test + +[system.l1_cntrl3.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl4] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl4.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl4.sequencer +transitions_per_cycle=32 +version=4 + +[system.l1_cntrl4.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl4.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl4.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=4 +physMemPort=system.physmem.port[4] +port=system.cpu4.test + +[system.l1_cntrl4.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl5] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl5.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl5.sequencer +transitions_per_cycle=32 +version=5 + +[system.l1_cntrl5.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl5.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl5.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=5 +physMemPort=system.physmem.port[5] +port=system.cpu5.test + +[system.l1_cntrl5.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl6] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl6.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl6.sequencer +transitions_per_cycle=32 +version=6 + +[system.l1_cntrl6.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl6.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl6.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=6 +physMemPort=system.physmem.port[6] +port=system.cpu6.test + +[system.l1_cntrl6.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl7] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl7.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl7.sequencer +transitions_per_cycle=32 +version=7 + +[system.l1_cntrl7.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl7.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl7.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=false +version=7 +physMemPort=system.physmem.port[7] +port=system.cpu7.test + +[system.l1_cntrl7.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -147,7 +468,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links1.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links2.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links3.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links4.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links5.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links6.ext_node.sequencer.physMemPort system.ruby.network.topology.ext_links7.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort system.l1_cntrl1.sequencer.physMemPort system.l1_cntrl2.sequencer.physMemPort system.l1_cntrl3.sequencer.physMemPort system.l1_cntrl4.sequencer.physMemPort system.l1_cntrl5.sequencer.physMemPort system.l1_cntrl6.sequencer.physMemPort system.l1_cntrl7.sequencer.physMemPort [system.ruby] type=RubySystem @@ -188,395 +509,82 @@ children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 ext_links5 ext_links6 ext_links7 ext_links8 int_links0 int_links1 int_links2 int_links3 int_links4 int_links5 int_links6 int_links7 int_links8 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 system.ruby.network.topology.ext_links5 system.ruby.network.topology.ext_links6 system.ruby.network.topology.ext_links7 system.ruby.network.topology.ext_links8 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 system.ruby.network.topology.int_links5 system.ruby.network.topology.int_links6 system.ruby.network.topology.int_links7 system.ruby.network.topology.int_links8 +name=Crossbar num_int_nodes=10 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=0 -physMemPort=system.physmem.port[0] -port=system.cpu0.test - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l1_cntrl1 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links1.ext_node.sequencer -transitions_per_cycle=32 -version=1 - -[system.ruby.network.topology.ext_links1.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links1.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=1 -physMemPort=system.physmem.port[1] -port=system.cpu1.test - -[system.ruby.network.topology.ext_links1.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.l1_cntrl2 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links2.ext_node.sequencer -transitions_per_cycle=32 -version=2 - -[system.ruby.network.topology.ext_links2.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links2.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=2 -physMemPort=system.physmem.port[2] -port=system.cpu2.test - -[system.ruby.network.topology.ext_links2.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links3] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links3.ext_node +ext_node=system.l1_cntrl3 int_node=3 latency=1 weight=1 -[system.ruby.network.topology.ext_links3.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links3.ext_node.sequencer -transitions_per_cycle=32 -version=3 - -[system.ruby.network.topology.ext_links3.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links3.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=3 -physMemPort=system.physmem.port[3] -port=system.cpu3.test - -[system.ruby.network.topology.ext_links3.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links4] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links4.ext_node +ext_node=system.l1_cntrl4 int_node=4 latency=1 weight=1 -[system.ruby.network.topology.ext_links4.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links4.ext_node.sequencer -transitions_per_cycle=32 -version=4 - -[system.ruby.network.topology.ext_links4.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links4.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=4 -physMemPort=system.physmem.port[4] -port=system.cpu4.test - -[system.ruby.network.topology.ext_links4.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links5] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links5.ext_node +ext_node=system.l1_cntrl5 int_node=5 latency=1 weight=1 -[system.ruby.network.topology.ext_links5.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links5.ext_node.sequencer -transitions_per_cycle=32 -version=5 - -[system.ruby.network.topology.ext_links5.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links5.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=5 -physMemPort=system.physmem.port[5] -port=system.cpu5.test - -[system.ruby.network.topology.ext_links5.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links6] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links6.ext_node +ext_node=system.l1_cntrl6 int_node=6 latency=1 weight=1 -[system.ruby.network.topology.ext_links6.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links6.ext_node.sequencer -transitions_per_cycle=32 -version=6 - -[system.ruby.network.topology.ext_links6.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links6.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=6 -physMemPort=system.physmem.port[6] -port=system.cpu6.test - -[system.ruby.network.topology.ext_links6.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links7] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links7.ext_node +ext_node=system.l1_cntrl7 int_node=7 latency=1 weight=1 -[system.ruby.network.topology.ext_links7.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links7.ext_node.sequencer -transitions_per_cycle=32 -version=7 - -[system.ruby.network.topology.ext_links7.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links7.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=false -version=7 -physMemPort=system.physmem.port[7] -port=system.cpu7.test - -[system.ruby.network.topology.ext_links7.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links8] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links8.ext_node +ext_node=system.dir_cntrl0 int_node=8 latency=1 weight=1 -[system.ruby.network.topology.ext_links8.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links8.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links8.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links8.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 15:36:18 +Real time: Aug/05/2010 10:12:12 Profiler Stats -------------- -Elapsed_time_in_seconds: 77 -Elapsed_time_in_minutes: 1.28333 -Elapsed_time_in_hours: 0.0213889 -Elapsed_time_in_days: 0.000891204 +Elapsed_time_in_seconds: 75 +Elapsed_time_in_minutes: 1.25 +Elapsed_time_in_hours: 0.0208333 +Elapsed_time_in_days: 0.000868056 -Virtual_time_in_seconds: 76.96 -Virtual_time_in_minutes: 1.28267 -Virtual_time_in_hours: 0.0213778 -Virtual_time_in_days: 0.000890741 +Virtual_time_in_seconds: 75.01 +Virtual_time_in_minutes: 1.25017 +Virtual_time_in_hours: 0.0208361 +Virtual_time_in_days: 0.000868171 -Ruby_current_time: 11048357 +Ruby_current_time: 11050902 Ruby_start_time: 0 -Ruby_cycles: 11048357 +Ruby_cycles: 11050902 -mbytes_resident: 30.7461 -mbytes_total: 331.699 -resident_ratio: 0.0927045 +mbytes_resident: 32.0586 +mbytes_total: 332.785 +resident_ratio: 0.0963459 -ruby_cycles_executed: [ 11048358 11048358 11048358 11048358 11048358 11048358 11048358 11048358 ] +ruby_cycles_executed: [ 11050903 11050903 11050903 11050903 11050903 11050903 11050903 11050903 ] Busy Controller Counts: L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 L1Cache-4:0 L1Cache-5:0 L1Cache-6:0 L1Cache-7:0 @@ -66,13 +66,32 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1227589 average: 1.875 | standard deviation: 0.330723 | 0 153452 1074137 ] +sequencer_requests_outstanding: [binsize: 1 max: 2 count: 1227865 average: 1.93749 | standard deviation: 0.242073 | 0 76749 1151116 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 4 max: 549 count: 1227573 average: 141.876 | standard deviation: 1.82074 | 14 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 25 294 5125 80867 1141231 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 4 max: 549 count: 798072 average: 141.875 | standard deviation: 1.78629 | 9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 14 192 3318 52570 741960 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 4 max: 531 count: 429501 average: 141.879 | standard deviation: 1.88309 | 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 102 1807 28297 399271 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 4 max: 520 count: 1227850 average: 141.94 | standard deviation: 1.74453 | 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 287 4805 76599 1146110 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 2 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 520 count: 798081 average: 141.941 | standard deviation: 1.85597 | 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 180 3163 49978 744722 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 359 count: 429769 average: 141.939 | standard deviation: 1.51603 | 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 17 90 322 1320 5345 21276 85759 315629 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 7 average: 3 | standard deviation: 0 | 0 0 0 7 ] +miss_latency_Directory: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_L1Cache_wCC: [binsize: 4 max: 520 count: 1227841 average: 141.941 | standard deviation: 1.69872 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 23 287 4805 76599 1146110 2 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 6 average: 0 | standard deviation: 0 | 6 ] +miss_latency_wCC_first_response_to_completion: [binsize: 4 max: 467 count: 6 average: 362 | standard deviation: 76.7203 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +imcomplete_wCC_Times: 1227835 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 2 average: 0 | standard deviation: 0 | 2 ] +miss_latency_dir_first_response_to_completion: [binsize: 2 max: 359 count: 2 average: 304 | standard deviation: 77.7817 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 0 +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 5 average: 3 | standard deviation: 0 | 0 0 0 5 ] +miss_latency_LD_Directory: [binsize: 2 max: 249 count: 1 average: 249 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache_wCC: [binsize: 4 max: 520 count: 798075 average: 141.941 | standard deviation: 1.81916 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 18 180 3163 49978 744722 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 2 average: 3 | standard deviation: 0 | 0 0 0 2 ] +miss_latency_ST_Directory: [binsize: 2 max: 359 count: 1 average: 359 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache_wCC: [binsize: 2 max: 287 count: 429766 average: 141.939 | standard deviation: 1.44875 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 4 17 90 322 1320 5345 21276 85759 315629 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -86,11 +105,11 @@ Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] -Total_nonPF_delay_cycles: [binsize: 4 max: 152 count: 2455118 average: 47.4372 | standard deviation: 47.4484 | 1227560 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] +Total_delay_cycles: [binsize: 4 max: 123 count: 2455686 average: 47.4686 | standard deviation: 47.4796 | 1227845 0 0 0 1 0 0 0 0 1 1 0 0 2 0 0 0 2 0 12 125 2432 38182 611799 575279 1 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +Total_nonPF_delay_cycles: [binsize: 4 max: 123 count: 2455686 average: 47.4686 | standard deviation: 47.4796 | 1227845 0 0 0 1 0 0 0 0 1 1 0 0 2 0 0 0 2 0 12 125 2432 38182 611799 575279 1 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227559 average: 0 | standard deviation: 0 | 1227559 ] - virtual_network_2_delay_cycles: [binsize: 4 max: 152 count: 1227559 average: 94.8743 | standard deviation: 1.46213 | 1 0 1 0 0 0 0 1 0 0 0 1 0 1 0 1 1 0 0 9 138 2625 40347 646958 537470 2 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 1227843 average: 0 | standard deviation: 0 | 1227843 ] + virtual_network_2_delay_cycles: [binsize: 4 max: 123 count: 1227843 average: 94.9372 | standard deviation: 1.44474 | 2 0 0 0 1 0 0 0 0 1 1 0 0 2 0 0 0 2 0 12 125 2432 38182 611799 575279 1 2 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -102,9 +121,9 @@ Resource Usage -------------- page_size: 4096 -user_time: 76 +user_time: 74 system_time: 0 -page_reclaims: 8851 +page_reclaims: 9310 page_faults: 0 swaps: 0 block_inputs: 0 @@ -113,552 +132,276 @@ Network Stats ------------- +total_msg_count_Control: 3683571 29468568 +total_msg_count_Response_Data: 3683529 265214088 +total_msg_count_Writeback_Control: 3683559 29468472 +total_msgs: 11050659 total_bytes: 324151128 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.434016 +links_utilized_percent_switch_0: 0.434018 links_utilized_percent_switch_0_link_0: 0.173607 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.694428 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 153483 1227864 [ 0 0 0 153483 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 153483 1227864 [ 0 0 153483 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.434016 +links_utilized_percent_switch_1: 0.434015 links_utilized_percent_switch_1_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.434016 - links_utilized_percent_switch_2_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.694425 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.434015 + links_utilized_percent_switch_2_link_0: 0.173607 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 2 switch_3_outlinks: 2 -links_utilized_percent_switch_3: 0.434016 +links_utilized_percent_switch_3: 0.434015 links_utilized_percent_switch_3_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.694425 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_4_inlinks: 2 switch_4_outlinks: 2 -links_utilized_percent_switch_4: 0.434014 +links_utilized_percent_switch_4: 0.434015 links_utilized_percent_switch_4_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_4_link_1: 0.694421 bw: 160000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_4_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_4_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_5_inlinks: 2 switch_5_outlinks: 2 -links_utilized_percent_switch_5: 0.434016 - links_utilized_percent_switch_5_link_0: 0.173606 bw: 640000 base_latency: 1 - links_utilized_percent_switch_5_link_1: 0.694425 bw: 160000 base_latency: 1 +links_utilized_percent_switch_5: 0.434015 + links_utilized_percent_switch_5_link_0: 0.173607 bw: 640000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_5_link_0_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Control: 153447 1227576 [ 0 0 153447 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_5_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_6_inlinks: 2 switch_6_outlinks: 2 -links_utilized_percent_switch_6: 0.434013 - links_utilized_percent_switch_6_link_0: 0.173605 bw: 640000 base_latency: 1 - links_utilized_percent_switch_6_link_1: 0.694421 bw: 160000 base_latency: 1 +links_utilized_percent_switch_6: 0.434015 + links_utilized_percent_switch_6_link_0: 0.173606 bw: 640000 base_latency: 1 + links_utilized_percent_switch_6_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_6_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_6_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_0_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_6_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_7_inlinks: 2 switch_7_outlinks: 2 -links_utilized_percent_switch_7: 0.434013 - links_utilized_percent_switch_7_link_0: 0.173605 bw: 640000 base_latency: 1 - links_utilized_percent_switch_7_link_1: 0.694421 bw: 160000 base_latency: 1 +links_utilized_percent_switch_7: 0.434015 + links_utilized_percent_switch_7_link_0: 0.173606 bw: 640000 base_latency: 1 + links_utilized_percent_switch_7_link_1: 0.694424 bw: 160000 base_latency: 1 - outgoing_messages_switch_7_link_0_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_0_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Control: 153446 1227568 [ 0 0 153446 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_7_link_1_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_0_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Control: 153482 1227856 [ 0 0 153482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_7_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 switch_8_inlinks: 2 switch_8_outlinks: 2 links_utilized_percent_switch_8: 0.347219 - links_utilized_percent_switch_8_link_0: 0.138886 bw: 640000 base_latency: 1 + links_utilized_percent_switch_8_link_0: 0.138887 bw: 640000 base_latency: 1 links_utilized_percent_switch_8_link_1: 0.555552 bw: 160000 base_latency: 1 - outgoing_messages_switch_8_link_0_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Control: 1227857 9822856 [ 0 0 1227857 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_8_link_1_Response_Data: 2 144 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_8_link_1_Writeback_Control: 1227569 9820552 [ 0 0 0 1227569 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_1_Writeback_Control: 1227853 9822824 [ 0 0 0 1227853 0 0 0 0 0 0 ] base_latency: 1 switch_9_inlinks: 9 switch_9_outlinks: 9 links_utilized_percent_switch_9: 0.678994 - links_utilized_percent_switch_9_link_0: 0.694429 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_1: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_2: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_3: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_4: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_5: 0.694425 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_6: 0.694421 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_7: 0.69442 bw: 160000 base_latency: 1 - links_utilized_percent_switch_9_link_8: 0.555545 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_0: 0.694428 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_1: 0.694424 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_2: 0.694428 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_3: 0.694423 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_4: 0.694423 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_5: 0.694428 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_6: 0.694423 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_7: 0.694423 bw: 160000 base_latency: 1 + links_utilized_percent_switch_9_link_8: 0.555546 bw: 160000 base_latency: 1 - outgoing_messages_switch_9_link_0_Response_Data: 153446 11048112 [ 0 0 0 0 153446 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_0_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_1_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_2_Writeback_Control: 153447 1227576 [ 0 0 0 153447 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_3_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_4_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Response_Data: 153445 11048040 [ 0 0 0 0 153445 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_5_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_6_Writeback_Control: 153446 1227568 [ 0 0 0 153446 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Response_Data: 153444 11047968 [ 0 0 0 0 153444 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_7_Writeback_Control: 153445 1227560 [ 0 0 0 153445 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_9_link_8_Control: 1227573 9820584 [ 0 0 1227573 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_0_Writeback_Control: 153483 1227864 [ 0 0 0 153483 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_1_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_2_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_3_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_4_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Response_Data: 153481 11050632 [ 0 0 0 0 153481 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_5_Writeback_Control: 153482 1227856 [ 0 0 0 153482 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_6_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Response_Data: 153480 11050560 [ 0 0 0 0 153480 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_7_Writeback_Control: 153481 1227848 [ 0 0 0 153481 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_9_link_8_Control: 1227857 9822856 [ 0 0 1227857 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 153483 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 153483 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 65.0211% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 34.9789% + system.l1_cntrl0.sequencer.icache_request_type_LD: 64.873% + system.l1_cntrl0.sequencer.icache_request_type_ST: 35.127% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 153483 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 99774 -Ifetch 0 -Store 53675 -Data 153446 -Fwd_GETX 153446 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 +Load [99792 100001 99630 99910 99573 99721 99800 99666 ] 798093 +Ifetch [0 0 0 0 0 0 0 0 ] 0 +Store [53690 53481 53852 53572 53915 53763 53682 53816 ] 429771 +Data [153480 153481 153480 153480 153481 153480 153481 153480 ] 1227843 +Fwd_GETX [153480 153481 153480 153480 153481 153480 153481 153480 ] 1227843 +Inv [0 0 0 0 0 0 0 0 ] 0 +Replacement [0 0 0 0 0 0 0 0 ] 0 +Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 - Transitions - -I Load 99773 -I Ifetch 0 <-- -I Store 53674 -I Inv 0 <-- -I Replacement 0 <-- +I Load [99792 100001 99630 99910 99569 99720 99800 99666 ] 798088 +I Ifetch [0 0 0 0 0 0 0 0 ] 0 +I Store [53690 53481 53852 53572 53914 53762 53682 53816 ] 429769 +I Inv [0 0 0 0 0 0 0 0 ] 0 +I Replacement [0 0 0 0 0 0 0 0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -M Load 1 -M Ifetch 0 <-- -M Store 1 -M Fwd_GETX 153446 -M Inv 0 <-- -M Replacement 0 <-- +M Load [0 0 0 0 4 1 0 0 ] 5 +M Ifetch [0 0 0 0 0 0 0 0 ] 0 +M Store [0 0 0 0 1 1 0 0 ] 2 +M Fwd_GETX [153480 153481 153480 153480 153481 153480 153481 153480 ] 1227843 +M Inv [0 0 0 0 0 0 0 0 ] 0 +M Replacement [0 0 0 0 0 0 0 0 ] 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 +MI Inv [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Ack [0 0 0 0 0 0 0 0 ] 0 +MI Writeback_Nack [0 0 0 0 0 0 0 0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 0 0 0 0 0 0 0 ] 0 -IS Data 99773 +IS Data [99790 100000 99629 99908 99567 99718 99799 99665 ] 798076 -IM Data 53673 +IM Data [53690 53481 53851 53572 53914 53762 53682 53815 ] 429767 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.sequencer.icache - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl1.sequencer.icache + system.l1_cntrl1.sequencer.icache_total_misses: 153482 + system.l1_cntrl1.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl1.sequencer.icache_total_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl1.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_LD: 64.6816% - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_type_ST: 35.3184% + system.l1_cntrl1.sequencer.icache_request_type_LD: 64.9718% + system.l1_cntrl1.sequencer.icache_request_type_ST: 35.0282% - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links1.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] + system.l1_cntrl1.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% - --- L1Cache 1 --- - - Event Counts - -Load 99260 -Ifetch 0 -Store 54199 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 +Cache Stats: system.l1_cntrl2.sequencer.icache + system.l1_cntrl2.sequencer.icache_total_misses: 153482 + system.l1_cntrl2.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl2.sequencer.icache_total_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl2.sequencer.icache_total_hw_prefetches: 0 - - Transitions - -I Load 99252 -I Ifetch 0 <-- -I Store 54195 -I Inv 0 <-- -I Replacement 0 <-- + system.l1_cntrl2.sequencer.icache_request_type_LD: 65.0239% + system.l1_cntrl2.sequencer.icache_request_type_ST: 34.9761% -II Writeback_Nack 0 <-- + system.l1_cntrl2.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% -M Load 8 -M Ifetch 0 <-- -M Store 4 -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- +Cache Stats: system.l1_cntrl3.sequencer.icache + system.l1_cntrl3.sequencer.icache_total_misses: 153482 + system.l1_cntrl3.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl3.sequencer.icache_total_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl3.sequencer.icache_total_hw_prefetches: 0 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- + system.l1_cntrl3.sequencer.icache_request_type_LD: 64.9366% + system.l1_cntrl3.sequencer.icache_request_type_ST: 35.0634% -MII Fwd_GETX 0 <-- + system.l1_cntrl3.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% -IS Data 99251 +Cache Stats: system.l1_cntrl4.sequencer.icache + system.l1_cntrl4.sequencer.icache_total_misses: 153482 + system.l1_cntrl4.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl4.sequencer.icache_total_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_total_hw_prefetches: 0 -IM Data 54194 + system.l1_cntrl4.sequencer.icache_request_type_LD: 65.0187% + system.l1_cntrl4.sequencer.icache_request_type_ST: 34.9813% -Cache Stats: system.ruby.network.topology.ext_links2.ext_node.sequencer.icache - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_total_hw_prefetches: 0 + system.l1_cntrl4.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_LD: 64.8804% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_type_ST: 35.1196% +Cache Stats: system.l1_cntrl5.sequencer.icache + system.l1_cntrl5.sequencer.icache_total_misses: 153482 + system.l1_cntrl5.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl5.sequencer.icache_total_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl5.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links2.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] + system.l1_cntrl5.sequencer.icache_request_type_LD: 65.1549% + system.l1_cntrl5.sequencer.icache_request_type_ST: 34.8451% - --- L1Cache 2 --- - - Event Counts - -Load 99557 -Ifetch 0 -Store 53890 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 + system.l1_cntrl5.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% - - Transitions - -I Load 99557 -I Ifetch 0 <-- -I Store 53890 -I Inv 0 <-- -I Replacement 0 <-- +Cache Stats: system.l1_cntrl6.sequencer.icache + system.l1_cntrl6.sequencer.icache_total_misses: 153482 + system.l1_cntrl6.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl6.sequencer.icache_total_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl6.sequencer.icache_total_hw_prefetches: 0 -II Writeback_Nack 0 <-- + system.l1_cntrl6.sequencer.icache_request_type_LD: 64.9131% + system.l1_cntrl6.sequencer.icache_request_type_ST: 35.0869% -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- + system.l1_cntrl6.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- +Cache Stats: system.l1_cntrl7.sequencer.icache + system.l1_cntrl7.sequencer.icache_total_misses: 153482 + system.l1_cntrl7.sequencer.icache_total_demand_misses: 153482 + system.l1_cntrl7.sequencer.icache_total_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl7.sequencer.icache_total_hw_prefetches: 0 -MII Fwd_GETX 0 <-- + system.l1_cntrl7.sequencer.icache_request_type_LD: 65.0956% + system.l1_cntrl7.sequencer.icache_request_type_ST: 34.9044% -IS Data 99555 + system.l1_cntrl7.sequencer.icache_access_mode_type_SupervisorMode: 153482 100% -IM Data 53890 - -Cache Stats: system.ruby.network.topology.ext_links3.ext_node.sequencer.icache - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_LD: 65.1254% - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_type_ST: 34.8746% - - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links3.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 3 --- - - Event Counts - -Load 99933 -Ifetch 0 -Store 53514 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99933 -I Ifetch 0 <-- -I Store 53514 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99932 - -IM Data 53513 - -Cache Stats: system.ruby.network.topology.ext_links4.ext_node.sequencer.icache - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_LD: 65.1702% - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_type_ST: 34.8298% - - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links4.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] - - --- L1Cache 4 --- - - Event Counts - -Load 100001 -Ifetch 0 -Store 53445 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 100001 -I Ifetch 0 <-- -I Store 53445 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 100000 - -IM Data 53445 - -Cache Stats: system.ruby.network.topology.ext_links5.ext_node.sequencer.icache - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_misses: 153447 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_demand_misses: 153447 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_LD: 65.1137% - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_type_ST: 34.8863% - - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153447 100% - system.ruby.network.topology.ext_links5.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153447 average: 1 | standard deviation: 0 | 0 153447 ] - - --- L1Cache 5 --- - - Event Counts - -Load 99915 -Ifetch 0 -Store 53532 -Data 153445 -Fwd_GETX 153445 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99915 -I Ifetch 0 <-- -I Store 53532 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153445 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99914 - -IM Data 53531 - -Cache Stats: system.ruby.network.topology.ext_links6.ext_node.sequencer.icache - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_LD: 65.0203% - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_type_ST: 34.9797% - - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links6.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] - - --- L1Cache 6 --- - - Event Counts - -Load 99771 -Ifetch 0 -Store 53675 -Data 153444 -Fwd_GETX 153444 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99771 -I Ifetch 0 <-- -I Store 53675 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153444 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99770 - -IM Data 53674 - -Cache Stats: system.ruby.network.topology.ext_links7.ext_node.sequencer.icache - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_misses: 153446 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_demand_misses: 153446 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_total_hw_prefetches: 0 - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_LD: 65.0841% - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_type_ST: 34.9159% - - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 153446 100% - system.ruby.network.topology.ext_links7.ext_node.sequencer.icache_request_size: [binsize: 1 max: 1 count: 153446 average: 1 | standard deviation: 0 | 0 153446 ] - - --- L1Cache 7 --- - - Event Counts - -Load 99869 -Ifetch 0 -Store 53577 -Data 153444 -Fwd_GETX 153444 -Inv 0 -Replacement 0 -Writeback_Ack 0 -Writeback_Nack 0 - - - Transitions - -I Load 99869 -I Ifetch 0 <-- -I Store 53577 -I Inv 0 <-- -I Replacement 0 <-- - -II Writeback_Nack 0 <-- - -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M Fwd_GETX 153444 -M Inv 0 <-- -M Replacement 0 <-- - -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Nack 0 <-- - -MII Fwd_GETX 0 <-- - -IS Data 99868 - -IM Data 53576 - -Memory controller: system.ruby.network.topology.ext_links8.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 2 memory_reads: 2 memory_writes: 0 @@ -678,70 +421,69 @@ memory_stalls_for_read_read_turnaround: 0 accesses_per_bank: 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 1227984 -GETS 0 -PUTX 0 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 2 -Memory_Ack 0 +GETX [1228268 ] 1228268 +GETS [0 ] 0 +PUTX [0 ] 0 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [2 ] 2 +Memory_Ack [0 ] 0 - Transitions - -I GETX 2 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [2 ] 2 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -M GETX 1227571 -M PUTX 0 <-- -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [1227855 ] 1227855 +M PUTX [0 ] 0 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 -IM GETX 411 -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 2 +IM GETX [411 ] 411 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [2 ] 2 -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 0 <-- +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [0 ] 0 -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu5: completed 10000 read accesses @1097795 -system.cpu1: completed 10000 read accesses @1101449 -system.cpu4: completed 10000 read accesses @1103861 -system.cpu3: completed 10000 read accesses @1104689 -system.cpu6: completed 10000 read accesses @1107767 -system.cpu2: completed 10000 read accesses @1108955 -system.cpu0: completed 10000 read accesses @1109315 -system.cpu7: completed 10000 read accesses @1115237 -system.cpu5: completed 20000 read accesses @2202527 -system.cpu4: completed 20000 read accesses @2207405 -system.cpu3: completed 20000 read accesses @2212049 -system.cpu2: completed 20000 read accesses @2212140 -system.cpu6: completed 20000 read accesses @2216495 -system.cpu1: completed 20000 read accesses @2218601 -system.cpu7: completed 20000 read accesses @2229041 -system.cpu0: completed 20000 read accesses @2229203 -system.cpu5: completed 30000 read accesses @3306575 -system.cpu4: completed 30000 read accesses @3307925 -system.cpu3: completed 30000 read accesses @3308753 -system.cpu7: completed 30000 read accesses @3318869 -system.cpu6: completed 30000 read accesses @3328247 -system.cpu2: completed 30000 read accesses @3331884 -system.cpu1: completed 30000 read accesses @3338201 -system.cpu0: completed 30000 read accesses @3340343 -system.cpu5: completed 40000 read accesses @4410227 -system.cpu4: completed 40000 read accesses @4410389 -system.cpu3: completed 40000 read accesses @4424177 -system.cpu7: completed 40000 read accesses @4429973 -system.cpu0: completed 40000 read accesses @4435175 -system.cpu6: completed 40000 read accesses @4438199 -system.cpu2: completed 40000 read accesses @4444715 -system.cpu1: completed 40000 read accesses @4450313 -system.cpu5: completed 50000 read accesses @5504627 -system.cpu4: completed 50000 read accesses @5519333 -system.cpu3: completed 50000 read accesses @5526785 -system.cpu7: completed 50000 read accesses @5529377 -system.cpu0: completed 50000 read accesses @5532419 -system.cpu6: completed 50000 read accesses @5546639 -system.cpu2: completed 50000 read accesses @5560715 -system.cpu1: completed 50000 read accesses @5569193 -system.cpu5: completed 60000 read accesses @6620303 -system.cpu4: completed 60000 read accesses @6630005 -system.cpu3: completed 60000 read accesses @6637745 -system.cpu7: completed 60000 read accesses @6639905 -system.cpu0: completed 60000 read accesses @6649463 -system.cpu6: completed 60000 read accesses @6652055 -system.cpu2: completed 60000 read accesses @6667068 -system.cpu1: completed 60000 read accesses @6690378 -system.cpu5: completed 70000 read accesses @7728671 -system.cpu3: completed 70000 read accesses @7729265 -system.cpu4: completed 70000 read accesses @7729373 -system.cpu7: completed 70000 read accesses @7748849 -system.cpu6: completed 70000 read accesses @7751423 -system.cpu0: completed 70000 read accesses @7760099 -system.cpu2: completed 70000 read accesses @7781196 -system.cpu1: completed 70000 read accesses @7788377 -system.cpu4: completed 80000 read accesses @8833637 -system.cpu3: completed 80000 read accesses @8841377 -system.cpu5: completed 80000 read accesses @8845283 -system.cpu7: completed 80000 read accesses @8850647 -system.cpu0: completed 80000 read accesses @8859269 -system.cpu6: completed 80000 read accesses @8861015 -system.cpu2: completed 80000 read accesses @8880203 -system.cpu1: completed 80000 read accesses @8893866 -system.cpu4: completed 90000 read accesses @9931349 -system.cpu7: completed 90000 read accesses @9951959 -system.cpu5: completed 90000 read accesses @9952175 -system.cpu3: completed 90000 read accesses @9957341 -system.cpu6: completed 90000 read accesses @9967079 -system.cpu0: completed 90000 read accesses @9971795 -system.cpu2: completed 90000 read accesses @9992027 -system.cpu1: completed 90000 read accesses @10012745 -system.cpu4: completed 100000 read accesses @11048357 +system.cpu5: completed 10000 read accesses @1100070 +system.cpu0: completed 10000 read accesses @1100862 +system.cpu3: completed 10000 read accesses @1101618 +system.cpu2: completed 10000 read accesses @1104192 +system.cpu7: completed 10000 read accesses @1106388 +system.cpu6: completed 10000 read accesses @1108314 +system.cpu1: completed 10000 read accesses @1111320 +system.cpu4: completed 10000 read accesses @1126260 +system.cpu3: completed 20000 read accesses @2202984 +system.cpu1: completed 20000 read accesses @2206764 +system.cpu2: completed 20000 read accesses @2214864 +system.cpu6: completed 20000 read accesses @2214882 +system.cpu5: completed 20000 read accesses @2216592 +system.cpu7: completed 20000 read accesses @2217060 +system.cpu0: completed 20000 read accesses @2219454 +system.cpu4: completed 20000 read accesses @2221290 +system.cpu3: completed 30000 read accesses @3305250 +system.cpu2: completed 30000 read accesses @3311478 +system.cpu5: completed 30000 read accesses @3315510 +system.cpu1: completed 30000 read accesses @3320172 +system.cpu4: completed 30000 read accesses @3321738 +system.cpu6: completed 30000 read accesses @3324834 +system.cpu0: completed 30000 read accesses @3325518 +system.cpu7: completed 30000 read accesses @3329316 +system.cpu3: completed 40000 read accesses @4412466 +system.cpu5: completed 40000 read accesses @4417632 +system.cpu2: completed 40000 read accesses @4422240 +system.cpu4: completed 40000 read accesses @4423716 +system.cpu0: completed 40000 read accesses @4432014 +system.cpu1: completed 40000 read accesses @4434588 +system.cpu7: completed 40000 read accesses @4434588 +system.cpu6: completed 40000 read accesses @4448664 +system.cpu3: completed 50000 read accesses @5516946 +system.cpu2: completed 50000 read accesses @5517414 +system.cpu5: completed 50000 read accesses @5521824 +system.cpu1: completed 50000 read accesses @5537898 +system.cpu7: completed 50000 read accesses @5539284 +system.cpu4: completed 50000 read accesses @5542218 +system.cpu0: completed 50000 read accesses @5550174 +system.cpu6: completed 50000 read accesses @5551560 +system.cpu2: completed 60000 read accesses @6627222 +system.cpu5: completed 60000 read accesses @6631200 +system.cpu3: completed 60000 read accesses @6633234 +system.cpu7: completed 60000 read accesses @6637716 +system.cpu1: completed 60000 read accesses @6651018 +system.cpu0: completed 60000 read accesses @6656526 +system.cpu6: completed 60000 read accesses @6658200 +system.cpu4: completed 60000 read accesses @6658452 +system.cpu5: completed 70000 read accesses @7738038 +system.cpu3: completed 70000 read accesses @7742520 +system.cpu2: completed 70000 read accesses @7742934 +system.cpu7: completed 70000 read accesses @7746156 +system.cpu1: completed 70000 read accesses @7748604 +system.cpu0: completed 70000 read accesses @7758271 +system.cpu6: completed 70000 read accesses @7758648 +system.cpu4: completed 70000 read accesses @7762554 +system.cpu5: completed 80000 read accesses @8838486 +system.cpu7: completed 80000 read accesses @8851284 +system.cpu2: completed 80000 read accesses @8855280 +system.cpu3: completed 80000 read accesses @8857800 +system.cpu1: completed 80000 read accesses @8860842 +system.cpu4: completed 80000 read accesses @8869194 +system.cpu6: completed 80000 read accesses @8874216 +system.cpu0: completed 80000 read accesses @8875711 +system.cpu5: completed 90000 read accesses @9952128 +system.cpu7: completed 90000 read accesses @9956052 +system.cpu2: completed 90000 read accesses @9965286 +system.cpu1: completed 90000 read accesses @9968778 +system.cpu4: completed 90000 read accesses @9973764 +system.cpu3: completed 90000 read accesses @9976914 +system.cpu6: completed 90000 read accesses @9982872 +system.cpu0: completed 90000 read accesses @9996463 +system.cpu5: completed 100000 read accesses @11050902 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/simout Wed Aug 11 14:38:35 2010 -0700 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 15:34:55 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 15:35:01 -M5 executing on cabr0210 +M5 compiled Aug 4 2010 17:29:21 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:10:57 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 11048357 because maximum number of loads reached +Exiting @ tick 11050902 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest-ruby/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,34 +1,34 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 339664 # Number of bytes of host memory used -host_seconds 76.81 # Real time elapsed on the host -host_tick_rate 143842 # Simulator tick rate (ticks/s) +host_mem_usage 340776 # Number of bytes of host memory used +host_seconds 74.82 # Real time elapsed on the host +host_tick_rate 147706 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.011048 # Number of seconds simulated -sim_ticks 11048357 # Number of ticks simulated +sim_seconds 0.011051 # Number of seconds simulated +sim_ticks 11050902 # Number of ticks simulated system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99774 # number of read accesses completed -system.cpu0.num_writes 53674 # number of write accesses completed +system.cpu0.num_reads 99571 # number of read accesses completed +system.cpu0.num_writes 53915 # number of write accesses completed system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99259 # number of read accesses completed -system.cpu1.num_writes 54198 # number of write accesses completed +system.cpu1.num_reads 99719 # number of read accesses completed +system.cpu1.num_writes 53763 # number of write accesses completed system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99555 # number of read accesses completed -system.cpu2.num_writes 53890 # number of write accesses completed +system.cpu2.num_reads 99799 # number of read accesses completed +system.cpu2.num_writes 53682 # number of write accesses completed system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99932 # number of read accesses completed -system.cpu3.num_writes 53513 # number of write accesses completed +system.cpu3.num_reads 99665 # number of read accesses completed +system.cpu3.num_writes 53815 # number of write accesses completed system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 100000 # number of read accesses completed -system.cpu4.num_writes 53445 # number of write accesses completed +system.cpu4.num_reads 99790 # number of read accesses completed +system.cpu4.num_writes 53690 # number of write accesses completed system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99914 # number of read accesses completed -system.cpu5.num_writes 53531 # number of write accesses completed +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 53481 # number of write accesses completed system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 99770 # number of read accesses completed -system.cpu6.num_writes 53674 # number of write accesses completed +system.cpu6.num_reads 99629 # number of read accesses completed +system.cpu6.num_writes 53851 # number of write accesses completed system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99868 # number of read accesses completed -system.cpu7.num_writes 53576 # number of write accesses completed +system.cpu7.num_reads 99908 # number of read accesses completed +system.cpu7.num_writes 53572 # number of write accesses completed ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -13,6 +13,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -60,6 +61,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -107,6 +109,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -154,6 +157,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -201,6 +205,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -248,6 +253,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -295,6 +301,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 @@ -342,6 +349,7 @@ type=MemTest children=l1c atomic=false +is_dma=false max_loads=100000 memory_size=65536 percent_dest_unaligned=50 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest/simerr --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simerr Wed Aug 11 14:38:35 2010 -0700 @@ -1,74 +1,74 @@ -system.cpu3: completed 10000 read accesses @26226880 -system.cpu6: completed 10000 read accesses @26416342 -system.cpu2: completed 10000 read accesses @26427251 -system.cpu5: completed 10000 read accesses @26798889 -system.cpu0: completed 10000 read accesses @26886521 -system.cpu7: completed 10000 read accesses @27109446 -system.cpu1: completed 10000 read accesses @27197408 -system.cpu4: completed 10000 read accesses @27318359 -system.cpu3: completed 20000 read accesses @53279230 -system.cpu6: completed 20000 read accesses @53417084 -system.cpu2: completed 20000 read accesses @53757092 -system.cpu0: completed 20000 read accesses @53888320 -system.cpu5: completed 20000 read accesses @53947132 -system.cpu4: completed 20000 read accesses @54390092 -system.cpu1: completed 20000 read accesses @54397720 -system.cpu7: completed 20000 read accesses @54632966 -system.cpu6: completed 30000 read accesses @80144176 -system.cpu3: completed 30000 read accesses @80518264 -system.cpu0: completed 30000 read accesses @80638600 -system.cpu5: completed 30000 read accesses @80869702 -system.cpu1: completed 30000 read accesses @81289158 -system.cpu2: completed 30000 read accesses @81358716 -system.cpu7: completed 30000 read accesses @81981296 -system.cpu4: completed 30000 read accesses @82043104 -system.cpu6: completed 40000 read accesses @107087547 -system.cpu0: completed 40000 read accesses @107662142 -system.cpu3: completed 40000 read accesses @107722516 -system.cpu5: completed 40000 read accesses @107884124 -system.cpu1: completed 40000 read accesses @107981413 -system.cpu7: completed 40000 read accesses @108415286 -system.cpu2: completed 40000 read accesses @108655120 -system.cpu4: completed 40000 read accesses @109427858 -system.cpu6: completed 50000 read accesses @133583246 -system.cpu0: completed 50000 read accesses @133832383 -system.cpu5: completed 50000 read accesses @134755386 -system.cpu1: completed 50000 read accesses @134792594 -system.cpu7: completed 50000 read accesses @134914312 -system.cpu3: completed 50000 read accesses @134993978 -system.cpu2: completed 50000 read accesses @135362549 -system.cpu4: completed 50000 read accesses @135394370 -system.cpu0: completed 60000 read accesses @160410176 -system.cpu6: completed 60000 read accesses @160667590 -system.cpu7: completed 60000 read accesses @161466346 -system.cpu1: completed 60000 read accesses @161592434 -system.cpu5: completed 60000 read accesses @161656374 -system.cpu4: completed 60000 read accesses @161882626 -system.cpu2: completed 60000 read accesses @162062631 -system.cpu3: completed 60000 read accesses @162154299 -system.cpu6: completed 70000 read accesses @187592265 -system.cpu1: completed 70000 read accesses @188138542 -system.cpu7: completed 70000 read accesses @188373105 -system.cpu0: completed 70000 read accesses @188690782 -system.cpu3: completed 70000 read accesses @189309687 -system.cpu2: completed 70000 read accesses @189360790 -system.cpu4: completed 70000 read accesses @189391126 -system.cpu5: completed 70000 read accesses @189902895 -system.cpu6: completed 80000 read accesses @214739574 -system.cpu1: completed 80000 read accesses @215665444 -system.cpu0: completed 80000 read accesses @216021457 -system.cpu7: completed 80000 read accesses @216394344 -system.cpu3: completed 80000 read accesses @216537382 -system.cpu4: completed 80000 read accesses @216775798 -system.cpu2: completed 80000 read accesses @216868662 -system.cpu5: completed 80000 read accesses @217401619 -system.cpu6: completed 90000 read accesses @241415090 -system.cpu1: completed 90000 read accesses @242558992 -system.cpu0: completed 90000 read accesses @242897388 -system.cpu7: completed 90000 read accesses @243372191 -system.cpu3: completed 90000 read accesses @243630762 -system.cpu5: completed 90000 read accesses @243633950 -system.cpu4: completed 90000 read accesses @243710816 -system.cpu2: completed 90000 read accesses @243974160 -system.cpu6: completed 100000 read accesses @268915439 +system.cpu5: completed 10000 read accesses @26695905 +system.cpu1: completed 10000 read accesses @26791606 +system.cpu0: completed 10000 read accesses @26792650 +system.cpu4: completed 10000 read accesses @26942582 +system.cpu7: completed 10000 read accesses @27101805 +system.cpu2: completed 10000 read accesses @27218798 +system.cpu6: completed 10000 read accesses @27391241 +system.cpu3: completed 10000 read accesses @27569488 +system.cpu1: completed 20000 read accesses @53349763 +system.cpu5: completed 20000 read accesses @53503744 +system.cpu0: completed 20000 read accesses @53714174 +system.cpu7: completed 20000 read accesses @53950546 +system.cpu2: completed 20000 read accesses @54185930 +system.cpu6: completed 20000 read accesses @54225484 +system.cpu4: completed 20000 read accesses @54276231 +system.cpu3: completed 20000 read accesses @54597598 +system.cpu6: completed 30000 read accesses @80866924 +system.cpu7: completed 30000 read accesses @80945592 +system.cpu1: completed 30000 read accesses @81027764 +system.cpu5: completed 30000 read accesses @81035060 +system.cpu3: completed 30000 read accesses @81318103 +system.cpu0: completed 30000 read accesses @81377684 +system.cpu2: completed 30000 read accesses @81429000 +system.cpu4: completed 30000 read accesses @81820011 +system.cpu5: completed 40000 read accesses @106813760 +system.cpu2: completed 40000 read accesses @106974444 +system.cpu1: completed 40000 read accesses @106993530 +system.cpu7: completed 40000 read accesses @107261306 +system.cpu0: completed 40000 read accesses @107310319 +system.cpu6: completed 40000 read accesses @107652944 +system.cpu4: completed 40000 read accesses @107852182 +system.cpu3: completed 40000 read accesses @108023308 +system.cpu5: completed 50000 read accesses @133853751 +system.cpu1: completed 50000 read accesses @134086054 +system.cpu2: completed 50000 read accesses @134273902 +system.cpu7: completed 50000 read accesses @134574750 +system.cpu6: completed 50000 read accesses @134577823 +system.cpu4: completed 50000 read accesses @134778033 +system.cpu0: completed 50000 read accesses @134896821 +system.cpu3: completed 50000 read accesses @135759299 +system.cpu5: completed 60000 read accesses @161211555 +system.cpu2: completed 60000 read accesses @161581369 +system.cpu1: completed 60000 read accesses @161831828 +system.cpu6: completed 60000 read accesses @161942121 +system.cpu4: completed 60000 read accesses @162215822 +system.cpu7: completed 60000 read accesses @162487402 +system.cpu0: completed 60000 read accesses @162758928 +system.cpu3: completed 60000 read accesses @162827113 +system.cpu5: completed 70000 read accesses @188493937 +system.cpu4: completed 70000 read accesses @189035964 +system.cpu2: completed 70000 read accesses @189157397 +system.cpu1: completed 70000 read accesses @189252661 +system.cpu6: completed 70000 read accesses @189257028 +system.cpu7: completed 70000 read accesses @189348164 +system.cpu0: completed 70000 read accesses @189769120 +system.cpu3: completed 70000 read accesses @191028989 +system.cpu5: completed 80000 read accesses @215328997 +system.cpu7: completed 80000 read accesses @216072978 +system.cpu4: completed 80000 read accesses @216240482 +system.cpu1: completed 80000 read accesses @216413258 +system.cpu2: completed 80000 read accesses @216551338 +system.cpu0: completed 80000 read accesses @216884718 +system.cpu6: completed 80000 read accesses @216894493 +system.cpu3: completed 80000 read accesses @218108705 +system.cpu5: completed 90000 read accesses @242508064 +system.cpu7: completed 90000 read accesses @242698389 +system.cpu4: completed 90000 read accesses @242967798 +system.cpu0: completed 90000 read accesses @243529194 +system.cpu2: completed 90000 read accesses @243598064 +system.cpu1: completed 90000 read accesses @243621284 +system.cpu6: completed 90000 read accesses @244529131 +system.cpu3: completed 90000 read accesses @246008618 +system.cpu5: completed 100000 read accesses @269223994 hack: be nice to actually delete the event here diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest/simout --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/simout Wed Aug 11 14:38:35 2010 -0700 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,11 +7,11 @@ All Rights Reserved -M5 compiled Feb 24 2010 23:12:40 -M5 revision 1a33ca29ec29 6980 default share-aware-test-update.patch tip qtip -M5 started Feb 25 2010 02:22:18 -M5 executing on SC2B0619 +M5 compiled Aug 4 2010 17:29:21 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:10:56 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest -re tests/run.py build/ALPHA_SE/tests/fast/quick/50.memtest/alpha/linux/memtest Global frequency set at 1000000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 268915439 because maximum number of loads reached +Exiting @ tick 269223994 because maximum number of loads reached diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt --- a/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/50.memtest/ref/alpha/linux/memtest/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,623 +1,623 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 316880 # Number of bytes of host memory used -host_seconds 287.16 # Real time elapsed on the host -host_tick_rate 936456 # Simulator tick rate (ticks/s) +host_mem_usage 327884 # Number of bytes of host memory used +host_seconds 215.72 # Real time elapsed on the host +host_tick_rate 1248021 # Simulator tick rate (ticks/s) sim_freq 1000000000000 # Frequency of simulated ticks sim_seconds 0.000269 # Number of seconds simulated -sim_ticks 268915439 # Number of ticks simulated -system.cpu0.l1c.ReadReq_accesses 45167 # number of ReadReq accesses(hits+misses) -system.cpu0.l1c.ReadReq_avg_miss_latency 34969.384548 # average ReadReq miss latency -system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 33965.516508 # average ReadReq mshr miss latency +sim_ticks 269223994 # Number of ticks simulated +system.cpu0.l1c.ReadReq_accesses 44597 # number of ReadReq accesses(hits+misses) +system.cpu0.l1c.ReadReq_avg_miss_latency 35021.258089 # average ReadReq miss latency +system.cpu0.l1c.ReadReq_avg_mshr_miss_latency 34017.390307 # average ReadReq mshr miss latency system.cpu0.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu0.l1c.ReadReq_hits 7762 # number of ReadReq hits -system.cpu0.l1c.ReadReq_miss_latency 1308029829 # number of ReadReq miss cycles -system.cpu0.l1c.ReadReq_miss_rate 0.828149 # miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_misses 37405 # number of ReadReq misses -system.cpu0.l1c.ReadReq_mshr_miss_latency 1270480145 # number of ReadReq MSHR miss cycles -system.cpu0.l1c.ReadReq_mshr_miss_rate 0.828149 # mshr miss rate for ReadReq accesses -system.cpu0.l1c.ReadReq_mshr_misses 37405 # number of ReadReq MSHR misses -system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 823463344 # number of ReadReq MSHR uncacheable cycles -system.cpu0.l1c.WriteReq_accesses 24274 # number of WriteReq accesses(hits+misses) -system.cpu0.l1c.WriteReq_avg_miss_latency 48866.153026 # average WriteReq miss latency -system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 47862.280113 # average WriteReq mshr miss latency +system.cpu0.l1c.ReadReq_hits 7416 # number of ReadReq hits +system.cpu0.l1c.ReadReq_miss_latency 1302125397 # number of ReadReq miss cycles +system.cpu0.l1c.ReadReq_miss_rate 0.833711 # miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_misses 37181 # number of ReadReq misses +system.cpu0.l1c.ReadReq_mshr_miss_latency 1264800589 # number of ReadReq MSHR miss cycles +system.cpu0.l1c.ReadReq_mshr_miss_rate 0.833711 # mshr miss rate for ReadReq accesses +system.cpu0.l1c.ReadReq_mshr_misses 37181 # number of ReadReq MSHR misses +system.cpu0.l1c.ReadReq_mshr_uncacheable_latency 826768479 # number of ReadReq MSHR uncacheable cycles +system.cpu0.l1c.WriteReq_accesses 24074 # number of WriteReq accesses(hits+misses) +system.cpu0.l1c.WriteReq_avg_miss_latency 49364.188581 # average WriteReq miss latency +system.cpu0.l1c.WriteReq_avg_mshr_miss_latency 48360.315635 # average WriteReq mshr miss latency system.cpu0.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu0.l1c.WriteReq_hits 912 # number of WriteReq hits -system.cpu0.l1c.WriteReq_miss_latency 1141611067 # number of WriteReq miss cycles -system.cpu0.l1c.WriteReq_miss_rate 0.962429 # miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_misses 23362 # number of WriteReq misses -system.cpu0.l1c.WriteReq_mshr_miss_latency 1118158588 # number of WriteReq MSHR miss cycles -system.cpu0.l1c.WriteReq_mshr_miss_rate 0.962429 # mshr miss rate for WriteReq accesses -system.cpu0.l1c.WriteReq_mshr_misses 23362 # number of WriteReq MSHR misses -system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 529803827 # number of WriteReq MSHR uncacheable cycles -system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3772.150399 # average number of cycles each access was blocked +system.cpu0.l1c.WriteReq_hits 832 # number of WriteReq hits +system.cpu0.l1c.WriteReq_miss_latency 1147322471 # number of WriteReq miss cycles +system.cpu0.l1c.WriteReq_miss_rate 0.965440 # miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_misses 23242 # number of WriteReq misses +system.cpu0.l1c.WriteReq_mshr_miss_latency 1123990456 # number of WriteReq MSHR miss cycles +system.cpu0.l1c.WriteReq_mshr_miss_rate 0.965440 # mshr miss rate for WriteReq accesses +system.cpu0.l1c.WriteReq_mshr_misses 23242 # number of WriteReq MSHR misses +system.cpu0.l1c.WriteReq_mshr_uncacheable_latency 523151149 # number of WriteReq MSHR uncacheable cycles +system.cpu0.l1c.avg_blocked_cycles::no_mshrs 3789.531715 # average number of cycles each access was blocked system.cpu0.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu0.l1c.avg_refs 0.412252 # Average number of references to valid blocks. -system.cpu0.l1c.blocked::no_mshrs 69914 # number of cycles access was blocked +system.cpu0.l1c.avg_refs 0.409166 # Average number of references to valid blocks. +system.cpu0.l1c.blocked::no_mshrs 69635 # number of cycles access was blocked system.cpu0.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu0.l1c.blocked_cycles::no_mshrs 263726123 # number of cycles access was blocked +system.cpu0.l1c.blocked_cycles::no_mshrs 263884041 # number of cycles access was blocked system.cpu0.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu0.l1c.cache_copies 0 # number of cache copies performed -system.cpu0.l1c.demand_accesses 69441 # number of demand (read+write) accesses -system.cpu0.l1c.demand_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.demand_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency -system.cpu0.l1c.demand_hits 8674 # number of demand (read+write) hits -system.cpu0.l1c.demand_miss_latency 2449640896 # number of demand (read+write) miss cycles -system.cpu0.l1c.demand_miss_rate 0.875088 # miss rate for demand accesses -system.cpu0.l1c.demand_misses 60767 # number of demand (read+write) misses +system.cpu0.l1c.demand_accesses 68671 # number of demand (read+write) accesses +system.cpu0.l1c.demand_avg_miss_latency 40538.335865 # average overall miss latency +system.cpu0.l1c.demand_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency +system.cpu0.l1c.demand_hits 8248 # number of demand (read+write) hits +system.cpu0.l1c.demand_miss_latency 2449447868 # number of demand (read+write) miss cycles +system.cpu0.l1c.demand_miss_rate 0.879891 # miss rate for demand accesses +system.cpu0.l1c.demand_misses 60423 # number of demand (read+write) misses system.cpu0.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu0.l1c.demand_mshr_miss_latency 2388638733 # number of demand (read+write) MSHR miss cycles -system.cpu0.l1c.demand_mshr_miss_rate 0.875088 # mshr miss rate for demand accesses -system.cpu0.l1c.demand_mshr_misses 60767 # number of demand (read+write) MSHR misses +system.cpu0.l1c.demand_mshr_miss_latency 2388791045 # number of demand (read+write) MSHR miss cycles +system.cpu0.l1c.demand_mshr_miss_rate 0.879891 # mshr miss rate for demand accesses +system.cpu0.l1c.demand_mshr_misses 60423 # number of demand (read+write) MSHR misses system.cpu0.l1c.fast_writes 0 # number of fast writes performed system.cpu0.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu0.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu0.l1c.occ_%::0 0.679849 # Average percentage of cache occupancy -system.cpu0.l1c.occ_%::1 -0.004028 # Average percentage of cache occupancy -system.cpu0.l1c.occ_blocks::0 348.082504 # Average occupied blocks per context -system.cpu0.l1c.occ_blocks::1 -2.062462 # Average occupied blocks per context -system.cpu0.l1c.overall_accesses 69441 # number of overall (read+write) accesses -system.cpu0.l1c.overall_avg_miss_latency 40312.026198 # average overall miss latency -system.cpu0.l1c.overall_avg_mshr_miss_latency 39308.156285 # average overall mshr miss latency +system.cpu0.l1c.occ_%::0 0.675030 # Average percentage of cache occupancy +system.cpu0.l1c.occ_%::1 -0.001774 # Average percentage of cache occupancy +system.cpu0.l1c.occ_blocks::0 345.615536 # Average occupied blocks per context +system.cpu0.l1c.occ_blocks::1 -0.908352 # Average occupied blocks per context +system.cpu0.l1c.overall_accesses 68671 # number of overall (read+write) accesses +system.cpu0.l1c.overall_avg_miss_latency 40538.335865 # average overall miss latency +system.cpu0.l1c.overall_avg_mshr_miss_latency 39534.466097 # average overall mshr miss latency system.cpu0.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu0.l1c.overall_hits 8674 # number of overall hits -system.cpu0.l1c.overall_miss_latency 2449640896 # number of overall miss cycles -system.cpu0.l1c.overall_miss_rate 0.875088 # miss rate for overall accesses -system.cpu0.l1c.overall_misses 60767 # number of overall misses +system.cpu0.l1c.overall_hits 8248 # number of overall hits +system.cpu0.l1c.overall_miss_latency 2449447868 # number of overall miss cycles +system.cpu0.l1c.overall_miss_rate 0.879891 # miss rate for overall accesses +system.cpu0.l1c.overall_misses 60423 # number of overall misses system.cpu0.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu0.l1c.overall_mshr_miss_latency 2388638733 # number of overall MSHR miss cycles -system.cpu0.l1c.overall_mshr_miss_rate 0.875088 # mshr miss rate for overall accesses -system.cpu0.l1c.overall_mshr_misses 60767 # number of overall MSHR misses -system.cpu0.l1c.overall_mshr_uncacheable_latency 1353267171 # number of overall MSHR uncacheable cycles +system.cpu0.l1c.overall_mshr_miss_latency 2388791045 # number of overall MSHR miss cycles +system.cpu0.l1c.overall_mshr_miss_rate 0.879891 # mshr miss rate for overall accesses +system.cpu0.l1c.overall_mshr_misses 60423 # number of overall MSHR misses +system.cpu0.l1c.overall_mshr_uncacheable_latency 1349919628 # number of overall MSHR uncacheable cycles system.cpu0.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu0.l1c.replacements 28158 # number of replacements -system.cpu0.l1c.sampled_refs 28502 # Sample count of references to valid blocks. +system.cpu0.l1c.replacements 27529 # number of replacements +system.cpu0.l1c.sampled_refs 27886 # Sample count of references to valid blocks. system.cpu0.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu0.l1c.tagsinuse 346.020042 # Cycle average of tags in use -system.cpu0.l1c.total_refs 11750 # Total number of references to valid blocks. +system.cpu0.l1c.tagsinuse 344.707183 # Cycle average of tags in use +system.cpu0.l1c.total_refs 11410 # Total number of references to valid blocks. system.cpu0.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu0.l1c.writebacks 11054 # number of writebacks +system.cpu0.l1c.writebacks 10821 # number of writebacks system.cpu0.num_copies 0 # number of copy accesses completed -system.cpu0.num_reads 99578 # number of read accesses completed -system.cpu0.num_writes 53795 # number of write accesses completed -system.cpu1.l1c.ReadReq_accesses 44697 # number of ReadReq accesses(hits+misses) -system.cpu1.l1c.ReadReq_avg_miss_latency 35164.953290 # average ReadReq miss latency -system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 34161.031796 # average ReadReq mshr miss latency +system.cpu0.num_reads 99231 # number of read accesses completed +system.cpu0.num_writes 53409 # number of write accesses completed +system.cpu1.l1c.ReadReq_accesses 44579 # number of ReadReq accesses(hits+misses) +system.cpu1.l1c.ReadReq_avg_miss_latency 34889.637670 # average ReadReq miss latency +system.cpu1.l1c.ReadReq_avg_mshr_miss_latency 33885.824425 # average ReadReq mshr miss latency system.cpu1.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu1.l1c.ReadReq_hits 7617 # number of ReadReq hits -system.cpu1.l1c.ReadReq_miss_latency 1303916468 # number of ReadReq miss cycles -system.cpu1.l1c.ReadReq_miss_rate 0.829586 # miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_misses 37080 # number of ReadReq misses -system.cpu1.l1c.ReadReq_mshr_miss_latency 1266691059 # number of ReadReq MSHR miss cycles -system.cpu1.l1c.ReadReq_mshr_miss_rate 0.829586 # mshr miss rate for ReadReq accesses -system.cpu1.l1c.ReadReq_mshr_misses 37080 # number of ReadReq MSHR misses -system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 820775277 # number of ReadReq MSHR uncacheable cycles -system.cpu1.l1c.WriteReq_accesses 24304 # number of WriteReq accesses(hits+misses) -system.cpu1.l1c.WriteReq_avg_miss_latency 48948.902781 # average WriteReq miss latency -system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 47945.115747 # average WriteReq mshr miss latency +system.cpu1.l1c.ReadReq_hits 7552 # number of ReadReq hits +system.cpu1.l1c.ReadReq_miss_latency 1291858614 # number of ReadReq miss cycles +system.cpu1.l1c.ReadReq_miss_rate 0.830593 # miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_misses 37027 # number of ReadReq misses +system.cpu1.l1c.ReadReq_mshr_miss_latency 1254690421 # number of ReadReq MSHR miss cycles +system.cpu1.l1c.ReadReq_mshr_miss_rate 0.830593 # mshr miss rate for ReadReq accesses +system.cpu1.l1c.ReadReq_mshr_misses 37027 # number of ReadReq MSHR misses +system.cpu1.l1c.ReadReq_mshr_uncacheable_latency 827526553 # number of ReadReq MSHR uncacheable cycles +system.cpu1.l1c.WriteReq_accesses 24391 # number of WriteReq accesses(hits+misses) +system.cpu1.l1c.WriteReq_avg_miss_latency 49206.403643 # average WriteReq miss latency +system.cpu1.l1c.WriteReq_avg_mshr_miss_latency 48202.444762 # average WriteReq mshr miss latency system.cpu1.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu1.l1c.WriteReq_hits 934 # number of WriteReq hits -system.cpu1.l1c.WriteReq_miss_latency 1143935858 # number of WriteReq miss cycles -system.cpu1.l1c.WriteReq_miss_rate 0.961570 # miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_misses 23370 # number of WriteReq misses -system.cpu1.l1c.WriteReq_mshr_miss_latency 1120477355 # number of WriteReq MSHR miss cycles -system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961570 # mshr miss rate for WriteReq accesses -system.cpu1.l1c.WriteReq_mshr_misses 23370 # number of WriteReq MSHR misses -system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 526051093 # number of WriteReq MSHR uncacheable cycles -system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3775.982019 # average number of cycles each access was blocked +system.cpu1.l1c.WriteReq_hits 947 # number of WriteReq hits +system.cpu1.l1c.WriteReq_miss_latency 1153594927 # number of WriteReq miss cycles +system.cpu1.l1c.WriteReq_miss_rate 0.961174 # miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_misses 23444 # number of WriteReq misses +system.cpu1.l1c.WriteReq_mshr_miss_latency 1130058115 # number of WriteReq MSHR miss cycles +system.cpu1.l1c.WriteReq_mshr_miss_rate 0.961174 # mshr miss rate for WriteReq accesses +system.cpu1.l1c.WriteReq_mshr_misses 23444 # number of WriteReq MSHR misses +system.cpu1.l1c.WriteReq_mshr_uncacheable_latency 533892016 # number of WriteReq MSHR uncacheable cycles +system.cpu1.l1c.avg_blocked_cycles::no_mshrs 3771.501135 # average number of cycles each access was blocked system.cpu1.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu1.l1c.avg_refs 0.415709 # Average number of references to valid blocks. -system.cpu1.l1c.blocked::no_mshrs 69517 # number of cycles access was blocked +system.cpu1.l1c.avg_refs 0.414445 # Average number of references to valid blocks. +system.cpu1.l1c.blocked::no_mshrs 69628 # number of cycles access was blocked system.cpu1.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu1.l1c.blocked_cycles::no_mshrs 262494942 # number of cycles access was blocked +system.cpu1.l1c.blocked_cycles::no_mshrs 262602081 # number of cycles access was blocked system.cpu1.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu1.l1c.cache_copies 0 # number of cache copies performed -system.cpu1.l1c.demand_accesses 69001 # number of demand (read+write) accesses -system.cpu1.l1c.demand_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.demand_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency -system.cpu1.l1c.demand_hits 8551 # number of demand (read+write) hits -system.cpu1.l1c.demand_miss_latency 2447852326 # number of demand (read+write) miss cycles -system.cpu1.l1c.demand_miss_rate 0.876074 # miss rate for demand accesses -system.cpu1.l1c.demand_misses 60450 # number of demand (read+write) misses +system.cpu1.l1c.demand_accesses 68970 # number of demand (read+write) accesses +system.cpu1.l1c.demand_avg_miss_latency 40440.104199 # average overall miss latency +system.cpu1.l1c.demand_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency +system.cpu1.l1c.demand_hits 8499 # number of demand (read+write) hits +system.cpu1.l1c.demand_miss_latency 2445453541 # number of demand (read+write) miss cycles +system.cpu1.l1c.demand_miss_rate 0.876773 # miss rate for demand accesses +system.cpu1.l1c.demand_misses 60471 # number of demand (read+write) misses system.cpu1.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu1.l1c.demand_mshr_miss_latency 2387168414 # number of demand (read+write) MSHR miss cycles -system.cpu1.l1c.demand_mshr_miss_rate 0.876074 # mshr miss rate for demand accesses -system.cpu1.l1c.demand_mshr_misses 60450 # number of demand (read+write) MSHR misses +system.cpu1.l1c.demand_mshr_miss_latency 2384748536 # number of demand (read+write) MSHR miss cycles +system.cpu1.l1c.demand_mshr_miss_rate 0.876773 # mshr miss rate for demand accesses +system.cpu1.l1c.demand_mshr_misses 60471 # number of demand (read+write) MSHR misses system.cpu1.l1c.fast_writes 0 # number of fast writes performed system.cpu1.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu1.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu1.l1c.occ_%::0 0.675435 # Average percentage of cache occupancy -system.cpu1.l1c.occ_%::1 -0.006011 # Average percentage of cache occupancy -system.cpu1.l1c.occ_blocks::0 345.822577 # Average occupied blocks per context -system.cpu1.l1c.occ_blocks::1 -3.077398 # Average occupied blocks per context -system.cpu1.l1c.overall_accesses 69001 # number of overall (read+write) accesses -system.cpu1.l1c.overall_avg_miss_latency 40493.835004 # average overall miss latency -system.cpu1.l1c.overall_avg_mshr_miss_latency 39489.965492 # average overall mshr miss latency +system.cpu1.l1c.occ_%::0 0.676765 # Average percentage of cache occupancy +system.cpu1.l1c.occ_%::1 -0.002698 # Average percentage of cache occupancy +system.cpu1.l1c.occ_blocks::0 346.503445 # Average occupied blocks per context +system.cpu1.l1c.occ_blocks::1 -1.381316 # Average occupied blocks per context +system.cpu1.l1c.overall_accesses 68970 # number of overall (read+write) accesses +system.cpu1.l1c.overall_avg_miss_latency 40440.104199 # average overall miss latency +system.cpu1.l1c.overall_avg_mshr_miss_latency 39436.234493 # average overall mshr miss latency system.cpu1.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu1.l1c.overall_hits 8551 # number of overall hits -system.cpu1.l1c.overall_miss_latency 2447852326 # number of overall miss cycles -system.cpu1.l1c.overall_miss_rate 0.876074 # miss rate for overall accesses -system.cpu1.l1c.overall_misses 60450 # number of overall misses +system.cpu1.l1c.overall_hits 8499 # number of overall hits +system.cpu1.l1c.overall_miss_latency 2445453541 # number of overall miss cycles +system.cpu1.l1c.overall_miss_rate 0.876773 # miss rate for overall accesses +system.cpu1.l1c.overall_misses 60471 # number of overall misses system.cpu1.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu1.l1c.overall_mshr_miss_latency 2387168414 # number of overall MSHR miss cycles -system.cpu1.l1c.overall_mshr_miss_rate 0.876074 # mshr miss rate for overall accesses -system.cpu1.l1c.overall_mshr_misses 60450 # number of overall MSHR misses -system.cpu1.l1c.overall_mshr_uncacheable_latency 1346826370 # number of overall MSHR uncacheable cycles +system.cpu1.l1c.overall_mshr_miss_latency 2384748536 # number of overall MSHR miss cycles +system.cpu1.l1c.overall_mshr_miss_rate 0.876773 # mshr miss rate for overall accesses +system.cpu1.l1c.overall_mshr_misses 60471 # number of overall MSHR misses +system.cpu1.l1c.overall_mshr_uncacheable_latency 1361418569 # number of overall MSHR uncacheable cycles system.cpu1.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu1.l1c.replacements 27563 # number of replacements -system.cpu1.l1c.sampled_refs 27921 # Sample count of references to valid blocks. +system.cpu1.l1c.replacements 27737 # number of replacements +system.cpu1.l1c.sampled_refs 28093 # Sample count of references to valid blocks. system.cpu1.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu1.l1c.tagsinuse 342.745179 # Cycle average of tags in use -system.cpu1.l1c.total_refs 11607 # Total number of references to valid blocks. +system.cpu1.l1c.tagsinuse 345.122129 # Cycle average of tags in use +system.cpu1.l1c.total_refs 11643 # Total number of references to valid blocks. system.cpu1.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu1.l1c.writebacks 10923 # number of writebacks +system.cpu1.l1c.writebacks 11013 # number of writebacks system.cpu1.num_copies 0 # number of copy accesses completed -system.cpu1.num_reads 99680 # number of read accesses completed -system.cpu1.num_writes 54175 # number of write accesses completed -system.cpu2.l1c.ReadReq_accesses 44938 # number of ReadReq accesses(hits+misses) -system.cpu2.l1c.ReadReq_avg_miss_latency 35061.175203 # average ReadReq miss latency -system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34057.333529 # average ReadReq mshr miss latency +system.cpu1.num_reads 99221 # number of read accesses completed +system.cpu1.num_writes 53555 # number of write accesses completed +system.cpu2.l1c.ReadReq_accesses 44853 # number of ReadReq accesses(hits+misses) +system.cpu2.l1c.ReadReq_avg_miss_latency 35352.171998 # average ReadReq miss latency +system.cpu2.l1c.ReadReq_avg_mshr_miss_latency 34348.249371 # average ReadReq mshr miss latency system.cpu2.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu2.l1c.ReadReq_hits 7547 # number of ReadReq hits -system.cpu2.l1c.ReadReq_miss_latency 1310972402 # number of ReadReq miss cycles -system.cpu2.l1c.ReadReq_miss_rate 0.832058 # miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_misses 37391 # number of ReadReq misses -system.cpu2.l1c.ReadReq_mshr_miss_latency 1273437758 # number of ReadReq MSHR miss cycles -system.cpu2.l1c.ReadReq_mshr_miss_rate 0.832058 # mshr miss rate for ReadReq accesses -system.cpu2.l1c.ReadReq_mshr_misses 37391 # number of ReadReq MSHR misses -system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 816852897 # number of ReadReq MSHR uncacheable cycles -system.cpu2.l1c.WriteReq_accesses 24061 # number of WriteReq accesses(hits+misses) -system.cpu2.l1c.WriteReq_avg_miss_latency 49509.483104 # average WriteReq miss latency -system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48505.611281 # average WriteReq mshr miss latency +system.cpu2.l1c.ReadReq_hits 7463 # number of ReadReq hits +system.cpu2.l1c.ReadReq_miss_latency 1321817711 # number of ReadReq miss cycles +system.cpu2.l1c.ReadReq_miss_rate 0.833612 # miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_misses 37390 # number of ReadReq misses +system.cpu2.l1c.ReadReq_mshr_miss_latency 1284281044 # number of ReadReq MSHR miss cycles +system.cpu2.l1c.ReadReq_mshr_miss_rate 0.833612 # mshr miss rate for ReadReq accesses +system.cpu2.l1c.ReadReq_mshr_misses 37390 # number of ReadReq MSHR misses +system.cpu2.l1c.ReadReq_mshr_uncacheable_latency 812771594 # number of ReadReq MSHR uncacheable cycles +system.cpu2.l1c.WriteReq_accesses 24060 # number of WriteReq accesses(hits+misses) +system.cpu2.l1c.WriteReq_avg_miss_latency 49141.675980 # average WriteReq miss latency +system.cpu2.l1c.WriteReq_avg_mshr_miss_latency 48137.889794 # average WriteReq mshr miss latency system.cpu2.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu2.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu2.l1c.WriteReq_miss_latency 1147184233 # number of WriteReq miss cycles -system.cpu2.l1c.WriteReq_miss_rate 0.963011 # miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_misses 23171 # number of WriteReq misses -system.cpu2.l1c.WriteReq_mshr_miss_latency 1123923519 # number of WriteReq MSHR miss cycles -system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963011 # mshr miss rate for WriteReq accesses -system.cpu2.l1c.WriteReq_mshr_misses 23171 # number of WriteReq MSHR misses -system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 515570726 # number of WriteReq MSHR uncacheable cycles -system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3785.643263 # average number of cycles each access was blocked +system.cpu2.l1c.WriteReq_hits 867 # number of WriteReq hits +system.cpu2.l1c.WriteReq_miss_latency 1139742891 # number of WriteReq miss cycles +system.cpu2.l1c.WriteReq_miss_rate 0.963965 # miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_misses 23193 # number of WriteReq misses +system.cpu2.l1c.WriteReq_mshr_miss_latency 1116462078 # number of WriteReq MSHR miss cycles +system.cpu2.l1c.WriteReq_mshr_miss_rate 0.963965 # mshr miss rate for WriteReq accesses +system.cpu2.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses +system.cpu2.l1c.WriteReq_mshr_uncacheable_latency 540024650 # number of WriteReq MSHR uncacheable cycles +system.cpu2.l1c.avg_blocked_cycles::no_mshrs 3782.890162 # average number of cycles each access was blocked system.cpu2.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu2.l1c.avg_refs 0.410349 # Average number of references to valid blocks. -system.cpu2.l1c.blocked::no_mshrs 69704 # number of cycles access was blocked +system.cpu2.l1c.avg_refs 0.405809 # Average number of references to valid blocks. +system.cpu2.l1c.blocked::no_mshrs 69548 # number of cycles access was blocked system.cpu2.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu2.l1c.blocked_cycles::no_mshrs 263874478 # number of cycles access was blocked +system.cpu2.l1c.blocked_cycles::no_mshrs 263092445 # number of cycles access was blocked system.cpu2.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu2.l1c.cache_copies 0 # number of cache copies performed -system.cpu2.l1c.demand_accesses 68999 # number of demand (read+write) accesses -system.cpu2.l1c.demand_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.demand_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency -system.cpu2.l1c.demand_hits 8437 # number of demand (read+write) hits -system.cpu2.l1c.demand_miss_latency 2458156635 # number of demand (read+write) miss cycles -system.cpu2.l1c.demand_miss_rate 0.877723 # miss rate for demand accesses -system.cpu2.l1c.demand_misses 60562 # number of demand (read+write) misses +system.cpu2.l1c.demand_accesses 68913 # number of demand (read+write) accesses +system.cpu2.l1c.demand_avg_miss_latency 40631.210108 # average overall miss latency +system.cpu2.l1c.demand_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency +system.cpu2.l1c.demand_hits 8330 # number of demand (read+write) hits +system.cpu2.l1c.demand_miss_latency 2461560602 # number of demand (read+write) miss cycles +system.cpu2.l1c.demand_miss_rate 0.879123 # miss rate for demand accesses +system.cpu2.l1c.demand_misses 60583 # number of demand (read+write) misses system.cpu2.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu2.l1c.demand_mshr_miss_latency 2397361277 # number of demand (read+write) MSHR miss cycles -system.cpu2.l1c.demand_mshr_miss_rate 0.877723 # mshr miss rate for demand accesses -system.cpu2.l1c.demand_mshr_misses 60562 # number of demand (read+write) MSHR misses +system.cpu2.l1c.demand_mshr_miss_latency 2400743122 # number of demand (read+write) MSHR miss cycles +system.cpu2.l1c.demand_mshr_miss_rate 0.879123 # mshr miss rate for demand accesses +system.cpu2.l1c.demand_mshr_misses 60583 # number of demand (read+write) MSHR misses system.cpu2.l1c.fast_writes 0 # number of fast writes performed system.cpu2.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu2.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu2.l1c.occ_%::0 0.678453 # Average percentage of cache occupancy -system.cpu2.l1c.occ_%::1 -0.001793 # Average percentage of cache occupancy -system.cpu2.l1c.occ_blocks::0 347.368052 # Average occupied blocks per context -system.cpu2.l1c.occ_blocks::1 -0.918043 # Average occupied blocks per context -system.cpu2.l1c.overall_accesses 68999 # number of overall (read+write) accesses -system.cpu2.l1c.overall_avg_miss_latency 40589.092748 # average overall miss latency -system.cpu2.l1c.overall_avg_mshr_miss_latency 39585.239540 # average overall mshr miss latency +system.cpu2.l1c.occ_%::0 0.675485 # Average percentage of cache occupancy +system.cpu2.l1c.occ_%::1 -0.002427 # Average percentage of cache occupancy +system.cpu2.l1c.occ_blocks::0 345.848425 # Average occupied blocks per context +system.cpu2.l1c.occ_blocks::1 -1.242713 # Average occupied blocks per context +system.cpu2.l1c.overall_accesses 68913 # number of overall (read+write) accesses +system.cpu2.l1c.overall_avg_miss_latency 40631.210108 # average overall miss latency +system.cpu2.l1c.overall_avg_mshr_miss_latency 39627.339716 # average overall mshr miss latency system.cpu2.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu2.l1c.overall_hits 8437 # number of overall hits -system.cpu2.l1c.overall_miss_latency 2458156635 # number of overall miss cycles -system.cpu2.l1c.overall_miss_rate 0.877723 # miss rate for overall accesses -system.cpu2.l1c.overall_misses 60562 # number of overall misses +system.cpu2.l1c.overall_hits 8330 # number of overall hits +system.cpu2.l1c.overall_miss_latency 2461560602 # number of overall miss cycles +system.cpu2.l1c.overall_miss_rate 0.879123 # miss rate for overall accesses +system.cpu2.l1c.overall_misses 60583 # number of overall misses system.cpu2.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu2.l1c.overall_mshr_miss_latency 2397361277 # number of overall MSHR miss cycles -system.cpu2.l1c.overall_mshr_miss_rate 0.877723 # mshr miss rate for overall accesses -system.cpu2.l1c.overall_mshr_misses 60562 # number of overall MSHR misses -system.cpu2.l1c.overall_mshr_uncacheable_latency 1332423623 # number of overall MSHR uncacheable cycles +system.cpu2.l1c.overall_mshr_miss_latency 2400743122 # number of overall MSHR miss cycles +system.cpu2.l1c.overall_mshr_miss_rate 0.879123 # mshr miss rate for overall accesses +system.cpu2.l1c.overall_mshr_misses 60583 # number of overall MSHR misses +system.cpu2.l1c.overall_mshr_uncacheable_latency 1352796244 # number of overall MSHR uncacheable cycles system.cpu2.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu2.l1c.replacements 27725 # number of replacements -system.cpu2.l1c.sampled_refs 28081 # Sample count of references to valid blocks. +system.cpu2.l1c.replacements 27772 # number of replacements +system.cpu2.l1c.sampled_refs 28129 # Sample count of references to valid blocks. system.cpu2.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu2.l1c.tagsinuse 346.450009 # Cycle average of tags in use -system.cpu2.l1c.total_refs 11523 # Total number of references to valid blocks. +system.cpu2.l1c.tagsinuse 344.605712 # Cycle average of tags in use +system.cpu2.l1c.total_refs 11415 # Total number of references to valid blocks. system.cpu2.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu2.l1c.writebacks 10868 # number of writebacks +system.cpu2.l1c.writebacks 10844 # number of writebacks system.cpu2.num_copies 0 # number of copy accesses completed -system.cpu2.num_reads 99153 # number of read accesses completed -system.cpu2.num_writes 52976 # number of write accesses completed -system.cpu3.l1c.ReadReq_accesses 44765 # number of ReadReq accesses(hits+misses) -system.cpu3.l1c.ReadReq_avg_miss_latency 35099.574214 # average ReadReq miss latency -system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34095.652628 # average ReadReq mshr miss latency +system.cpu2.num_reads 99462 # number of read accesses completed +system.cpu2.num_writes 53250 # number of write accesses completed +system.cpu3.l1c.ReadReq_accesses 44365 # number of ReadReq accesses(hits+misses) +system.cpu3.l1c.ReadReq_avg_miss_latency 35201.306246 # average ReadReq miss latency +system.cpu3.l1c.ReadReq_avg_mshr_miss_latency 34197.412075 # average ReadReq mshr miss latency system.cpu3.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu3.l1c.ReadReq_hits 7629 # number of ReadReq hits -system.cpu3.l1c.ReadReq_miss_latency 1303457788 # number of ReadReq miss cycles -system.cpu3.l1c.ReadReq_miss_rate 0.829577 # miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_misses 37136 # number of ReadReq misses -system.cpu3.l1c.ReadReq_mshr_miss_latency 1266176156 # number of ReadReq MSHR miss cycles -system.cpu3.l1c.ReadReq_mshr_miss_rate 0.829577 # mshr miss rate for ReadReq accesses -system.cpu3.l1c.ReadReq_mshr_misses 37136 # number of ReadReq MSHR misses -system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 809090503 # number of ReadReq MSHR uncacheable cycles -system.cpu3.l1c.WriteReq_accesses 24303 # number of WriteReq accesses(hits+misses) -system.cpu3.l1c.WriteReq_avg_miss_latency 49401.057101 # average WriteReq miss latency -system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48397.098346 # average WriteReq mshr miss latency +system.cpu3.l1c.ReadReq_hits 7447 # number of ReadReq hits +system.cpu3.l1c.ReadReq_miss_latency 1299561824 # number of ReadReq miss cycles +system.cpu3.l1c.ReadReq_miss_rate 0.832142 # miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_misses 36918 # number of ReadReq misses +system.cpu3.l1c.ReadReq_mshr_miss_latency 1262500059 # number of ReadReq MSHR miss cycles +system.cpu3.l1c.ReadReq_mshr_miss_rate 0.832142 # mshr miss rate for ReadReq accesses +system.cpu3.l1c.ReadReq_mshr_misses 36918 # number of ReadReq MSHR misses +system.cpu3.l1c.ReadReq_mshr_uncacheable_latency 824241710 # number of ReadReq MSHR uncacheable cycles +system.cpu3.l1c.WriteReq_accesses 24091 # number of WriteReq accesses(hits+misses) +system.cpu3.l1c.WriteReq_avg_miss_latency 49786.879855 # average WriteReq miss latency +system.cpu3.l1c.WriteReq_avg_mshr_miss_latency 48783.051269 # average WriteReq mshr miss latency system.cpu3.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu3.l1c.WriteReq_hits 906 # number of WriteReq hits -system.cpu3.l1c.WriteReq_miss_latency 1155836533 # number of WriteReq miss cycles -system.cpu3.l1c.WriteReq_miss_rate 0.962721 # miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_misses 23397 # number of WriteReq misses -system.cpu3.l1c.WriteReq_mshr_miss_latency 1132346910 # number of WriteReq MSHR miss cycles -system.cpu3.l1c.WriteReq_mshr_miss_rate 0.962721 # mshr miss rate for WriteReq accesses -system.cpu3.l1c.WriteReq_mshr_misses 23397 # number of WriteReq MSHR misses -system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 535399356 # number of WriteReq MSHR uncacheable cycles -system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3780.086099 # average number of cycles each access was blocked +system.cpu3.l1c.WriteReq_hits 919 # number of WriteReq hits +system.cpu3.l1c.WriteReq_miss_latency 1153661580 # number of WriteReq miss cycles +system.cpu3.l1c.WriteReq_miss_rate 0.961853 # miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_misses 23172 # number of WriteReq misses +system.cpu3.l1c.WriteReq_mshr_miss_latency 1130400864 # number of WriteReq MSHR miss cycles +system.cpu3.l1c.WriteReq_mshr_miss_rate 0.961853 # mshr miss rate for WriteReq accesses +system.cpu3.l1c.WriteReq_mshr_misses 23172 # number of WriteReq MSHR misses +system.cpu3.l1c.WriteReq_mshr_uncacheable_latency 525075683 # number of WriteReq MSHR uncacheable cycles +system.cpu3.l1c.avg_blocked_cycles::no_mshrs 3810.709164 # average number of cycles each access was blocked system.cpu3.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu3.l1c.avg_refs 0.418843 # Average number of references to valid blocks. -system.cpu3.l1c.blocked::no_mshrs 69350 # number of cycles access was blocked +system.cpu3.l1c.avg_refs 0.409480 # Average number of references to valid blocks. +system.cpu3.l1c.blocked::no_mshrs 69290 # number of cycles access was blocked system.cpu3.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu3.l1c.blocked_cycles::no_mshrs 262148971 # number of cycles access was blocked +system.cpu3.l1c.blocked_cycles::no_mshrs 264044038 # number of cycles access was blocked system.cpu3.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu3.l1c.cache_copies 0 # number of cache copies performed -system.cpu3.l1c.demand_accesses 69068 # number of demand (read+write) accesses -system.cpu3.l1c.demand_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.demand_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency -system.cpu3.l1c.demand_hits 8535 # number of demand (read+write) hits -system.cpu3.l1c.demand_miss_latency 2459294321 # number of demand (read+write) miss cycles -system.cpu3.l1c.demand_miss_rate 0.876426 # miss rate for demand accesses -system.cpu3.l1c.demand_misses 60533 # number of demand (read+write) misses +system.cpu3.l1c.demand_accesses 68456 # number of demand (read+write) accesses +system.cpu3.l1c.demand_avg_miss_latency 40825.818006 # average overall miss latency +system.cpu3.l1c.demand_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency +system.cpu3.l1c.demand_hits 8366 # number of demand (read+write) hits +system.cpu3.l1c.demand_miss_latency 2453223404 # number of demand (read+write) miss cycles +system.cpu3.l1c.demand_miss_rate 0.877790 # miss rate for demand accesses +system.cpu3.l1c.demand_misses 60090 # number of demand (read+write) misses system.cpu3.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu3.l1c.demand_mshr_miss_latency 2398523066 # number of demand (read+write) MSHR miss cycles -system.cpu3.l1c.demand_mshr_miss_rate 0.876426 # mshr miss rate for demand accesses -system.cpu3.l1c.demand_mshr_misses 60533 # number of demand (read+write) MSHR misses +system.cpu3.l1c.demand_mshr_miss_latency 2392900923 # number of demand (read+write) MSHR miss cycles +system.cpu3.l1c.demand_mshr_miss_rate 0.877790 # mshr miss rate for demand accesses +system.cpu3.l1c.demand_mshr_misses 60090 # number of demand (read+write) MSHR misses system.cpu3.l1c.fast_writes 0 # number of fast writes performed system.cpu3.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu3.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu3.l1c.occ_%::0 0.676337 # Average percentage of cache occupancy -system.cpu3.l1c.occ_%::1 -0.001850 # Average percentage of cache occupancy -system.cpu3.l1c.occ_blocks::0 346.284781 # Average occupied blocks per context -system.cpu3.l1c.occ_blocks::1 -0.947285 # Average occupied blocks per context -system.cpu3.l1c.overall_accesses 69068 # number of overall (read+write) accesses -system.cpu3.l1c.overall_avg_miss_latency 40627.332546 # average overall miss latency -system.cpu3.l1c.overall_avg_mshr_miss_latency 39623.396594 # average overall mshr miss latency +system.cpu3.l1c.occ_%::0 0.675570 # Average percentage of cache occupancy +system.cpu3.l1c.occ_%::1 -0.001897 # Average percentage of cache occupancy +system.cpu3.l1c.occ_blocks::0 345.891792 # Average occupied blocks per context +system.cpu3.l1c.occ_blocks::1 -0.971043 # Average occupied blocks per context +system.cpu3.l1c.overall_accesses 68456 # number of overall (read+write) accesses +system.cpu3.l1c.overall_avg_miss_latency 40825.818006 # average overall miss latency +system.cpu3.l1c.overall_avg_mshr_miss_latency 39821.949126 # average overall mshr miss latency system.cpu3.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu3.l1c.overall_hits 8535 # number of overall hits -system.cpu3.l1c.overall_miss_latency 2459294321 # number of overall miss cycles -system.cpu3.l1c.overall_miss_rate 0.876426 # miss rate for overall accesses -system.cpu3.l1c.overall_misses 60533 # number of overall misses +system.cpu3.l1c.overall_hits 8366 # number of overall hits +system.cpu3.l1c.overall_miss_latency 2453223404 # number of overall miss cycles +system.cpu3.l1c.overall_miss_rate 0.877790 # miss rate for overall accesses +system.cpu3.l1c.overall_misses 60090 # number of overall misses system.cpu3.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu3.l1c.overall_mshr_miss_latency 2398523066 # number of overall MSHR miss cycles -system.cpu3.l1c.overall_mshr_miss_rate 0.876426 # mshr miss rate for overall accesses -system.cpu3.l1c.overall_mshr_misses 60533 # number of overall MSHR misses -system.cpu3.l1c.overall_mshr_uncacheable_latency 1344489859 # number of overall MSHR uncacheable cycles +system.cpu3.l1c.overall_mshr_miss_latency 2392900923 # number of overall MSHR miss cycles +system.cpu3.l1c.overall_mshr_miss_rate 0.877790 # mshr miss rate for overall accesses +system.cpu3.l1c.overall_mshr_misses 60090 # number of overall MSHR misses +system.cpu3.l1c.overall_mshr_uncacheable_latency 1349317393 # number of overall MSHR uncacheable cycles system.cpu3.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu3.l1c.replacements 27562 # number of replacements -system.cpu3.l1c.sampled_refs 27915 # Sample count of references to valid blocks. +system.cpu3.l1c.replacements 27569 # number of replacements +system.cpu3.l1c.sampled_refs 27933 # Sample count of references to valid blocks. system.cpu3.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu3.l1c.tagsinuse 345.337496 # Cycle average of tags in use -system.cpu3.l1c.total_refs 11692 # Total number of references to valid blocks. +system.cpu3.l1c.tagsinuse 344.920749 # Cycle average of tags in use +system.cpu3.l1c.total_refs 11438 # Total number of references to valid blocks. system.cpu3.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu3.l1c.writebacks 10850 # number of writebacks +system.cpu3.l1c.writebacks 10833 # number of writebacks system.cpu3.num_copies 0 # number of copy accesses completed -system.cpu3.num_reads 99282 # number of read accesses completed -system.cpu3.num_writes 53764 # number of write accesses completed -system.cpu4.l1c.ReadReq_accesses 44687 # number of ReadReq accesses(hits+misses) -system.cpu4.l1c.ReadReq_avg_miss_latency 35015.303210 # average ReadReq miss latency -system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34011.435353 # average ReadReq mshr miss latency +system.cpu3.num_reads 98484 # number of read accesses completed +system.cpu3.num_writes 53322 # number of write accesses completed +system.cpu4.l1c.ReadReq_accesses 44742 # number of ReadReq accesses(hits+misses) +system.cpu4.l1c.ReadReq_avg_miss_latency 35246.657121 # average ReadReq miss latency +system.cpu4.l1c.ReadReq_avg_mshr_miss_latency 34242.680675 # average ReadReq mshr miss latency system.cpu4.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu4.l1c.ReadReq_hits 7462 # number of ReadReq hits -system.cpu4.l1c.ReadReq_miss_latency 1303444662 # number of ReadReq miss cycles -system.cpu4.l1c.ReadReq_miss_rate 0.833016 # miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_misses 37225 # number of ReadReq misses -system.cpu4.l1c.ReadReq_mshr_miss_latency 1266075681 # number of ReadReq MSHR miss cycles -system.cpu4.l1c.ReadReq_mshr_miss_rate 0.833016 # mshr miss rate for ReadReq accesses -system.cpu4.l1c.ReadReq_mshr_misses 37225 # number of ReadReq MSHR misses -system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 822702802 # number of ReadReq MSHR uncacheable cycles -system.cpu4.l1c.WriteReq_accesses 24166 # number of WriteReq accesses(hits+misses) -system.cpu4.l1c.WriteReq_avg_miss_latency 49419.242444 # average WriteReq miss latency -system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 48415.543957 # average WriteReq mshr miss latency +system.cpu4.l1c.ReadReq_hits 7551 # number of ReadReq hits +system.cpu4.l1c.ReadReq_miss_latency 1310858425 # number of ReadReq miss cycles +system.cpu4.l1c.ReadReq_miss_rate 0.831232 # miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_misses 37191 # number of ReadReq misses +system.cpu4.l1c.ReadReq_mshr_miss_latency 1273519537 # number of ReadReq MSHR miss cycles +system.cpu4.l1c.ReadReq_mshr_miss_rate 0.831232 # mshr miss rate for ReadReq accesses +system.cpu4.l1c.ReadReq_mshr_misses 37191 # number of ReadReq MSHR misses +system.cpu4.l1c.ReadReq_mshr_uncacheable_latency 821041101 # number of ReadReq MSHR uncacheable cycles +system.cpu4.l1c.WriteReq_accesses 24235 # number of WriteReq accesses(hits+misses) +system.cpu4.l1c.WriteReq_avg_miss_latency 48987.169998 # average WriteReq miss latency +system.cpu4.l1c.WriteReq_avg_mshr_miss_latency 47983.555251 # average WriteReq mshr miss latency system.cpu4.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu4.l1c.WriteReq_hits 973 # number of WriteReq hits -system.cpu4.l1c.WriteReq_miss_latency 1146180490 # number of WriteReq miss cycles -system.cpu4.l1c.WriteReq_miss_rate 0.959737 # miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_misses 23193 # number of WriteReq misses -system.cpu4.l1c.WriteReq_mshr_miss_latency 1122901711 # number of WriteReq MSHR miss cycles -system.cpu4.l1c.WriteReq_mshr_miss_rate 0.959737 # mshr miss rate for WriteReq accesses -system.cpu4.l1c.WriteReq_mshr_misses 23193 # number of WriteReq MSHR misses -system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 528019968 # number of WriteReq MSHR uncacheable cycles -system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3787.291600 # average number of cycles each access was blocked +system.cpu4.l1c.WriteReq_hits 923 # number of WriteReq hits +system.cpu4.l1c.WriteReq_miss_latency 1141988907 # number of WriteReq miss cycles +system.cpu4.l1c.WriteReq_miss_rate 0.961915 # miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_misses 23312 # number of WriteReq misses +system.cpu4.l1c.WriteReq_mshr_miss_latency 1118592640 # number of WriteReq MSHR miss cycles +system.cpu4.l1c.WriteReq_mshr_miss_rate 0.961915 # mshr miss rate for WriteReq accesses +system.cpu4.l1c.WriteReq_mshr_misses 23312 # number of WriteReq MSHR misses +system.cpu4.l1c.WriteReq_mshr_uncacheable_latency 537191159 # number of WriteReq MSHR uncacheable cycles +system.cpu4.l1c.avg_blocked_cycles::no_mshrs 3781.018448 # average number of cycles each access was blocked system.cpu4.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu4.l1c.avg_refs 0.411354 # Average number of references to valid blocks. -system.cpu4.l1c.blocked::no_mshrs 69537 # number of cycles access was blocked +system.cpu4.l1c.avg_refs 0.407526 # Average number of references to valid blocks. +system.cpu4.l1c.blocked::no_mshrs 69602 # number of cycles access was blocked system.cpu4.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu4.l1c.blocked_cycles::no_mshrs 263356896 # number of cycles access was blocked +system.cpu4.l1c.blocked_cycles::no_mshrs 263166446 # number of cycles access was blocked system.cpu4.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu4.l1c.cache_copies 0 # number of cache copies performed -system.cpu4.l1c.demand_accesses 68853 # number of demand (read+write) accesses -system.cpu4.l1c.demand_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.demand_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency -system.cpu4.l1c.demand_hits 8435 # number of demand (read+write) hits -system.cpu4.l1c.demand_miss_latency 2449625152 # number of demand (read+write) miss cycles -system.cpu4.l1c.demand_miss_rate 0.877493 # miss rate for demand accesses -system.cpu4.l1c.demand_misses 60418 # number of demand (read+write) misses +system.cpu4.l1c.demand_accesses 68977 # number of demand (read+write) accesses +system.cpu4.l1c.demand_avg_miss_latency 40540.920814 # average overall miss latency +system.cpu4.l1c.demand_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency +system.cpu4.l1c.demand_hits 8474 # number of demand (read+write) hits +system.cpu4.l1c.demand_miss_latency 2452847332 # number of demand (read+write) miss cycles +system.cpu4.l1c.demand_miss_rate 0.877147 # miss rate for demand accesses +system.cpu4.l1c.demand_misses 60503 # number of demand (read+write) misses system.cpu4.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu4.l1c.demand_mshr_miss_latency 2388977392 # number of demand (read+write) MSHR miss cycles -system.cpu4.l1c.demand_mshr_miss_rate 0.877493 # mshr miss rate for demand accesses -system.cpu4.l1c.demand_mshr_misses 60418 # number of demand (read+write) MSHR misses +system.cpu4.l1c.demand_mshr_miss_latency 2392112177 # number of demand (read+write) MSHR miss cycles +system.cpu4.l1c.demand_mshr_miss_rate 0.877147 # mshr miss rate for demand accesses +system.cpu4.l1c.demand_mshr_misses 60503 # number of demand (read+write) MSHR misses system.cpu4.l1c.fast_writes 0 # number of fast writes performed system.cpu4.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu4.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu4.l1c.occ_%::0 0.676775 # Average percentage of cache occupancy -system.cpu4.l1c.occ_%::1 -0.003496 # Average percentage of cache occupancy -system.cpu4.l1c.occ_blocks::0 346.508789 # Average occupied blocks per context -system.cpu4.l1c.occ_blocks::1 -1.790088 # Average occupied blocks per context -system.cpu4.l1c.overall_accesses 68853 # number of overall (read+write) accesses -system.cpu4.l1c.overall_avg_miss_latency 40544.624979 # average overall miss latency -system.cpu4.l1c.overall_avg_mshr_miss_latency 39540.822139 # average overall mshr miss latency +system.cpu4.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy +system.cpu4.l1c.occ_%::1 -0.006074 # Average percentage of cache occupancy +system.cpu4.l1c.occ_blocks::0 346.381795 # Average occupied blocks per context +system.cpu4.l1c.occ_blocks::1 -3.109691 # Average occupied blocks per context +system.cpu4.l1c.overall_accesses 68977 # number of overall (read+write) accesses +system.cpu4.l1c.overall_avg_miss_latency 40540.920814 # average overall miss latency +system.cpu4.l1c.overall_avg_mshr_miss_latency 39537.083731 # average overall mshr miss latency system.cpu4.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu4.l1c.overall_hits 8435 # number of overall hits -system.cpu4.l1c.overall_miss_latency 2449625152 # number of overall miss cycles -system.cpu4.l1c.overall_miss_rate 0.877493 # miss rate for overall accesses -system.cpu4.l1c.overall_misses 60418 # number of overall misses +system.cpu4.l1c.overall_hits 8474 # number of overall hits +system.cpu4.l1c.overall_miss_latency 2452847332 # number of overall miss cycles +system.cpu4.l1c.overall_miss_rate 0.877147 # miss rate for overall accesses +system.cpu4.l1c.overall_misses 60503 # number of overall misses system.cpu4.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu4.l1c.overall_mshr_miss_latency 2388977392 # number of overall MSHR miss cycles -system.cpu4.l1c.overall_mshr_miss_rate 0.877493 # mshr miss rate for overall accesses -system.cpu4.l1c.overall_mshr_misses 60418 # number of overall MSHR misses -system.cpu4.l1c.overall_mshr_uncacheable_latency 1350722770 # number of overall MSHR uncacheable cycles +system.cpu4.l1c.overall_mshr_miss_latency 2392112177 # number of overall MSHR miss cycles +system.cpu4.l1c.overall_mshr_miss_rate 0.877147 # mshr miss rate for overall accesses +system.cpu4.l1c.overall_mshr_misses 60503 # number of overall MSHR misses +system.cpu4.l1c.overall_mshr_uncacheable_latency 1358232260 # number of overall MSHR uncacheable cycles system.cpu4.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu4.l1c.replacements 27721 # number of replacements -system.cpu4.l1c.sampled_refs 28078 # Sample count of references to valid blocks. +system.cpu4.l1c.replacements 28030 # number of replacements +system.cpu4.l1c.sampled_refs 28381 # Sample count of references to valid blocks. system.cpu4.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu4.l1c.tagsinuse 344.718702 # Cycle average of tags in use -system.cpu4.l1c.total_refs 11550 # Total number of references to valid blocks. +system.cpu4.l1c.tagsinuse 343.272105 # Cycle average of tags in use +system.cpu4.l1c.total_refs 11566 # Total number of references to valid blocks. system.cpu4.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu4.l1c.writebacks 10846 # number of writebacks +system.cpu4.l1c.writebacks 11122 # number of writebacks system.cpu4.num_copies 0 # number of copy accesses completed -system.cpu4.num_reads 99301 # number of read accesses completed -system.cpu4.num_writes 53586 # number of write accesses completed -system.cpu5.l1c.ReadReq_accesses 44547 # number of ReadReq accesses(hits+misses) -system.cpu5.l1c.ReadReq_avg_miss_latency 34955.945435 # average ReadReq miss latency -system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33952.104976 # average ReadReq mshr miss latency +system.cpu4.num_reads 99459 # number of read accesses completed +system.cpu4.num_writes 53508 # number of write accesses completed +system.cpu5.l1c.ReadReq_accesses 44755 # number of ReadReq accesses(hits+misses) +system.cpu5.l1c.ReadReq_avg_miss_latency 34940.465460 # average ReadReq miss latency +system.cpu5.l1c.ReadReq_avg_mshr_miss_latency 33936.624875 # average ReadReq mshr miss latency system.cpu5.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu5.l1c.ReadReq_hits 7472 # number of ReadReq hits -system.cpu5.l1c.ReadReq_miss_latency 1295991677 # number of ReadReq miss cycles -system.cpu5.l1c.ReadReq_miss_rate 0.832267 # miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_misses 37075 # number of ReadReq misses -system.cpu5.l1c.ReadReq_mshr_miss_latency 1258774292 # number of ReadReq MSHR miss cycles -system.cpu5.l1c.ReadReq_mshr_miss_rate 0.832267 # mshr miss rate for ReadReq accesses -system.cpu5.l1c.ReadReq_mshr_misses 37075 # number of ReadReq MSHR misses -system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 819117357 # number of ReadReq MSHR uncacheable cycles -system.cpu5.l1c.WriteReq_accesses 24285 # number of WriteReq accesses(hits+misses) -system.cpu5.l1c.WriteReq_avg_miss_latency 49434.988716 # average WriteReq miss latency -system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48431.115110 # average WriteReq mshr miss latency +system.cpu5.l1c.ReadReq_hits 7682 # number of ReadReq hits +system.cpu5.l1c.ReadReq_miss_latency 1295347876 # number of ReadReq miss cycles +system.cpu5.l1c.ReadReq_miss_rate 0.828354 # miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_misses 37073 # number of ReadReq misses +system.cpu5.l1c.ReadReq_mshr_miss_latency 1258132494 # number of ReadReq MSHR miss cycles +system.cpu5.l1c.ReadReq_mshr_miss_rate 0.828354 # mshr miss rate for ReadReq accesses +system.cpu5.l1c.ReadReq_mshr_misses 37073 # number of ReadReq MSHR misses +system.cpu5.l1c.ReadReq_mshr_uncacheable_latency 842968180 # number of ReadReq MSHR uncacheable cycles +system.cpu5.l1c.WriteReq_accesses 23967 # number of WriteReq accesses(hits+misses) +system.cpu5.l1c.WriteReq_avg_miss_latency 49240.876366 # average WriteReq miss latency +system.cpu5.l1c.WriteReq_avg_mshr_miss_latency 48237.004902 # average WriteReq mshr miss latency system.cpu5.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu5.l1c.WriteReq_hits 890 # number of WriteReq hits -system.cpu5.l1c.WriteReq_miss_latency 1156531561 # number of WriteReq miss cycles -system.cpu5.l1c.WriteReq_miss_rate 0.963352 # miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_misses 23395 # number of WriteReq misses -system.cpu5.l1c.WriteReq_mshr_miss_latency 1133045938 # number of WriteReq MSHR miss cycles -system.cpu5.l1c.WriteReq_mshr_miss_rate 0.963352 # mshr miss rate for WriteReq accesses -system.cpu5.l1c.WriteReq_mshr_misses 23395 # number of WriteReq MSHR misses -system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 539640321 # number of WriteReq MSHR uncacheable cycles -system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3783.632237 # average number of cycles each access was blocked +system.cpu5.l1c.WriteReq_hits 915 # number of WriteReq hits +system.cpu5.l1c.WriteReq_miss_latency 1135100682 # number of WriteReq miss cycles +system.cpu5.l1c.WriteReq_miss_rate 0.961823 # miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_misses 23052 # number of WriteReq misses +system.cpu5.l1c.WriteReq_mshr_miss_latency 1111959437 # number of WriteReq MSHR miss cycles +system.cpu5.l1c.WriteReq_mshr_miss_rate 0.961823 # mshr miss rate for WriteReq accesses +system.cpu5.l1c.WriteReq_mshr_misses 23052 # number of WriteReq MSHR misses +system.cpu5.l1c.WriteReq_mshr_uncacheable_latency 550257500 # number of WriteReq MSHR uncacheable cycles +system.cpu5.l1c.avg_blocked_cycles::no_mshrs 3789.796507 # average number of cycles each access was blocked system.cpu5.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu5.l1c.avg_refs 0.410620 # Average number of references to valid blocks. -system.cpu5.l1c.blocked::no_mshrs 69474 # number of cycles access was blocked +system.cpu5.l1c.avg_refs 0.418015 # Average number of references to valid blocks. +system.cpu5.l1c.blocked::no_mshrs 69457 # number of cycles access was blocked system.cpu5.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu5.l1c.blocked_cycles::no_mshrs 262864066 # number of cycles access was blocked +system.cpu5.l1c.blocked_cycles::no_mshrs 263227896 # number of cycles access was blocked system.cpu5.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu5.l1c.cache_copies 0 # number of cache copies performed -system.cpu5.l1c.demand_accesses 68832 # number of demand (read+write) accesses -system.cpu5.l1c.demand_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.demand_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency -system.cpu5.l1c.demand_hits 8362 # number of demand (read+write) hits -system.cpu5.l1c.demand_miss_latency 2452523238 # number of demand (read+write) miss cycles -system.cpu5.l1c.demand_miss_rate 0.878516 # miss rate for demand accesses -system.cpu5.l1c.demand_misses 60470 # number of demand (read+write) misses +system.cpu5.l1c.demand_accesses 68722 # number of demand (read+write) accesses +system.cpu5.l1c.demand_avg_miss_latency 40423.260840 # average overall miss latency +system.cpu5.l1c.demand_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency +system.cpu5.l1c.demand_hits 8597 # number of demand (read+write) hits +system.cpu5.l1c.demand_miss_latency 2430448558 # number of demand (read+write) miss cycles +system.cpu5.l1c.demand_miss_rate 0.874902 # miss rate for demand accesses +system.cpu5.l1c.demand_misses 60125 # number of demand (read+write) misses system.cpu5.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu5.l1c.demand_mshr_miss_latency 2391820230 # number of demand (read+write) MSHR miss cycles -system.cpu5.l1c.demand_mshr_miss_rate 0.878516 # mshr miss rate for demand accesses -system.cpu5.l1c.demand_mshr_misses 60470 # number of demand (read+write) MSHR misses +system.cpu5.l1c.demand_mshr_miss_latency 2370091931 # number of demand (read+write) MSHR miss cycles +system.cpu5.l1c.demand_mshr_miss_rate 0.874902 # mshr miss rate for demand accesses +system.cpu5.l1c.demand_mshr_misses 60125 # number of demand (read+write) MSHR misses system.cpu5.l1c.fast_writes 0 # number of fast writes performed system.cpu5.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu5.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu5.l1c.occ_%::0 0.676296 # Average percentage of cache occupancy -system.cpu5.l1c.occ_%::1 -0.006346 # Average percentage of cache occupancy -system.cpu5.l1c.occ_blocks::0 346.263302 # Average occupied blocks per context -system.cpu5.l1c.occ_blocks::1 -3.249085 # Average occupied blocks per context -system.cpu5.l1c.overall_accesses 68832 # number of overall (read+write) accesses -system.cpu5.l1c.overall_avg_miss_latency 40557.685431 # average overall miss latency -system.cpu5.l1c.overall_avg_mshr_miss_latency 39553.832148 # average overall mshr miss latency +system.cpu5.l1c.occ_%::0 0.676497 # Average percentage of cache occupancy +system.cpu5.l1c.occ_%::1 -0.002501 # Average percentage of cache occupancy +system.cpu5.l1c.occ_blocks::0 346.366637 # Average occupied blocks per context +system.cpu5.l1c.occ_blocks::1 -1.280483 # Average occupied blocks per context +system.cpu5.l1c.overall_accesses 68722 # number of overall (read+write) accesses +system.cpu5.l1c.overall_avg_miss_latency 40423.260840 # average overall miss latency +system.cpu5.l1c.overall_avg_mshr_miss_latency 39419.408416 # average overall mshr miss latency system.cpu5.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu5.l1c.overall_hits 8362 # number of overall hits -system.cpu5.l1c.overall_miss_latency 2452523238 # number of overall miss cycles -system.cpu5.l1c.overall_miss_rate 0.878516 # miss rate for overall accesses -system.cpu5.l1c.overall_misses 60470 # number of overall misses +system.cpu5.l1c.overall_hits 8597 # number of overall hits +system.cpu5.l1c.overall_miss_latency 2430448558 # number of overall miss cycles +system.cpu5.l1c.overall_miss_rate 0.874902 # miss rate for overall accesses +system.cpu5.l1c.overall_misses 60125 # number of overall misses system.cpu5.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu5.l1c.overall_mshr_miss_latency 2391820230 # number of overall MSHR miss cycles -system.cpu5.l1c.overall_mshr_miss_rate 0.878516 # mshr miss rate for overall accesses -system.cpu5.l1c.overall_mshr_misses 60470 # number of overall MSHR misses -system.cpu5.l1c.overall_mshr_uncacheable_latency 1358757678 # number of overall MSHR uncacheable cycles +system.cpu5.l1c.overall_mshr_miss_latency 2370091931 # number of overall MSHR miss cycles +system.cpu5.l1c.overall_mshr_miss_rate 0.874902 # mshr miss rate for overall accesses +system.cpu5.l1c.overall_mshr_misses 60125 # number of overall MSHR misses +system.cpu5.l1c.overall_mshr_uncacheable_latency 1393225680 # number of overall MSHR uncacheable cycles system.cpu5.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu5.l1c.replacements 27632 # number of replacements -system.cpu5.l1c.sampled_refs 27965 # Sample count of references to valid blocks. +system.cpu5.l1c.replacements 27483 # number of replacements +system.cpu5.l1c.sampled_refs 27822 # Sample count of references to valid blocks. system.cpu5.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu5.l1c.tagsinuse 343.014216 # Cycle average of tags in use -system.cpu5.l1c.total_refs 11483 # Total number of references to valid blocks. +system.cpu5.l1c.tagsinuse 345.086155 # Cycle average of tags in use +system.cpu5.l1c.total_refs 11630 # Total number of references to valid blocks. system.cpu5.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu5.l1c.writebacks 10950 # number of writebacks +system.cpu5.l1c.writebacks 10776 # number of writebacks system.cpu5.num_copies 0 # number of copy accesses completed -system.cpu5.num_reads 99024 # number of read accesses completed -system.cpu5.num_writes 53903 # number of write accesses completed -system.cpu6.l1c.ReadReq_accesses 45059 # number of ReadReq accesses(hits+misses) -system.cpu6.l1c.ReadReq_avg_miss_latency 34819.869819 # average ReadReq miss latency -system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 33816.053743 # average ReadReq mshr miss latency +system.cpu5.num_reads 100000 # number of read accesses completed +system.cpu5.num_writes 53740 # number of write accesses completed +system.cpu6.l1c.ReadReq_accesses 44447 # number of ReadReq accesses(hits+misses) +system.cpu6.l1c.ReadReq_avg_miss_latency 35088.024234 # average ReadReq miss latency +system.cpu6.l1c.ReadReq_avg_mshr_miss_latency 34084.129987 # average ReadReq mshr miss latency system.cpu6.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu6.l1c.ReadReq_hits 7473 # number of ReadReq hits -system.cpu6.l1c.ReadReq_miss_latency 1308739627 # number of ReadReq miss cycles -system.cpu6.l1c.ReadReq_miss_rate 0.834151 # miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_misses 37586 # number of ReadReq misses -system.cpu6.l1c.ReadReq_mshr_miss_latency 1271010196 # number of ReadReq MSHR miss cycles -system.cpu6.l1c.ReadReq_mshr_miss_rate 0.834151 # mshr miss rate for ReadReq accesses -system.cpu6.l1c.ReadReq_mshr_misses 37586 # number of ReadReq MSHR misses -system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 815633156 # number of ReadReq MSHR uncacheable cycles -system.cpu6.l1c.WriteReq_accesses 24310 # number of WriteReq accesses(hits+misses) -system.cpu6.l1c.WriteReq_avg_miss_latency 48931.121563 # average WriteReq miss latency -system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 47927.206055 # average WriteReq mshr miss latency +system.cpu6.l1c.ReadReq_hits 7474 # number of ReadReq hits +system.cpu6.l1c.ReadReq_miss_latency 1297309520 # number of ReadReq miss cycles +system.cpu6.l1c.ReadReq_miss_rate 0.831845 # miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_misses 36973 # number of ReadReq misses +system.cpu6.l1c.ReadReq_mshr_miss_latency 1260192538 # number of ReadReq MSHR miss cycles +system.cpu6.l1c.ReadReq_mshr_miss_rate 0.831845 # mshr miss rate for ReadReq accesses +system.cpu6.l1c.ReadReq_mshr_misses 36973 # number of ReadReq MSHR misses +system.cpu6.l1c.ReadReq_mshr_uncacheable_latency 822421052 # number of ReadReq MSHR uncacheable cycles +system.cpu6.l1c.WriteReq_accesses 24198 # number of WriteReq accesses(hits+misses) +system.cpu6.l1c.WriteReq_avg_miss_latency 49598.993348 # average WriteReq miss latency +system.cpu6.l1c.WriteReq_avg_mshr_miss_latency 48595.207082 # average WriteReq mshr miss latency system.cpu6.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu6.l1c.WriteReq_hits 923 # number of WriteReq hits -system.cpu6.l1c.WriteReq_miss_latency 1144352140 # number of WriteReq miss cycles -system.cpu6.l1c.WriteReq_miss_rate 0.962032 # miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_misses 23387 # number of WriteReq misses -system.cpu6.l1c.WriteReq_mshr_miss_latency 1120873568 # number of WriteReq MSHR miss cycles -system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962032 # mshr miss rate for WriteReq accesses -system.cpu6.l1c.WriteReq_mshr_misses 23387 # number of WriteReq MSHR misses -system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 545355496 # number of WriteReq MSHR uncacheable cycles -system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3751.801399 # average number of cycles each access was blocked +system.cpu6.l1c.WriteReq_hits 898 # number of WriteReq hits +system.cpu6.l1c.WriteReq_miss_latency 1155656545 # number of WriteReq miss cycles +system.cpu6.l1c.WriteReq_miss_rate 0.962889 # miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_misses 23300 # number of WriteReq misses +system.cpu6.l1c.WriteReq_mshr_miss_latency 1132268325 # number of WriteReq MSHR miss cycles +system.cpu6.l1c.WriteReq_mshr_miss_rate 0.962889 # mshr miss rate for WriteReq accesses +system.cpu6.l1c.WriteReq_mshr_misses 23300 # number of WriteReq MSHR misses +system.cpu6.l1c.WriteReq_mshr_uncacheable_latency 529109628 # number of WriteReq MSHR uncacheable cycles +system.cpu6.l1c.avg_blocked_cycles::no_mshrs 3801.306186 # average number of cycles each access was blocked system.cpu6.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu6.l1c.avg_refs 0.403583 # Average number of references to valid blocks. -system.cpu6.l1c.blocked::no_mshrs 69894 # number of cycles access was blocked +system.cpu6.l1c.avg_refs 0.409698 # Average number of references to valid blocks. +system.cpu6.l1c.blocked::no_mshrs 69363 # number of cycles access was blocked system.cpu6.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu6.l1c.blocked_cycles::no_mshrs 262228407 # number of cycles access was blocked +system.cpu6.l1c.blocked_cycles::no_mshrs 263670001 # number of cycles access was blocked system.cpu6.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu6.l1c.cache_copies 0 # number of cache copies performed -system.cpu6.l1c.demand_accesses 69369 # number of demand (read+write) accesses -system.cpu6.l1c.demand_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.demand_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency -system.cpu6.l1c.demand_hits 8396 # number of demand (read+write) hits -system.cpu6.l1c.demand_miss_latency 2453091767 # number of demand (read+write) miss cycles -system.cpu6.l1c.demand_miss_rate 0.878966 # miss rate for demand accesses -system.cpu6.l1c.demand_misses 60973 # number of demand (read+write) misses +system.cpu6.l1c.demand_accesses 68645 # number of demand (read+write) accesses +system.cpu6.l1c.demand_avg_miss_latency 40697.593699 # average overall miss latency +system.cpu6.l1c.demand_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency +system.cpu6.l1c.demand_hits 8372 # number of demand (read+write) hits +system.cpu6.l1c.demand_miss_latency 2452966065 # number of demand (read+write) miss cycles +system.cpu6.l1c.demand_miss_rate 0.878039 # miss rate for demand accesses +system.cpu6.l1c.demand_misses 60273 # number of demand (read+write) misses system.cpu6.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu6.l1c.demand_mshr_miss_latency 2391883764 # number of demand (read+write) MSHR miss cycles -system.cpu6.l1c.demand_mshr_miss_rate 0.878966 # mshr miss rate for demand accesses -system.cpu6.l1c.demand_mshr_misses 60973 # number of demand (read+write) MSHR misses +system.cpu6.l1c.demand_mshr_miss_latency 2392460863 # number of demand (read+write) MSHR miss cycles +system.cpu6.l1c.demand_mshr_miss_rate 0.878039 # mshr miss rate for demand accesses +system.cpu6.l1c.demand_mshr_misses 60273 # number of demand (read+write) MSHR misses system.cpu6.l1c.fast_writes 0 # number of fast writes performed system.cpu6.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu6.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu6.l1c.occ_%::0 0.675041 # Average percentage of cache occupancy -system.cpu6.l1c.occ_%::1 -0.003803 # Average percentage of cache occupancy -system.cpu6.l1c.occ_blocks::0 345.621031 # Average occupied blocks per context -system.cpu6.l1c.occ_blocks::1 -1.947349 # Average occupied blocks per context -system.cpu6.l1c.overall_accesses 69369 # number of overall (read+write) accesses -system.cpu6.l1c.overall_avg_miss_latency 40232.426927 # average overall miss latency -system.cpu6.l1c.overall_avg_mshr_miss_latency 39228.572713 # average overall mshr miss latency +system.cpu6.l1c.occ_%::0 0.676527 # Average percentage of cache occupancy +system.cpu6.l1c.occ_%::1 -0.006962 # Average percentage of cache occupancy +system.cpu6.l1c.occ_blocks::0 346.381949 # Average occupied blocks per context +system.cpu6.l1c.occ_blocks::1 -3.564360 # Average occupied blocks per context +system.cpu6.l1c.overall_accesses 68645 # number of overall (read+write) accesses +system.cpu6.l1c.overall_avg_miss_latency 40697.593699 # average overall miss latency +system.cpu6.l1c.overall_avg_mshr_miss_latency 39693.741194 # average overall mshr miss latency system.cpu6.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu6.l1c.overall_hits 8396 # number of overall hits -system.cpu6.l1c.overall_miss_latency 2453091767 # number of overall miss cycles -system.cpu6.l1c.overall_miss_rate 0.878966 # miss rate for overall accesses -system.cpu6.l1c.overall_misses 60973 # number of overall misses +system.cpu6.l1c.overall_hits 8372 # number of overall hits +system.cpu6.l1c.overall_miss_latency 2452966065 # number of overall miss cycles +system.cpu6.l1c.overall_miss_rate 0.878039 # miss rate for overall accesses +system.cpu6.l1c.overall_misses 60273 # number of overall misses system.cpu6.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu6.l1c.overall_mshr_miss_latency 2391883764 # number of overall MSHR miss cycles -system.cpu6.l1c.overall_mshr_miss_rate 0.878966 # mshr miss rate for overall accesses -system.cpu6.l1c.overall_mshr_misses 60973 # number of overall MSHR misses -system.cpu6.l1c.overall_mshr_uncacheable_latency 1360988652 # number of overall MSHR uncacheable cycles +system.cpu6.l1c.overall_mshr_miss_latency 2392460863 # number of overall MSHR miss cycles +system.cpu6.l1c.overall_mshr_miss_rate 0.878039 # mshr miss rate for overall accesses +system.cpu6.l1c.overall_mshr_misses 60273 # number of overall MSHR misses +system.cpu6.l1c.overall_mshr_uncacheable_latency 1351530680 # number of overall MSHR uncacheable cycles system.cpu6.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu6.l1c.replacements 28139 # number of replacements -system.cpu6.l1c.sampled_refs 28470 # Sample count of references to valid blocks. +system.cpu6.l1c.replacements 27642 # number of replacements +system.cpu6.l1c.sampled_refs 27984 # Sample count of references to valid blocks. system.cpu6.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu6.l1c.tagsinuse 343.673683 # Cycle average of tags in use -system.cpu6.l1c.total_refs 11490 # Total number of references to valid blocks. +system.cpu6.l1c.tagsinuse 342.817588 # Cycle average of tags in use +system.cpu6.l1c.total_refs 11465 # Total number of references to valid blocks. system.cpu6.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu6.l1c.writebacks 11130 # number of writebacks +system.cpu6.l1c.writebacks 10964 # number of writebacks system.cpu6.num_copies 0 # number of copy accesses completed -system.cpu6.num_reads 100000 # number of read accesses completed -system.cpu6.num_writes 54239 # number of write accesses completed -system.cpu7.l1c.ReadReq_accesses 44716 # number of ReadReq accesses(hits+misses) -system.cpu7.l1c.ReadReq_avg_miss_latency 35110.555319 # average ReadReq miss latency -system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 34106.579783 # average ReadReq mshr miss latency +system.cpu6.num_reads 98887 # number of read accesses completed +system.cpu6.num_writes 53455 # number of write accesses completed +system.cpu7.l1c.ReadReq_accesses 45091 # number of ReadReq accesses(hits+misses) +system.cpu7.l1c.ReadReq_avg_miss_latency 34987.655695 # average ReadReq miss latency +system.cpu7.l1c.ReadReq_avg_mshr_miss_latency 33983.814011 # average ReadReq mshr miss latency system.cpu7.l1c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.cpu7.l1c.ReadReq_hits 7559 # number of ReadReq hits -system.cpu7.l1c.ReadReq_miss_latency 1304602904 # number of ReadReq miss cycles -system.cpu7.l1c.ReadReq_miss_rate 0.830955 # miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_misses 37157 # number of ReadReq misses -system.cpu7.l1c.ReadReq_mshr_miss_latency 1267298185 # number of ReadReq MSHR miss cycles -system.cpu7.l1c.ReadReq_mshr_miss_rate 0.830955 # mshr miss rate for ReadReq accesses -system.cpu7.l1c.ReadReq_mshr_misses 37157 # number of ReadReq MSHR misses -system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 815723673 # number of ReadReq MSHR uncacheable cycles -system.cpu7.l1c.WriteReq_accesses 24205 # number of WriteReq accesses(hits+misses) -system.cpu7.l1c.WriteReq_avg_miss_latency 49444.663145 # average WriteReq miss latency -system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48440.833956 # average WriteReq mshr miss latency +system.cpu7.l1c.ReadReq_hits 7691 # number of ReadReq hits +system.cpu7.l1c.ReadReq_miss_latency 1308538323 # number of ReadReq miss cycles +system.cpu7.l1c.ReadReq_miss_rate 0.829434 # miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_misses 37400 # number of ReadReq misses +system.cpu7.l1c.ReadReq_mshr_miss_latency 1270994644 # number of ReadReq MSHR miss cycles +system.cpu7.l1c.ReadReq_mshr_miss_rate 0.829434 # mshr miss rate for ReadReq accesses +system.cpu7.l1c.ReadReq_mshr_misses 37400 # number of ReadReq MSHR misses +system.cpu7.l1c.ReadReq_mshr_uncacheable_latency 814528138 # number of ReadReq MSHR uncacheable cycles +system.cpu7.l1c.WriteReq_accesses 24179 # number of WriteReq accesses(hits+misses) +system.cpu7.l1c.WriteReq_avg_miss_latency 49459.078476 # average WriteReq miss latency +system.cpu7.l1c.WriteReq_avg_mshr_miss_latency 48455.291783 # average WriteReq mshr miss latency system.cpu7.l1c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.cpu7.l1c.WriteReq_hits 922 # number of WriteReq hits -system.cpu7.l1c.WriteReq_miss_latency 1151220092 # number of WriteReq miss cycles -system.cpu7.l1c.WriteReq_miss_rate 0.961909 # miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_misses 23283 # number of WriteReq misses -system.cpu7.l1c.WriteReq_mshr_miss_latency 1127847937 # number of WriteReq MSHR miss cycles -system.cpu7.l1c.WriteReq_mshr_miss_rate 0.961909 # mshr miss rate for WriteReq accesses -system.cpu7.l1c.WriteReq_mshr_misses 23283 # number of WriteReq MSHR misses -system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 536405254 # number of WriteReq MSHR uncacheable cycles -system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3782.889997 # average number of cycles each access was blocked +system.cpu7.l1c.WriteReq_hits 898 # number of WriteReq hits +system.cpu7.l1c.WriteReq_miss_latency 1151456806 # number of WriteReq miss cycles +system.cpu7.l1c.WriteReq_miss_rate 0.962860 # miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_misses 23281 # number of WriteReq misses +system.cpu7.l1c.WriteReq_mshr_miss_latency 1128087648 # number of WriteReq MSHR miss cycles +system.cpu7.l1c.WriteReq_mshr_miss_rate 0.962860 # mshr miss rate for WriteReq accesses +system.cpu7.l1c.WriteReq_mshr_misses 23281 # number of WriteReq MSHR misses +system.cpu7.l1c.WriteReq_mshr_uncacheable_latency 533243363 # number of WriteReq MSHR uncacheable cycles +system.cpu7.l1c.avg_blocked_cycles::no_mshrs 3781.140887 # average number of cycles each access was blocked system.cpu7.l1c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.cpu7.l1c.avg_refs 0.414017 # Average number of references to valid blocks. -system.cpu7.l1c.blocked::no_mshrs 69498 # number of cycles access was blocked +system.cpu7.l1c.avg_refs 0.414313 # Average number of references to valid blocks. +system.cpu7.l1c.blocked::no_mshrs 69687 # number of cycles access was blocked system.cpu7.l1c.blocked::no_targets 0 # number of cycles access was blocked -system.cpu7.l1c.blocked_cycles::no_mshrs 262903289 # number of cycles access was blocked +system.cpu7.l1c.blocked_cycles::no_mshrs 263496365 # number of cycles access was blocked system.cpu7.l1c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.cpu7.l1c.cache_copies 0 # number of cache copies performed -system.cpu7.l1c.demand_accesses 68921 # number of demand (read+write) accesses -system.cpu7.l1c.demand_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.demand_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency -system.cpu7.l1c.demand_hits 8481 # number of demand (read+write) hits -system.cpu7.l1c.demand_miss_latency 2455822996 # number of demand (read+write) miss cycles -system.cpu7.l1c.demand_miss_rate 0.876946 # miss rate for demand accesses -system.cpu7.l1c.demand_misses 60440 # number of demand (read+write) misses +system.cpu7.l1c.demand_accesses 69270 # number of demand (read+write) accesses +system.cpu7.l1c.demand_avg_miss_latency 40539.792175 # average overall miss latency +system.cpu7.l1c.demand_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency +system.cpu7.l1c.demand_hits 8589 # number of demand (read+write) hits +system.cpu7.l1c.demand_miss_latency 2459995129 # number of demand (read+write) miss cycles +system.cpu7.l1c.demand_miss_rate 0.876007 # miss rate for demand accesses +system.cpu7.l1c.demand_misses 60681 # number of demand (read+write) misses system.cpu7.l1c.demand_mshr_hits 0 # number of demand (read+write) MSHR hits -system.cpu7.l1c.demand_mshr_miss_latency 2395146122 # number of demand (read+write) MSHR miss cycles -system.cpu7.l1c.demand_mshr_miss_rate 0.876946 # mshr miss rate for demand accesses -system.cpu7.l1c.demand_mshr_misses 60440 # number of demand (read+write) MSHR misses +system.cpu7.l1c.demand_mshr_miss_latency 2399082292 # number of demand (read+write) MSHR miss cycles +system.cpu7.l1c.demand_mshr_miss_rate 0.876007 # mshr miss rate for demand accesses +system.cpu7.l1c.demand_mshr_misses 60681 # number of demand (read+write) MSHR misses system.cpu7.l1c.fast_writes 0 # number of fast writes performed system.cpu7.l1c.mshr_cap_events 0 # number of times MSHR cap was activated system.cpu7.l1c.no_allocate_misses 0 # Number of misses that were no-allocate -system.cpu7.l1c.occ_%::0 0.676947 # Average percentage of cache occupancy -system.cpu7.l1c.occ_%::1 -0.001736 # Average percentage of cache occupancy -system.cpu7.l1c.occ_blocks::0 346.596700 # Average occupied blocks per context -system.cpu7.l1c.occ_blocks::1 -0.888916 # Average occupied blocks per context -system.cpu7.l1c.overall_accesses 68921 # number of overall (read+write) accesses -system.cpu7.l1c.overall_avg_miss_latency 40632.412244 # average overall miss latency -system.cpu7.l1c.overall_avg_mshr_miss_latency 39628.493084 # average overall mshr miss latency +system.cpu7.l1c.occ_%::0 0.680280 # Average percentage of cache occupancy +system.cpu7.l1c.occ_%::1 -0.007590 # Average percentage of cache occupancy +system.cpu7.l1c.occ_blocks::0 348.303356 # Average occupied blocks per context +system.cpu7.l1c.occ_blocks::1 -3.885943 # Average occupied blocks per context +system.cpu7.l1c.overall_accesses 69270 # number of overall (read+write) accesses +system.cpu7.l1c.overall_avg_miss_latency 40539.792175 # average overall miss latency +system.cpu7.l1c.overall_avg_mshr_miss_latency 39535.971589 # average overall mshr miss latency system.cpu7.l1c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.cpu7.l1c.overall_hits 8481 # number of overall hits -system.cpu7.l1c.overall_miss_latency 2455822996 # number of overall miss cycles -system.cpu7.l1c.overall_miss_rate 0.876946 # miss rate for overall accesses -system.cpu7.l1c.overall_misses 60440 # number of overall misses +system.cpu7.l1c.overall_hits 8589 # number of overall hits +system.cpu7.l1c.overall_miss_latency 2459995129 # number of overall miss cycles +system.cpu7.l1c.overall_miss_rate 0.876007 # miss rate for overall accesses +system.cpu7.l1c.overall_misses 60681 # number of overall misses system.cpu7.l1c.overall_mshr_hits 0 # number of overall MSHR hits -system.cpu7.l1c.overall_mshr_miss_latency 2395146122 # number of overall MSHR miss cycles -system.cpu7.l1c.overall_mshr_miss_rate 0.876946 # mshr miss rate for overall accesses -system.cpu7.l1c.overall_mshr_misses 60440 # number of overall MSHR misses -system.cpu7.l1c.overall_mshr_uncacheable_latency 1352128927 # number of overall MSHR uncacheable cycles +system.cpu7.l1c.overall_mshr_miss_latency 2399082292 # number of overall MSHR miss cycles +system.cpu7.l1c.overall_mshr_miss_rate 0.876007 # mshr miss rate for overall accesses +system.cpu7.l1c.overall_mshr_misses 60681 # number of overall MSHR misses +system.cpu7.l1c.overall_mshr_uncacheable_latency 1347771501 # number of overall MSHR uncacheable cycles system.cpu7.l1c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.cpu7.l1c.replacements 27627 # number of replacements -system.cpu7.l1c.sampled_refs 27994 # Sample count of references to valid blocks. +system.cpu7.l1c.replacements 28023 # number of replacements +system.cpu7.l1c.sampled_refs 28394 # Sample count of references to valid blocks. system.cpu7.l1c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.cpu7.l1c.tagsinuse 345.707784 # Cycle average of tags in use -system.cpu7.l1c.total_refs 11590 # Total number of references to valid blocks. +system.cpu7.l1c.tagsinuse 345.385459 # Cycle average of tags in use +system.cpu7.l1c.total_refs 11764 # Total number of references to valid blocks. system.cpu7.l1c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.cpu7.l1c.writebacks 10984 # number of writebacks +system.cpu7.l1c.writebacks 11064 # number of writebacks system.cpu7.num_copies 0 # number of copy accesses completed -system.cpu7.num_reads 99634 # number of read accesses completed -system.cpu7.num_writes 53744 # number of write accesses completed -system.l2c.ReadExReq_accesses::0 9360 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::1 9426 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::2 9454 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::3 9421 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::4 9377 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::5 9282 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::6 9385 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::7 9437 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_accesses::total 75142 # number of ReadExReq accesses(hits+misses) -system.l2c.ReadExReq_avg_miss_latency::0 400291.554701 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::1 397488.749417 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::2 396311.503279 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::3 397699.708311 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::4 399565.847499 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::5 403655.349278 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::6 399225.247949 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::7 397025.426725 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_miss_latency::total 3191263.387158 # average ReadExReq miss latency -system.l2c.ReadExReq_avg_mshr_miss_latency 39995.605218 # average ReadExReq mshr miss latency -system.l2c.ReadExReq_miss_latency 3746728952 # number of ReadExReq miss cycles +system.cpu7.num_reads 99565 # number of read accesses completed +system.cpu7.num_writes 53846 # number of write accesses completed +system.l2c.ReadExReq_accesses::0 9412 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::1 9288 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::2 9313 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::3 9344 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::4 9463 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::5 9358 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::6 9360 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::7 9364 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::total 74902 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_avg_miss_latency::0 396995.145984 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::1 402295.253445 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::2 401215.324171 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::3 399884.237372 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::4 394855.575822 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::5 399285.992092 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::6 399200.674573 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::7 399030.148868 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_miss_latency::total 3192762.352326 # average ReadExReq miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency 39999.222355 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_miss_latency 3736518314 # number of ReadExReq miss cycles system.l2c.ReadExReq_miss_rate::0 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::1 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::2 1 # miss rate for ReadExReq accesses @@ -627,108 +627,108 @@ system.l2c.ReadExReq_miss_rate::6 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::7 1 # miss rate for ReadExReq accesses system.l2c.ReadExReq_miss_rate::total 8 # miss rate for ReadExReq accesses -system.l2c.ReadExReq_misses::0 9360 # number of ReadExReq misses -system.l2c.ReadExReq_misses::1 9426 # number of ReadExReq misses -system.l2c.ReadExReq_misses::2 9454 # number of ReadExReq misses -system.l2c.ReadExReq_misses::3 9421 # number of ReadExReq misses -system.l2c.ReadExReq_misses::4 9377 # number of ReadExReq misses -system.l2c.ReadExReq_misses::5 9282 # number of ReadExReq misses -system.l2c.ReadExReq_misses::6 9385 # number of ReadExReq misses -system.l2c.ReadExReq_misses::7 9437 # number of ReadExReq misses -system.l2c.ReadExReq_misses::total 75142 # number of ReadExReq misses -system.l2c.ReadExReq_mshr_hits 587 # number of ReadExReq MSHR hits -system.l2c.ReadExReq_mshr_miss_latency 2981872347 # number of ReadExReq MSHR miss cycles -system.l2c.ReadExReq_mshr_miss_rate::0 7.965278 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::1 7.909506 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::2 7.886080 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::3 7.913703 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::4 7.950837 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::5 8.032213 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::6 7.944060 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::7 7.900286 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_miss_rate::total 63.501963 # mshr miss rate for ReadExReq accesses -system.l2c.ReadExReq_mshr_misses 74555 # number of ReadExReq MSHR misses -system.l2c.ReadReq_accesses::0 17364 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::1 17185 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::2 17073 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::3 17340 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::4 17244 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::5 17349 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::6 17201 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::7 17166 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_accesses::total 137922 # number of ReadReq accesses(hits+misses) -system.l2c.ReadReq_avg_miss_latency::0 396394.393314 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::1 396328.481377 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::2 399048.968190 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::3 396065.052675 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::4 402281.769958 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::5 398581.854013 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::6 391254.019534 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::7 397187.049992 # average ReadReq miss latency -system.l2c.ReadReq_avg_miss_latency::total 3177141.589053 # average ReadReq miss latency -system.l2c.ReadReq_avg_mshr_miss_latency 39996.564362 # average ReadReq mshr miss latency +system.l2c.ReadExReq_misses::0 9412 # number of ReadExReq misses +system.l2c.ReadExReq_misses::1 9288 # number of ReadExReq misses +system.l2c.ReadExReq_misses::2 9313 # number of ReadExReq misses +system.l2c.ReadExReq_misses::3 9344 # number of ReadExReq misses +system.l2c.ReadExReq_misses::4 9463 # number of ReadExReq misses +system.l2c.ReadExReq_misses::5 9358 # number of ReadExReq misses +system.l2c.ReadExReq_misses::6 9360 # number of ReadExReq misses +system.l2c.ReadExReq_misses::7 9364 # number of ReadExReq misses +system.l2c.ReadExReq_misses::total 74902 # number of ReadExReq misses +system.l2c.ReadExReq_mshr_hits 557 # number of ReadExReq MSHR hits +system.l2c.ReadExReq_mshr_miss_latency 2973742186 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_rate::0 7.898959 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::1 8.004414 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::2 7.982927 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::3 7.956443 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::4 7.856388 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::5 7.944539 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::6 7.942842 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::7 7.939449 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::total 63.525961 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_misses 74345 # number of ReadExReq MSHR misses +system.l2c.ReadReq_accesses::0 17188 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::1 17330 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::2 17220 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::3 17498 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::4 17144 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::5 17272 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::6 17157 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::7 17383 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 138192 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_avg_miss_latency::0 401579.741645 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::1 391420.730324 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::2 401239.419831 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::3 391097.402445 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::4 398873.222746 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::5 393306.625187 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::6 405084.287645 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::7 395078.867991 # average ReadReq miss latency +system.l2c.ReadReq_avg_miss_latency::total 3177680.297815 # average ReadReq miss latency +system.l2c.ReadReq_avg_mshr_miss_latency 40002.426325 # average ReadReq mshr miss latency system.l2c.ReadReq_avg_mshr_uncacheable_latency inf # average ReadReq mshr uncacheable latency -system.l2c.ReadReq_hits::0 11351 # number of ReadReq hits -system.l2c.ReadReq_hits::1 11171 # number of ReadReq hits -system.l2c.ReadReq_hits::2 11100 # number of ReadReq hits -system.l2c.ReadReq_hits::3 11322 # number of ReadReq hits -system.l2c.ReadReq_hits::4 11319 # number of ReadReq hits -system.l2c.ReadReq_hits::5 11369 # number of ReadReq hits -system.l2c.ReadReq_hits::6 11109 # number of ReadReq hits -system.l2c.ReadReq_hits::7 11165 # number of ReadReq hits -system.l2c.ReadReq_hits::total 89906 # number of ReadReq hits -system.l2c.ReadReq_miss_latency 2383519487 # number of ReadReq miss cycles -system.l2c.ReadReq_miss_rate::0 0.346291 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::1 0.349956 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::2 0.349851 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::3 0.347059 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::4 0.343598 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::5 0.344688 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::6 0.354165 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::7 0.349586 # miss rate for ReadReq accesses -system.l2c.ReadReq_miss_rate::total 2.785195 # miss rate for ReadReq accesses -system.l2c.ReadReq_misses::0 6013 # number of ReadReq misses -system.l2c.ReadReq_misses::1 6014 # number of ReadReq misses -system.l2c.ReadReq_misses::2 5973 # number of ReadReq misses -system.l2c.ReadReq_misses::3 6018 # number of ReadReq misses -system.l2c.ReadReq_misses::4 5925 # number of ReadReq misses -system.l2c.ReadReq_misses::5 5980 # number of ReadReq misses -system.l2c.ReadReq_misses::6 6092 # number of ReadReq misses -system.l2c.ReadReq_misses::7 6001 # number of ReadReq misses -system.l2c.ReadReq_misses::total 48016 # number of ReadReq misses -system.l2c.ReadReq_mshr_hits 1016 # number of ReadReq MSHR hits -system.l2c.ReadReq_mshr_miss_latency 1879838525 # number of ReadReq MSHR miss cycles -system.l2c.ReadReq_mshr_miss_rate::0 2.706750 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::1 2.734943 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::2 2.752885 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::3 2.710496 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::4 2.725586 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::5 2.709090 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::6 2.732399 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::7 2.737970 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_miss_rate::total 21.810119 # mshr miss rate for ReadReq accesses -system.l2c.ReadReq_mshr_misses 47000 # number of ReadReq MSHR misses -system.l2c.ReadReq_mshr_uncacheable_latency 3163753169 # number of ReadReq MSHR uncacheable cycles -system.l2c.UpgradeReq_accesses::0 2273 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::1 2288 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::2 2314 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::3 2311 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::4 2383 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::5 2289 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::6 2257 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::7 2313 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_accesses::total 18428 # number of UpgradeReq accesses(hits+misses) -system.l2c.UpgradeReq_avg_miss_latency::0 226995.596128 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::1 225507.425699 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::2 222973.634399 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::3 223263.085244 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::4 216517.410827 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::5 225408.907820 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::6 228604.780682 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::7 223070.034587 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_miss_latency::total 1792340.875388 # average UpgradeReq miss latency -system.l2c.UpgradeReq_avg_mshr_miss_latency 39992.012512 # average UpgradeReq mshr miss latency -system.l2c.UpgradeReq_miss_latency 515960990 # number of UpgradeReq miss cycles +system.l2c.ReadReq_hits::0 11293 # number of ReadReq hits +system.l2c.ReadReq_hits::1 11282 # number of ReadReq hits +system.l2c.ReadReq_hits::2 11320 # number of ReadReq hits +system.l2c.ReadReq_hits::3 11445 # number of ReadReq hits +system.l2c.ReadReq_hits::4 11209 # number of ReadReq hits +system.l2c.ReadReq_hits::5 11253 # number of ReadReq hits +system.l2c.ReadReq_hits::6 11313 # number of ReadReq hits +system.l2c.ReadReq_hits::7 11391 # number of ReadReq hits +system.l2c.ReadReq_hits::total 90506 # number of ReadReq hits +system.l2c.ReadReq_miss_latency 2367312577 # number of ReadReq miss cycles +system.l2c.ReadReq_miss_rate::0 0.342972 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::1 0.348990 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::2 0.342625 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::3 0.345925 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::4 0.346185 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::5 0.348483 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::6 0.340619 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::7 0.344705 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::total 2.760504 # miss rate for ReadReq accesses +system.l2c.ReadReq_misses::0 5895 # number of ReadReq misses +system.l2c.ReadReq_misses::1 6048 # number of ReadReq misses +system.l2c.ReadReq_misses::2 5900 # number of ReadReq misses +system.l2c.ReadReq_misses::3 6053 # number of ReadReq misses +system.l2c.ReadReq_misses::4 5935 # number of ReadReq misses +system.l2c.ReadReq_misses::5 6019 # number of ReadReq misses +system.l2c.ReadReq_misses::6 5844 # number of ReadReq misses +system.l2c.ReadReq_misses::7 5992 # number of ReadReq misses +system.l2c.ReadReq_misses::total 47686 # number of ReadReq misses +system.l2c.ReadReq_mshr_hits 1069 # number of ReadReq MSHR hits +system.l2c.ReadReq_mshr_miss_latency 1864793108 # number of ReadReq MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::0 2.712183 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::1 2.689960 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::2 2.707143 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::3 2.664133 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::4 2.719144 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::5 2.698993 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::6 2.717083 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::7 2.681758 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::total 21.590396 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_misses 46617 # number of ReadReq MSHR misses +system.l2c.ReadReq_mshr_uncacheable_latency 3184396233 # number of ReadReq MSHR uncacheable cycles +system.l2c.UpgradeReq_accesses::0 2342 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::1 2293 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::2 2237 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::3 2252 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::4 2274 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::5 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::6 2351 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::7 2359 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 18459 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_avg_miss_latency::0 217987.236123 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::1 222645.489315 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::2 228219.091194 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::3 226698.981794 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::4 224505.763852 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::5 217152.746491 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::6 217152.746491 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::7 216416.323442 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_miss_latency::total 1770778.378702 # average UpgradeReq miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency 40000.703945 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_miss_latency 510526107 # number of UpgradeReq miss cycles system.l2c.UpgradeReq_miss_rate::0 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::1 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::2 1 # miss rate for UpgradeReq accesses @@ -738,189 +738,189 @@ system.l2c.UpgradeReq_miss_rate::6 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::7 1 # miss rate for UpgradeReq accesses system.l2c.UpgradeReq_miss_rate::total 8 # miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_misses::0 2273 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::1 2288 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::2 2314 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::3 2311 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::4 2383 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::5 2289 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::6 2257 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::7 2313 # number of UpgradeReq misses -system.l2c.UpgradeReq_misses::total 18428 # number of UpgradeReq misses -system.l2c.UpgradeReq_mshr_hits 45 # number of UpgradeReq MSHR hits -system.l2c.UpgradeReq_mshr_miss_latency 735173166 # number of UpgradeReq MSHR miss cycles -system.l2c.UpgradeReq_mshr_miss_rate::0 8.087549 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::1 8.034528 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::2 7.944252 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::3 7.954565 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::4 7.714226 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::5 8.031018 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::6 8.144883 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::7 7.947687 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_miss_rate::total 63.858708 # mshr miss rate for UpgradeReq accesses -system.l2c.UpgradeReq_mshr_misses 18383 # number of UpgradeReq MSHR misses +system.l2c.UpgradeReq_misses::0 2342 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::1 2293 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::2 2237 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::3 2252 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::4 2274 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::5 2351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::6 2351 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::7 2359 # number of UpgradeReq misses +system.l2c.UpgradeReq_misses::total 18459 # number of UpgradeReq misses +system.l2c.UpgradeReq_mshr_hits 57 # number of UpgradeReq MSHR hits +system.l2c.UpgradeReq_mshr_miss_latency 736092954 # number of UpgradeReq MSHR miss cycles +system.l2c.UpgradeReq_mshr_miss_rate::0 7.857387 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::1 8.025294 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::2 8.226196 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::3 8.171403 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::4 8.092348 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::5 7.827308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::6 7.827308 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::7 7.800763 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::total 63.828007 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_misses 18402 # number of UpgradeReq MSHR misses system.l2c.WriteReq_avg_mshr_uncacheable_latency inf # average WriteReq mshr uncacheable latency -system.l2c.WriteReq_mshr_uncacheable_latency 1717039696 # number of WriteReq MSHR uncacheable cycles -system.l2c.Writeback_accesses::0 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_accesses::total 86929 # number of Writeback accesses(hits+misses) -system.l2c.Writeback_hits::0 86929 # number of Writeback hits -system.l2c.Writeback_hits::total 86929 # number of Writeback hits -system.l2c.avg_blocked_cycles::no_mshrs 7154.090909 # average number of cycles each access was blocked +system.l2c.WriteReq_mshr_uncacheable_latency 1720878838 # number of WriteReq MSHR uncacheable cycles +system.l2c.Writeback_accesses::0 86764 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 86764 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_hits::0 86764 # number of Writeback hits +system.l2c.Writeback_hits::total 86764 # number of Writeback hits +system.l2c.avg_blocked_cycles::no_mshrs 6575.500000 # average number of cycles each access was blocked system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked -system.l2c.avg_refs 2.005630 # Average number of references to valid blocks. -system.l2c.blocked::no_mshrs 11 # number of cycles access was blocked +system.l2c.avg_refs 2.025850 # Average number of references to valid blocks. +system.l2c.blocked::no_mshrs 22 # number of cycles access was blocked system.l2c.blocked::no_targets 0 # number of cycles access was blocked -system.l2c.blocked_cycles::no_mshrs 78695 # number of cycles access was blocked +system.l2c.blocked_cycles::no_mshrs 144661 # number of cycles access was blocked system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked system.l2c.cache_copies 0 # number of cache copies performed -system.l2c.demand_accesses::0 26724 # number of demand (read+write) accesses -system.l2c.demand_accesses::1 26611 # number of demand (read+write) accesses -system.l2c.demand_accesses::2 26527 # number of demand (read+write) accesses -system.l2c.demand_accesses::3 26761 # number of demand (read+write) accesses -system.l2c.demand_accesses::4 26621 # number of demand (read+write) accesses -system.l2c.demand_accesses::5 26631 # number of demand (read+write) accesses -system.l2c.demand_accesses::6 26586 # number of demand (read+write) accesses -system.l2c.demand_accesses::7 26603 # number of demand (read+write) accesses -system.l2c.demand_accesses::total 213064 # number of demand (read+write) accesses -system.l2c.demand_avg_miss_latency::0 398767.217784 # average overall miss latency -system.l2c.demand_avg_miss_latency::1 397036.815997 # average overall miss latency -system.l2c.demand_avg_miss_latency::2 397371.390355 # average overall miss latency -system.l2c.demand_avg_miss_latency::3 397062.532483 # average overall miss latency -system.l2c.demand_avg_miss_latency::4 400617.464318 # average overall miss latency -system.l2c.demand_avg_miss_latency::5 401667.438016 # average overall miss latency -system.l2c.demand_avg_miss_latency::6 396087.642243 # average overall miss latency -system.l2c.demand_avg_miss_latency::7 397088.252300 # average overall miss latency -system.l2c.demand_avg_miss_latency::total 3185698.753496 # average overall miss latency -system.l2c.demand_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency -system.l2c.demand_hits::0 11351 # number of demand (read+write) hits -system.l2c.demand_hits::1 11171 # number of demand (read+write) hits -system.l2c.demand_hits::2 11100 # number of demand (read+write) hits -system.l2c.demand_hits::3 11322 # number of demand (read+write) hits -system.l2c.demand_hits::4 11319 # number of demand (read+write) hits -system.l2c.demand_hits::5 11369 # number of demand (read+write) hits -system.l2c.demand_hits::6 11109 # number of demand (read+write) hits -system.l2c.demand_hits::7 11165 # number of demand (read+write) hits -system.l2c.demand_hits::total 89906 # number of demand (read+write) hits -system.l2c.demand_miss_latency 6130248439 # number of demand (read+write) miss cycles -system.l2c.demand_miss_rate::0 0.575251 # miss rate for demand accesses -system.l2c.demand_miss_rate::1 0.580211 # miss rate for demand accesses -system.l2c.demand_miss_rate::2 0.581558 # miss rate for demand accesses -system.l2c.demand_miss_rate::3 0.576922 # miss rate for demand accesses -system.l2c.demand_miss_rate::4 0.574809 # miss rate for demand accesses -system.l2c.demand_miss_rate::5 0.573092 # miss rate for demand accesses -system.l2c.demand_miss_rate::6 0.582148 # miss rate for demand accesses -system.l2c.demand_miss_rate::7 0.580310 # miss rate for demand accesses -system.l2c.demand_miss_rate::total 4.624302 # miss rate for demand accesses -system.l2c.demand_misses::0 15373 # number of demand (read+write) misses -system.l2c.demand_misses::1 15440 # number of demand (read+write) misses -system.l2c.demand_misses::2 15427 # number of demand (read+write) misses -system.l2c.demand_misses::3 15439 # number of demand (read+write) misses -system.l2c.demand_misses::4 15302 # number of demand (read+write) misses -system.l2c.demand_misses::5 15262 # number of demand (read+write) misses -system.l2c.demand_misses::6 15477 # number of demand (read+write) misses -system.l2c.demand_misses::7 15438 # number of demand (read+write) misses -system.l2c.demand_misses::total 123158 # number of demand (read+write) misses -system.l2c.demand_mshr_hits 1603 # number of demand (read+write) MSHR hits -system.l2c.demand_mshr_miss_latency 4861710872 # number of demand (read+write) MSHR miss cycles -system.l2c.demand_mshr_miss_rate::0 4.548533 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::1 4.567848 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::2 4.582312 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::3 4.542244 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::4 4.566132 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::5 4.564417 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::6 4.572143 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::7 4.569222 # mshr miss rate for demand accesses -system.l2c.demand_mshr_miss_rate::total 36.512852 # mshr miss rate for demand accesses -system.l2c.demand_mshr_misses 121555 # number of demand (read+write) MSHR misses +system.l2c.demand_accesses::0 26600 # number of demand (read+write) accesses +system.l2c.demand_accesses::1 26618 # number of demand (read+write) accesses +system.l2c.demand_accesses::2 26533 # number of demand (read+write) accesses +system.l2c.demand_accesses::3 26842 # number of demand (read+write) accesses +system.l2c.demand_accesses::4 26607 # number of demand (read+write) accesses +system.l2c.demand_accesses::5 26630 # number of demand (read+write) accesses +system.l2c.demand_accesses::6 26517 # number of demand (read+write) accesses +system.l2c.demand_accesses::7 26747 # number of demand (read+write) accesses +system.l2c.demand_accesses::total 213094 # number of demand (read+write) accesses +system.l2c.demand_avg_miss_latency::0 398760.755929 # average overall miss latency +system.l2c.demand_avg_miss_latency::1 398006.709116 # average overall miss latency +system.l2c.demand_avg_miss_latency::2 401224.669099 # average overall miss latency +system.l2c.demand_avg_miss_latency::3 396429.881860 # average overall miss latency +system.l2c.demand_avg_miss_latency::4 396404.136316 # average overall miss latency +system.l2c.demand_avg_miss_latency::5 396945.495935 # average overall miss latency +system.l2c.demand_avg_miss_latency::6 401462.173836 # average overall miss latency +system.l2c.demand_avg_miss_latency::7 397488.336220 # average overall miss latency +system.l2c.demand_avg_miss_latency::total 3186722.158311 # average overall miss latency +system.l2c.demand_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency +system.l2c.demand_hits::0 11293 # number of demand (read+write) hits +system.l2c.demand_hits::1 11282 # number of demand (read+write) hits +system.l2c.demand_hits::2 11320 # number of demand (read+write) hits +system.l2c.demand_hits::3 11445 # number of demand (read+write) hits +system.l2c.demand_hits::4 11209 # number of demand (read+write) hits +system.l2c.demand_hits::5 11253 # number of demand (read+write) hits +system.l2c.demand_hits::6 11313 # number of demand (read+write) hits +system.l2c.demand_hits::7 11391 # number of demand (read+write) hits +system.l2c.demand_hits::total 90506 # number of demand (read+write) hits +system.l2c.demand_miss_latency 6103830891 # number of demand (read+write) miss cycles +system.l2c.demand_miss_rate::0 0.575451 # miss rate for demand accesses +system.l2c.demand_miss_rate::1 0.576151 # miss rate for demand accesses +system.l2c.demand_miss_rate::2 0.573361 # miss rate for demand accesses +system.l2c.demand_miss_rate::3 0.573616 # miss rate for demand accesses +system.l2c.demand_miss_rate::4 0.578720 # miss rate for demand accesses +system.l2c.demand_miss_rate::5 0.577431 # miss rate for demand accesses +system.l2c.demand_miss_rate::6 0.573368 # miss rate for demand accesses +system.l2c.demand_miss_rate::7 0.574120 # miss rate for demand accesses +system.l2c.demand_miss_rate::total 4.602220 # miss rate for demand accesses +system.l2c.demand_misses::0 15307 # number of demand (read+write) misses +system.l2c.demand_misses::1 15336 # number of demand (read+write) misses +system.l2c.demand_misses::2 15213 # number of demand (read+write) misses +system.l2c.demand_misses::3 15397 # number of demand (read+write) misses +system.l2c.demand_misses::4 15398 # number of demand (read+write) misses +system.l2c.demand_misses::5 15377 # number of demand (read+write) misses +system.l2c.demand_misses::6 15204 # number of demand (read+write) misses +system.l2c.demand_misses::7 15356 # number of demand (read+write) misses +system.l2c.demand_misses::total 122588 # number of demand (read+write) misses +system.l2c.demand_mshr_hits 1626 # number of demand (read+write) MSHR hits +system.l2c.demand_mshr_miss_latency 4838535294 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_rate::0 4.547444 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::1 4.544368 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::2 4.558927 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::3 4.506445 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::4 4.546247 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::5 4.542321 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::6 4.561677 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::7 4.522451 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::total 36.329880 # mshr miss rate for demand accesses +system.l2c.demand_mshr_misses 120962 # number of demand (read+write) MSHR misses system.l2c.fast_writes 0 # number of fast writes performed system.l2c.mshr_cap_events 0 # number of times MSHR cap was activated system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate -system.l2c.occ_%::0 0.025896 # Average percentage of cache occupancy -system.l2c.occ_%::1 0.025716 # Average percentage of cache occupancy -system.l2c.occ_%::2 0.025892 # Average percentage of cache occupancy -system.l2c.occ_%::3 0.026232 # Average percentage of cache occupancy -system.l2c.occ_%::4 0.025792 # Average percentage of cache occupancy -system.l2c.occ_%::5 0.026195 # Average percentage of cache occupancy -system.l2c.occ_%::6 0.026471 # Average percentage of cache occupancy -system.l2c.occ_%::7 0.026663 # Average percentage of cache occupancy -system.l2c.occ_%::8 0.410030 # Average percentage of cache occupancy -system.l2c.occ_blocks::0 26.517416 # Average occupied blocks per context -system.l2c.occ_blocks::1 26.332816 # Average occupied blocks per context -system.l2c.occ_blocks::2 26.512954 # Average occupied blocks per context -system.l2c.occ_blocks::3 26.861209 # Average occupied blocks per context -system.l2c.occ_blocks::4 26.410697 # Average occupied blocks per context -system.l2c.occ_blocks::5 26.823356 # Average occupied blocks per context -system.l2c.occ_blocks::6 27.106140 # Average occupied blocks per context -system.l2c.occ_blocks::7 27.302482 # Average occupied blocks per context -system.l2c.occ_blocks::8 419.870758 # Average occupied blocks per context -system.l2c.overall_accesses::0 26724 # number of overall (read+write) accesses -system.l2c.overall_accesses::1 26611 # number of overall (read+write) accesses -system.l2c.overall_accesses::2 26527 # number of overall (read+write) accesses -system.l2c.overall_accesses::3 26761 # number of overall (read+write) accesses -system.l2c.overall_accesses::4 26621 # number of overall (read+write) accesses -system.l2c.overall_accesses::5 26631 # number of overall (read+write) accesses -system.l2c.overall_accesses::6 26586 # number of overall (read+write) accesses -system.l2c.overall_accesses::7 26603 # number of overall (read+write) accesses -system.l2c.overall_accesses::total 213064 # number of overall (read+write) accesses -system.l2c.overall_avg_miss_latency::0 398767.217784 # average overall miss latency -system.l2c.overall_avg_miss_latency::1 397036.815997 # average overall miss latency -system.l2c.overall_avg_miss_latency::2 397371.390355 # average overall miss latency -system.l2c.overall_avg_miss_latency::3 397062.532483 # average overall miss latency -system.l2c.overall_avg_miss_latency::4 400617.464318 # average overall miss latency -system.l2c.overall_avg_miss_latency::5 401667.438016 # average overall miss latency -system.l2c.overall_avg_miss_latency::6 396087.642243 # average overall miss latency -system.l2c.overall_avg_miss_latency::7 397088.252300 # average overall miss latency -system.l2c.overall_avg_miss_latency::total 3185698.753496 # average overall miss latency -system.l2c.overall_avg_mshr_miss_latency 39995.976077 # average overall mshr miss latency +system.l2c.occ_%::0 0.025853 # Average percentage of cache occupancy +system.l2c.occ_%::1 0.026694 # Average percentage of cache occupancy +system.l2c.occ_%::2 0.026105 # Average percentage of cache occupancy +system.l2c.occ_%::3 0.026914 # Average percentage of cache occupancy +system.l2c.occ_%::4 0.026038 # Average percentage of cache occupancy +system.l2c.occ_%::5 0.026270 # Average percentage of cache occupancy +system.l2c.occ_%::6 0.025331 # Average percentage of cache occupancy +system.l2c.occ_%::7 0.026254 # Average percentage of cache occupancy +system.l2c.occ_%::8 0.409154 # Average percentage of cache occupancy +system.l2c.occ_blocks::0 26.473544 # Average occupied blocks per context +system.l2c.occ_blocks::1 27.334486 # Average occupied blocks per context +system.l2c.occ_blocks::2 26.731121 # Average occupied blocks per context +system.l2c.occ_blocks::3 27.560151 # Average occupied blocks per context +system.l2c.occ_blocks::4 26.663054 # Average occupied blocks per context +system.l2c.occ_blocks::5 26.900488 # Average occupied blocks per context +system.l2c.occ_blocks::6 25.938523 # Average occupied blocks per context +system.l2c.occ_blocks::7 26.884287 # Average occupied blocks per context +system.l2c.occ_blocks::8 418.973617 # Average occupied blocks per context +system.l2c.overall_accesses::0 26600 # number of overall (read+write) accesses +system.l2c.overall_accesses::1 26618 # number of overall (read+write) accesses +system.l2c.overall_accesses::2 26533 # number of overall (read+write) accesses +system.l2c.overall_accesses::3 26842 # number of overall (read+write) accesses +system.l2c.overall_accesses::4 26607 # number of overall (read+write) accesses +system.l2c.overall_accesses::5 26630 # number of overall (read+write) accesses +system.l2c.overall_accesses::6 26517 # number of overall (read+write) accesses +system.l2c.overall_accesses::7 26747 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 213094 # number of overall (read+write) accesses +system.l2c.overall_avg_miss_latency::0 398760.755929 # average overall miss latency +system.l2c.overall_avg_miss_latency::1 398006.709116 # average overall miss latency +system.l2c.overall_avg_miss_latency::2 401224.669099 # average overall miss latency +system.l2c.overall_avg_miss_latency::3 396429.881860 # average overall miss latency +system.l2c.overall_avg_miss_latency::4 396404.136316 # average overall miss latency +system.l2c.overall_avg_miss_latency::5 396945.495935 # average overall miss latency +system.l2c.overall_avg_miss_latency::6 401462.173836 # average overall miss latency +system.l2c.overall_avg_miss_latency::7 397488.336220 # average overall miss latency +system.l2c.overall_avg_miss_latency::total 3186722.158311 # average overall miss latency +system.l2c.overall_avg_mshr_miss_latency 40000.457119 # average overall mshr miss latency system.l2c.overall_avg_mshr_uncacheable_latency inf # average overall mshr uncacheable latency -system.l2c.overall_hits::0 11351 # number of overall hits -system.l2c.overall_hits::1 11171 # number of overall hits -system.l2c.overall_hits::2 11100 # number of overall hits -system.l2c.overall_hits::3 11322 # number of overall hits -system.l2c.overall_hits::4 11319 # number of overall hits -system.l2c.overall_hits::5 11369 # number of overall hits -system.l2c.overall_hits::6 11109 # number of overall hits -system.l2c.overall_hits::7 11165 # number of overall hits -system.l2c.overall_hits::total 89906 # number of overall hits -system.l2c.overall_miss_latency 6130248439 # number of overall miss cycles -system.l2c.overall_miss_rate::0 0.575251 # miss rate for overall accesses -system.l2c.overall_miss_rate::1 0.580211 # miss rate for overall accesses -system.l2c.overall_miss_rate::2 0.581558 # miss rate for overall accesses -system.l2c.overall_miss_rate::3 0.576922 # miss rate for overall accesses -system.l2c.overall_miss_rate::4 0.574809 # miss rate for overall accesses -system.l2c.overall_miss_rate::5 0.573092 # miss rate for overall accesses -system.l2c.overall_miss_rate::6 0.582148 # miss rate for overall accesses -system.l2c.overall_miss_rate::7 0.580310 # miss rate for overall accesses -system.l2c.overall_miss_rate::total 4.624302 # miss rate for overall accesses -system.l2c.overall_misses::0 15373 # number of overall misses -system.l2c.overall_misses::1 15440 # number of overall misses -system.l2c.overall_misses::2 15427 # number of overall misses -system.l2c.overall_misses::3 15439 # number of overall misses -system.l2c.overall_misses::4 15302 # number of overall misses -system.l2c.overall_misses::5 15262 # number of overall misses -system.l2c.overall_misses::6 15477 # number of overall misses -system.l2c.overall_misses::7 15438 # number of overall misses -system.l2c.overall_misses::total 123158 # number of overall misses -system.l2c.overall_mshr_hits 1603 # number of overall MSHR hits -system.l2c.overall_mshr_miss_latency 4861710872 # number of overall MSHR miss cycles -system.l2c.overall_mshr_miss_rate::0 4.548533 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::1 4.567848 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::2 4.582312 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::3 4.542244 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::4 4.566132 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::5 4.564417 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::6 4.572143 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::7 4.569222 # mshr miss rate for overall accesses -system.l2c.overall_mshr_miss_rate::total 36.512852 # mshr miss rate for overall accesses -system.l2c.overall_mshr_misses 121555 # number of overall MSHR misses -system.l2c.overall_mshr_uncacheable_latency 4880792865 # number of overall MSHR uncacheable cycles +system.l2c.overall_hits::0 11293 # number of overall hits +system.l2c.overall_hits::1 11282 # number of overall hits +system.l2c.overall_hits::2 11320 # number of overall hits +system.l2c.overall_hits::3 11445 # number of overall hits +system.l2c.overall_hits::4 11209 # number of overall hits +system.l2c.overall_hits::5 11253 # number of overall hits +system.l2c.overall_hits::6 11313 # number of overall hits +system.l2c.overall_hits::7 11391 # number of overall hits +system.l2c.overall_hits::total 90506 # number of overall hits +system.l2c.overall_miss_latency 6103830891 # number of overall miss cycles +system.l2c.overall_miss_rate::0 0.575451 # miss rate for overall accesses +system.l2c.overall_miss_rate::1 0.576151 # miss rate for overall accesses +system.l2c.overall_miss_rate::2 0.573361 # miss rate for overall accesses +system.l2c.overall_miss_rate::3 0.573616 # miss rate for overall accesses +system.l2c.overall_miss_rate::4 0.578720 # miss rate for overall accesses +system.l2c.overall_miss_rate::5 0.577431 # miss rate for overall accesses +system.l2c.overall_miss_rate::6 0.573368 # miss rate for overall accesses +system.l2c.overall_miss_rate::7 0.574120 # miss rate for overall accesses +system.l2c.overall_miss_rate::total 4.602220 # miss rate for overall accesses +system.l2c.overall_misses::0 15307 # number of overall misses +system.l2c.overall_misses::1 15336 # number of overall misses +system.l2c.overall_misses::2 15213 # number of overall misses +system.l2c.overall_misses::3 15397 # number of overall misses +system.l2c.overall_misses::4 15398 # number of overall misses +system.l2c.overall_misses::5 15377 # number of overall misses +system.l2c.overall_misses::6 15204 # number of overall misses +system.l2c.overall_misses::7 15356 # number of overall misses +system.l2c.overall_misses::total 122588 # number of overall misses +system.l2c.overall_mshr_hits 1626 # number of overall MSHR hits +system.l2c.overall_mshr_miss_latency 4838535294 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_rate::0 4.547444 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::1 4.544368 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::2 4.558927 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::3 4.506445 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::4 4.546247 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::5 4.542321 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::6 4.561677 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::7 4.522451 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::total 36.329880 # mshr miss rate for overall accesses +system.l2c.overall_mshr_misses 120962 # number of overall MSHR misses +system.l2c.overall_mshr_uncacheable_latency 4905275071 # number of overall MSHR uncacheable cycles system.l2c.overall_mshr_uncacheable_misses 0 # number of overall MSHR uncacheable misses -system.l2c.replacements 73303 # number of replacements -system.l2c.sampled_refs 73894 # Sample count of references to valid blocks. +system.l2c.replacements 72848 # number of replacements +system.l2c.sampled_refs 73502 # Sample count of references to valid blocks. system.l2c.soft_prefetch_mshr_full 0 # number of mshr full events for SW prefetching instrutions -system.l2c.tagsinuse 633.737828 # Cycle average of tags in use -system.l2c.total_refs 148204 # Total number of references to valid blocks. +system.l2c.tagsinuse 633.459270 # Cycle average of tags in use +system.l2c.total_refs 148904 # Total number of references to valid blocks. system.l2c.warmup_cycle 0 # Cycle when the warmup percentage was hit. -system.l2c.writebacks 47216 # number of writebacks +system.l2c.writebacks 46916 # number of writebacks ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,118 @@ [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +to_mem_ctrl_latency=1 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +to_l2_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +l2_request_latency=2 +l2_response_latency=2 +number_of_TBEs=256 +recycle_latency=10 +to_l1_latency=1 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +125,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,141 +166,34 @@ children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -to_l2_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -l2_request_latency=2 -l2_response_latency=2 -number_of_TBEs=256 -recycle_latency=10 -to_l1_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -to_mem_ctrl_latency=1 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:37:01 +Real time: Aug/05/2010 10:33:27 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_hours: 0.000277778 Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 1.11 -Virtual_time_in_minutes: 0.0185 -Virtual_time_in_hours: 0.000308333 -Virtual_time_in_days: 1.28472e-05 +Virtual_time_in_seconds: 0.71 +Virtual_time_in_minutes: 0.0118333 +Virtual_time_in_hours: 0.000197222 +Virtual_time_in_days: 8.21759e-06 -Ruby_current_time: 385311 +Ruby_current_time: 344871 Ruby_start_time: 0 -Ruby_cycles: 385311 +Ruby_cycles: 344871 -mbytes_resident: 30.6758 -mbytes_total: 203.664 -resident_ratio: 0.150658 +mbytes_resident: 31.5195 +mbytes_total: 31.5273 +resident_ratio: 1 -ruby_cycles_executed: [ 385312 ] +ruby_cycles_executed: [ 344872 ] Busy Controller Counts: L1Cache-0:0 @@ -66,13 +66,28 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1035 average: 15.8406 | standard deviation: 1.10345 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 975 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 989 average: 15.8241 | standard deviation: 1.13108 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 55 920 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 256 max: 34673 count: 1020 average: 5812.61 | standard deviation: 8321.57 | 94 13 65 91 82 85 75 46 28 39 28 23 31 15 11 13 6 8 12 9 6 3 9 2 3 6 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 3 1 0 0 0 0 0 0 2 2 0 3 1 3 1 3 2 1 6 1 2 2 5 2 7 2 1 3 4 4 3 2 6 5 9 2 2 10 1 6 4 3 4 4 5 3 5 2 5 5 2 3 6 3 3 1 3 3 4 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 256 max: 28025 count: 100 average: 5269.19 | standard deviation: 7878.72 | 12 1 6 6 7 10 10 8 2 4 3 0 3 2 1 2 0 1 1 0 0 0 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 1 2 1 0 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 256 max: 34673 count: 920 average: 5871.67 | standard deviation: 8370.25 | 82 12 59 85 75 75 65 38 26 35 25 23 28 13 10 11 6 7 11 9 6 3 8 2 2 5 0 1 4 2 2 2 1 1 2 0 1 2 0 2 1 2 1 1 1 1 1 1 0 1 0 2 1 0 0 0 0 0 0 2 2 0 2 0 3 0 3 2 1 6 1 2 1 5 2 6 2 1 3 4 3 3 1 4 4 9 2 2 10 1 5 3 3 4 4 4 3 5 2 4 5 2 3 5 3 3 1 2 3 3 0 2 0 0 1 2 1 0 0 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 32169 count: 974 average: 5285.58 | standard deviation: 7638.9 | 100 23 77 92 81 69 51 49 39 28 29 13 21 12 12 14 4 11 7 9 6 2 8 6 5 6 2 2 3 3 0 1 1 0 2 0 1 1 1 1 2 3 1 1 0 2 1 0 2 1 1 1 1 3 3 3 4 3 2 2 2 2 5 2 4 2 4 2 2 4 3 2 1 5 2 5 4 3 2 5 3 4 2 2 3 3 0 2 2 2 4 4 3 6 5 1 1 3 3 3 4 3 1 1 3 2 2 0 2 4 0 1 0 0 0 0 0 0 1 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 16 max: 2681 count: 53 average: 955.906 | standard deviation: 434.89 | 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 3 0 2 1 1 1 4 0 0 0 0 2 0 0 0 0 0 0 2 1 2 1 0 0 0 2 0 1 2 0 0 1 2 1 0 2 0 1 1 1 2 1 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 256 max: 27271 count: 47 average: 5079.15 | standard deviation: 7361.33 | 8 1 2 2 6 2 3 3 3 0 0 2 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 256 max: 32169 count: 874 average: 5559.23 | standard deviation: 7807.37 | 91 19 60 79 61 61 46 46 36 28 28 11 20 12 12 13 4 10 7 9 6 2 7 5 5 6 2 1 3 3 0 1 1 0 2 0 1 1 1 1 2 3 0 1 0 2 1 0 2 1 1 1 1 3 3 3 4 2 2 2 2 2 4 2 3 2 4 2 2 4 3 2 0 5 2 5 4 3 1 4 3 4 2 2 3 3 0 2 2 2 4 4 3 6 5 1 1 3 3 3 4 3 1 0 3 2 1 0 2 4 0 1 0 0 0 0 0 0 1 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 32169 count: 974 average: 5285.58 | standard deviation: 7638.9 | 100 23 77 92 81 69 51 49 39 28 29 13 21 12 12 14 4 11 7 9 6 2 8 6 5 6 2 2 3 3 0 1 1 0 2 0 1 1 1 1 2 3 1 1 0 2 1 0 2 1 1 1 1 3 3 3 4 3 2 2 2 2 5 2 4 2 4 2 2 4 3 2 1 5 2 5 4 3 2 5 3 4 2 2 3 3 0 2 2 2 4 4 3 6 5 1 1 3 3 3 4 3 1 1 3 2 2 0 2 4 0 1 0 0 0 0 0 0 1 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 16 max: 2681 count: 53 average: 955.906 | standard deviation: 434.89 | 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 1 3 0 2 1 1 1 4 0 0 0 0 2 0 0 0 0 0 0 2 1 2 1 0 0 0 2 0 1 2 0 0 1 2 1 0 2 0 1 1 1 2 1 0 0 1 0 1 1 0 1 0 0 1 0 0 0 0 0 0 2 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_NULL: [binsize: 256 max: 27271 count: 47 average: 5079.15 | standard deviation: 7361.33 | 8 1 2 2 6 2 3 3 3 0 0 2 1 0 0 1 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 256 max: 32169 count: 874 average: 5559.23 | standard deviation: 7807.37 | 91 19 60 79 61 61 46 46 36 28 28 11 20 12 12 13 4 10 7 9 6 2 7 5 5 6 2 1 3 3 0 1 1 0 2 0 1 1 1 1 2 3 0 1 0 2 1 0 2 1 1 1 1 3 3 3 4 2 2 2 2 2 4 2 3 2 4 2 2 4 3 2 0 5 2 5 4 3 1 4 3 4 2 2 3 3 0 2 2 2 4 4 3 6 5 1 1 3 3 3 4 3 1 0 3 2 1 0 2 4 0 1 0 0 0 0 0 0 1 1 3 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -86,12 +101,12 @@ Message Delayed Cycles ---------------------- -Total_delay_cycles: [binsize: 32 max: 1500 count: 6932 average: 17.1509 | standard deviation: 98.3547 | 6592 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ] -Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4219 average: 0 | standard deviation: 0 | 4219 ] - virtual_network_0_delay_cycles: [binsize: 32 max: 1500 count: 2713 average: 43.8223 | standard deviation: 153.471 | 2373 5 32 90 2 8 38 6 0 15 11 1 8 21 4 12 12 1 3 10 11 2 3 11 1 6 7 6 0 2 4 1 2 0 0 1 1 0 0 0 1 0 0 0 0 0 2 0 ] +Total_delay_cycles: [binsize: 32 max: 1490 count: 6493 average: 21.5062 | standard deviation: 106.543 | 6105 9 32 70 11 19 33 6 8 21 12 7 14 16 2 13 23 6 4 18 12 4 10 10 2 11 3 2 0 4 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 1 1 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 4044 average: 0 | standard deviation: 0 | 4044 ] + virtual_network_0_delay_cycles: [binsize: 32 max: 1490 count: 2449 average: 57.0192 | standard deviation: 167.563 | 2061 9 32 70 11 19 33 6 8 21 12 7 14 16 2 13 23 6 4 18 12 4 10 10 2 11 3 2 0 4 1 0 1 0 0 2 0 0 0 0 0 0 0 0 0 1 1 0 ] virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 566 average: 0 | standard deviation: 0 | 566 ] - virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3653 average: 0 | standard deviation: 0 | 3653 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 597 average: 0 | standard deviation: 0 | 597 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 3447 average: 0 | standard deviation: 0 | 3447 ] virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] @@ -102,10 +117,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 1 +user_time: 0 system_time: 0 -page_reclaims: 8843 -page_faults: 0 +page_reclaims: 6996 +page_faults: 1889 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,490 +128,494 @@ Network Stats ------------- +total_msg_count_Control: 5196 41568 +total_msg_count_Request_Control: 1791 14328 +total_msg_count_Response_Data: 7488 539136 +total_msg_count_Response_Control: 6238 49904 +total_msg_count_Writeback_Data: 3786 272592 +total_msg_count_Writeback_Control: 99 792 +total_msgs: 24598 total_bytes: 918320 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.105942 - links_utilized_percent_switch_0_link_0: 0.0300309 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.181853 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.111119 + links_utilized_percent_switch_0_link_0: 0.0316894 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.19055 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Control: 931 7448 [ 0 6 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Request_Control: 597 4776 [ 597 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 875 63000 [ 0 875 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 271 2168 [ 0 271 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 877 7016 [ 877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Control: 875 7000 [ 0 52 823 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 1262 90864 [ 717 545 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 33 264 [ 33 0 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.151597 - links_utilized_percent_switch_1_link_0: 0.0748065 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.228387 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.159469 + links_utilized_percent_switch_1_link_0: 0.0786019 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.240336 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 1743 125496 [ 0 1743 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Control: 441 3528 [ 0 441 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Control: 877 7016 [ 877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 855 61560 [ 0 855 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Control: 1723 13784 [ 0 901 822 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 1262 90864 [ 717 545 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 33 264 [ 33 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 855 6840 [ 855 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 597 4776 [ 597 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 1641 118152 [ 0 1641 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 356 2848 [ 0 356 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0722257 - links_utilized_percent_switch_2_link_0: 0.0270658 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.117386 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0761335 + links_utilized_percent_switch_2_link_0: 0.0283947 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.123872 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Control: 901 7208 [ 0 901 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Control: 855 6840 [ 855 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 766 55152 [ 0 766 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Control: 85 680 [ 0 85 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 855 61560 [ 0 855 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 849 6792 [ 0 849 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.175871 - links_utilized_percent_switch_3_link_0: 0.120124 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.299226 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.108263 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.184915 + links_utilized_percent_switch_3_link_0: 0.126758 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.314407 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.113579 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Request_Control: 566 4528 [ 566 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 926 66672 [ 0 926 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Control: 357 2856 [ 0 357 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Control: 927 7416 [ 927 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 905 65160 [ 0 905 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Control: 1831 14648 [ 0 906 925 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 1342 96624 [ 783 559 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 78 624 [ 78 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Control: 906 7248 [ 906 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 817 58824 [ 0 817 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Control: 84 672 [ 0 84 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Request_Control: 597 4776 [ 597 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 875 63000 [ 0 875 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 271 2168 [ 0 271 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 877 7016 [ 877 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 855 61560 [ 0 855 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Control: 1723 13784 [ 0 901 822 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 1262 90864 [ 717 545 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 33 264 [ 33 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Control: 855 6840 [ 855 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 766 55152 [ 0 766 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Control: 85 680 [ 0 85 0 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 1000 -Inv 566 -L1_Replacement 547844 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_GET_INSTR 0 -Data 0 -Data_Exclusive 88 -DataS_fromL1 0 -Data_all_Acks 838 -Ack 0 -Ack_all 0 -WB_Ack 357 +Load [48 ] 48 +Ifetch [218 ] 218 +Store [1036 ] 1036 +Inv [597 ] 597 +L1_Replacement [485174 ] 485174 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_GET_INSTR [0 ] 0 +Data [0 ] 0 +Data_Exclusive [39 ] 39 +DataS_fromL1 [0 ] 0 +Data_all_Acks [836 ] 836 +Ack [0 ] 0 +Ack_all [1 ] 1 +WB_Ack [270 ] 270 - Transitions - -NP Load 88 -NP Ifetch 0 <-- -NP Store 839 -NP Inv 0 <-- -NP L1_Replacement 0 <-- +NP Load [41 ] 41 +NP Ifetch [52 ] 52 +NP Store [783 ] 783 +NP Inv [1 ] 1 +NP L1_Replacement [0 ] 0 -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I Inv 0 <-- -I L1_Replacement 63 +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Inv [0 ] 0 +I L1_Replacement [115 ] 115 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S Inv 0 <-- -S L1_Replacement 0 <-- +S Load [0 ] 0 +S Ifetch [1 ] 1 +S Store [1 ] 1 +S Inv [31 ] 31 +S L1_Replacement [6 ] 6 -E Load 0 <-- -E Ifetch 0 <-- -E Store 1 -E Inv 6 -E L1_Replacement 80 -E Fwd_GETX 0 <-- -E Fwd_GETS 0 <-- -E Fwd_GET_INSTR 0 <-- +E Load [0 ] 0 +E Ifetch [0 ] 0 +E Store [0 ] 0 +E Inv [5 ] 5 +E L1_Replacement [33 ] 33 +E Fwd_GETX [0 ] 0 +E Fwd_GETS [0 ] 0 +E Fwd_GET_INSTR [0 ] 0 -M Load 12 -M Ifetch 0 <-- -M Store 81 -M Inv 57 -M L1_Replacement 781 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_GET_INSTR 0 <-- +M Load [7 ] 7 +M Ifetch [0 ] 0 +M Store [90 ] 90 +M Inv [66 ] 66 +M L1_Replacement [717 ] 717 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_GET_INSTR [0 ] 0 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS Inv 0 <-- -IS L1_Replacement 46341 -IS Data_Exclusive 88 -IS DataS_fromL1 0 <-- -IS Data_all_Acks 0 <-- +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Inv [15 ] 15 +IS L1_Replacement [30034 ] 30034 +IS Data_Exclusive [39 ] 39 +IS DataS_fromL1 [0 ] 0 +IS Data_all_Acks [38 ] 38 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM Inv 0 <-- -IM L1_Replacement 500579 -IM Data 0 <-- -IM Data_all_Acks 838 -IM Ack 0 <-- +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Inv [0 ] 0 +IM L1_Replacement [454269 ] 454269 +IM Data [0 ] 0 +IM Data_all_Acks [783 ] 783 +IM Ack [0 ] 0 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM Inv 0 <-- -SM L1_Replacement 0 <-- -SM Ack 0 <-- -SM Ack_all 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Inv [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Ack [0 ] 0 +SM Ack_all [1 ] 1 -IS_I Load 0 <-- -IS_I Ifetch 0 <-- -IS_I Store 0 <-- -IS_I Inv 0 <-- -IS_I L1_Replacement 0 <-- -IS_I Data_Exclusive 0 <-- -IS_I DataS_fromL1 0 <-- -IS_I Data_all_Acks 0 <-- +IS_I Load [0 ] 0 +IS_I Ifetch [0 ] 0 +IS_I Store [0 ] 0 +IS_I Inv [0 ] 0 +IS_I L1_Replacement [0 ] 0 +IS_I Data_Exclusive [0 ] 0 +IS_I DataS_fromL1 [0 ] 0 +IS_I Data_all_Acks [15 ] 15 -M_I Load 0 <-- -M_I Ifetch 0 <-- -M_I Store 79 -M_I Inv 503 -M_I L1_Replacement 0 <-- -M_I Fwd_GETX 0 <-- -M_I Fwd_GETS 0 <-- -M_I Fwd_GET_INSTR 0 <-- -M_I WB_Ack 357 +M_I Load [0 ] 0 +M_I Ifetch [165 ] 165 +M_I Store [162 ] 162 +M_I Inv [479 ] 479 +M_I L1_Replacement [0 ] 0 +M_I Fwd_GETX [0 ] 0 +M_I Fwd_GETS [0 ] 0 +M_I Fwd_GET_INSTR [0 ] 0 +M_I WB_Ack [270 ] 270 -E_I Load 0 <-- -E_I Ifetch 0 <-- -E_I Store 0 <-- -E_I L1_Replacement 0 <-- +E_I Load [0 ] 0 +E_I Ifetch [0 ] 0 +E_I Store [0 ] 0 +E_I L1_Replacement [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GET_INSTR 0 -L1_GETS 94 -L1_GETX 851 -L1_UPGRADE 0 -L1_PUTX 506 -L1_PUTX_old 504 -Fwd_L1_GETX 0 -Fwd_L1_GETS 0 -Fwd_L1_GET_INSTR 0 -L2_Replacement 292 -L2_Replacement_clean 12332 -Mem_Data 905 -Mem_Ack 900 -WB_Data 525 -WB_Data_clean 34 -Ack 0 -Ack_all 6 -Unblock 0 -Unblock_Cancel 0 -Exclusive_Unblock 925 -MEM_Inv 0 +L1_GET_INSTR [52 ] 52 +L1_GETS [41 ] 41 +L1_GETX [783 ] 783 +L1_UPGRADE [1 ] 1 +L1_PUTX [337 ] 337 +L1_PUTX_old [480 ] 480 +Fwd_L1_GETX [0 ] 0 +Fwd_L1_GETS [0 ] 0 +Fwd_L1_GET_INSTR [0 ] 0 +L2_Replacement [237 ] 237 +L2_Replacement_clean [14511 ] 14511 +Mem_Data [855 ] 855 +Mem_Ack [849 ] 849 +WB_Data [529 ] 529 +WB_Data_clean [16 ] 16 +Ack [0 ] 0 +Ack_all [52 ] 52 +Unblock [0 ] 0 +Unblock_Cancel [0 ] 0 +Exclusive_Unblock [822 ] 822 +MEM_Inv [0 ] 0 - Transitions - -NP L1_GET_INSTR 0 <-- -NP L1_GETS 86 -NP L1_GETX 820 -NP L1_PUTX 0 <-- -NP L1_PUTX_old 95 +NP L1_GET_INSTR [47 ] 47 +NP L1_GETS [40 ] 40 +NP L1_GETX [768 ] 768 +NP L1_PUTX [0 ] 0 +NP L1_PUTX_old [86 ] 86 -SS L1_GET_INSTR 0 <-- -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_UPGRADE 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTX_old 0 <-- -SS L2_Replacement 0 <-- -SS L2_Replacement_clean 0 <-- -SS MEM_Inv 0 <-- +SS L1_GET_INSTR [0 ] 0 +SS L1_GETS [1 ] 1 +SS L1_GETX [4 ] 4 +SS L1_UPGRADE [1 ] 1 +SS L1_PUTX [0 ] 0 +SS L1_PUTX_old [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L2_Replacement_clean [47 ] 47 +SS MEM_Inv [0 ] 0 -M L1_GET_INSTR 0 <-- -M L1_GETS 2 -M L1_GETX 19 -M L1_PUTX 0 <-- -M L1_PUTX_old 0 <-- -M L2_Replacement 292 -M L2_Replacement_clean 44 -M MEM_Inv 0 <-- +M L1_GET_INSTR [5 ] 5 +M L1_GETS [0 ] 0 +M L1_GETX [11 ] 11 +M L1_PUTX [0 ] 0 +M L1_PUTX_old [0 ] 0 +M L2_Replacement [237 ] 237 +M L2_Replacement_clean [17 ] 17 +M MEM_Inv [0 ] 0 -MT L1_GET_INSTR 0 <-- -MT L1_GETS 0 <-- -MT L1_GETX 0 <-- -MT L1_PUTX 357 -MT L1_PUTX_old 0 <-- -MT L2_Replacement 0 <-- -MT L2_Replacement_clean 566 -MT MEM_Inv 0 <-- +MT L1_GET_INSTR [0 ] 0 +MT L1_GETS [0 ] 0 +MT L1_GETX [0 ] 0 +MT L1_PUTX [270 ] 270 +MT L1_PUTX_old [0 ] 0 +MT L2_Replacement [0 ] 0 +MT L2_Replacement_clean [550 ] 550 +MT MEM_Inv [0 ] 0 -M_I L1_GET_INSTR 0 <-- -M_I L1_GETS 6 -M_I L1_GETX 12 -M_I L1_UPGRADE 0 <-- -M_I L1_PUTX 0 <-- -M_I L1_PUTX_old 108 -M_I Mem_Ack 900 -M_I MEM_Inv 0 <-- +M_I L1_GET_INSTR [0 ] 0 +M_I L1_GETS [0 ] 0 +M_I L1_GETX [0 ] 0 +M_I L1_UPGRADE [0 ] 0 +M_I L1_PUTX [0 ] 0 +M_I L1_PUTX_old [119 ] 119 +M_I Mem_Ack [849 ] 849 +M_I MEM_Inv [0 ] 0 -MT_I L1_GET_INSTR 0 <-- -MT_I L1_GETS 0 <-- -MT_I L1_GETX 0 <-- -MT_I L1_UPGRADE 0 <-- -MT_I L1_PUTX 0 <-- -MT_I L1_PUTX_old 0 <-- -MT_I WB_Data 0 <-- -MT_I WB_Data_clean 0 <-- -MT_I Ack_all 0 <-- -MT_I MEM_Inv 0 <-- +MT_I L1_GET_INSTR [0 ] 0 +MT_I L1_GETS [0 ] 0 +MT_I L1_GETX [0 ] 0 +MT_I L1_UPGRADE [0 ] 0 +MT_I L1_PUTX [0 ] 0 +MT_I L1_PUTX_old [0 ] 0 +MT_I WB_Data [0 ] 0 +MT_I WB_Data_clean [0 ] 0 +MT_I Ack_all [0 ] 0 +MT_I MEM_Inv [0 ] 0 -MCT_I L1_GET_INSTR 0 <-- -MCT_I L1_GETS 0 <-- -MCT_I L1_GETX 0 <-- -MCT_I L1_UPGRADE 0 <-- -MCT_I L1_PUTX 0 <-- -MCT_I L1_PUTX_old 124 -MCT_I WB_Data 525 -MCT_I WB_Data_clean 34 -MCT_I Ack_all 6 +MCT_I L1_GET_INSTR [0 ] 0 +MCT_I L1_GETS [0 ] 0 +MCT_I L1_GETX [0 ] 0 +MCT_I L1_UPGRADE [0 ] 0 +MCT_I L1_PUTX [0 ] 0 +MCT_I L1_PUTX_old [136 ] 136 +MCT_I WB_Data [529 ] 529 +MCT_I WB_Data_clean [16 ] 16 +MCT_I Ack_all [5 ] 5 -I_I L1_GET_INSTR 0 <-- -I_I L1_GETS 0 <-- -I_I L1_GETX 0 <-- -I_I L1_UPGRADE 0 <-- -I_I L1_PUTX 0 <-- -I_I L1_PUTX_old 0 <-- -I_I Ack 0 <-- -I_I Ack_all 0 <-- +I_I L1_GET_INSTR [0 ] 0 +I_I L1_GETS [0 ] 0 +I_I L1_GETX [0 ] 0 +I_I L1_UPGRADE [0 ] 0 +I_I L1_PUTX [0 ] 0 +I_I L1_PUTX_old [0 ] 0 +I_I Ack [0 ] 0 +I_I Ack_all [47 ] 47 -S_I L1_GET_INSTR 0 <-- -S_I L1_GETS 0 <-- -S_I L1_GETX 0 <-- -S_I L1_UPGRADE 0 <-- -S_I L1_PUTX 0 <-- -S_I L1_PUTX_old 0 <-- -S_I Ack 0 <-- -S_I Ack_all 0 <-- -S_I MEM_Inv 0 <-- +S_I L1_GET_INSTR [0 ] 0 +S_I L1_GETS [0 ] 0 +S_I L1_GETX [0 ] 0 +S_I L1_UPGRADE [0 ] 0 +S_I L1_PUTX [0 ] 0 +S_I L1_PUTX_old [0 ] 0 +S_I Ack [0 ] 0 +S_I Ack_all [0 ] 0 +S_I MEM_Inv [0 ] 0 -ISS L1_GET_INSTR 0 <-- -ISS L1_GETS 0 <-- -ISS L1_GETX 0 <-- -ISS L1_PUTX 0 <-- -ISS L1_PUTX_old 0 <-- -ISS L2_Replacement 0 <-- -ISS L2_Replacement_clean 481 -ISS Mem_Data 86 -ISS MEM_Inv 0 <-- +ISS L1_GET_INSTR [0 ] 0 +ISS L1_GETS [0 ] 0 +ISS L1_GETX [0 ] 0 +ISS L1_PUTX [0 ] 0 +ISS L1_PUTX_old [0 ] 0 +ISS L2_Replacement [0 ] 0 +ISS L2_Replacement_clean [306 ] 306 +ISS Mem_Data [40 ] 40 +ISS MEM_Inv [0 ] 0 -IS L1_GET_INSTR 0 <-- -IS L1_GETS 0 <-- -IS L1_GETX 0 <-- -IS L1_PUTX 0 <-- -IS L1_PUTX_old 0 <-- -IS L2_Replacement 0 <-- -IS L2_Replacement_clean 0 <-- -IS Mem_Data 0 <-- -IS MEM_Inv 0 <-- +IS L1_GET_INSTR [0 ] 0 +IS L1_GETS [0 ] 0 +IS L1_GETX [0 ] 0 +IS L1_PUTX [0 ] 0 +IS L1_PUTX_old [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L2_Replacement_clean [1133 ] 1133 +IS Mem_Data [47 ] 47 +IS MEM_Inv [0 ] 0 -IM L1_GET_INSTR 0 <-- -IM L1_GETS 0 <-- -IM L1_GETX 0 <-- -IM L1_PUTX 0 <-- -IM L1_PUTX_old 0 <-- -IM L2_Replacement 0 <-- -IM L2_Replacement_clean 4544 -IM Mem_Data 819 -IM MEM_Inv 0 <-- +IM L1_GET_INSTR [0 ] 0 +IM L1_GETS [0 ] 0 +IM L1_GETX [0 ] 0 +IM L1_PUTX [0 ] 0 +IM L1_PUTX_old [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L2_Replacement_clean [4868 ] 4868 +IM Mem_Data [768 ] 768 +IM MEM_Inv [0 ] 0 -SS_MB L1_GET_INSTR 0 <-- -SS_MB L1_GETS 0 <-- -SS_MB L1_GETX 0 <-- -SS_MB L1_UPGRADE 0 <-- -SS_MB L1_PUTX 0 <-- -SS_MB L1_PUTX_old 0 <-- -SS_MB L2_Replacement 0 <-- -SS_MB L2_Replacement_clean 0 <-- -SS_MB Unblock_Cancel 0 <-- -SS_MB Exclusive_Unblock 0 <-- -SS_MB MEM_Inv 0 <-- +SS_MB L1_GET_INSTR [0 ] 0 +SS_MB L1_GETS [0 ] 0 +SS_MB L1_GETX [0 ] 0 +SS_MB L1_UPGRADE [0 ] 0 +SS_MB L1_PUTX [0 ] 0 +SS_MB L1_PUTX_old [0 ] 0 +SS_MB L2_Replacement [0 ] 0 +SS_MB L2_Replacement_clean [0 ] 0 +SS_MB Unblock_Cancel [0 ] 0 +SS_MB Exclusive_Unblock [5 ] 5 +SS_MB MEM_Inv [0 ] 0 -MT_MB L1_GET_INSTR 0 <-- -MT_MB L1_GETS 0 <-- -MT_MB L1_GETX 0 <-- -MT_MB L1_UPGRADE 0 <-- -MT_MB L1_PUTX 149 -MT_MB L1_PUTX_old 177 -MT_MB L2_Replacement 0 <-- -MT_MB L2_Replacement_clean 6697 -MT_MB Unblock_Cancel 0 <-- -MT_MB Exclusive_Unblock 925 -MT_MB MEM_Inv 0 <-- +MT_MB L1_GET_INSTR [0 ] 0 +MT_MB L1_GETS [0 ] 0 +MT_MB L1_GETX [0 ] 0 +MT_MB L1_UPGRADE [0 ] 0 +MT_MB L1_PUTX [67 ] 67 +MT_MB L1_PUTX_old [139 ] 139 +MT_MB L2_Replacement [0 ] 0 +MT_MB L2_Replacement_clean [7590 ] 7590 +MT_MB Unblock_Cancel [0 ] 0 +MT_MB Exclusive_Unblock [817 ] 817 +MT_MB MEM_Inv [0 ] 0 -M_MB L1_GET_INSTR 0 <-- -M_MB L1_GETS 0 <-- -M_MB L1_GETX 0 <-- -M_MB L1_UPGRADE 0 <-- -M_MB L1_PUTX 0 <-- -M_MB L1_PUTX_old 0 <-- -M_MB L2_Replacement 0 <-- -M_MB L2_Replacement_clean 0 <-- -M_MB Exclusive_Unblock 0 <-- -M_MB MEM_Inv 0 <-- +M_MB L1_GET_INSTR [0 ] 0 +M_MB L1_GETS [0 ] 0 +M_MB L1_GETX [0 ] 0 +M_MB L1_UPGRADE [0 ] 0 +M_MB L1_PUTX [0 ] 0 +M_MB L1_PUTX_old [0 ] 0 +M_MB L2_Replacement [0 ] 0 +M_MB L2_Replacement_clean [0 ] 0 +M_MB Exclusive_Unblock [0 ] 0 +M_MB MEM_Inv [0 ] 0 -MT_IIB L1_GET_INSTR 0 <-- -MT_IIB L1_GETS 0 <-- -MT_IIB L1_GETX 0 <-- -MT_IIB L1_UPGRADE 0 <-- -MT_IIB L1_PUTX 0 <-- -MT_IIB L1_PUTX_old 0 <-- -MT_IIB L2_Replacement 0 <-- -MT_IIB L2_Replacement_clean 0 <-- -MT_IIB WB_Data 0 <-- -MT_IIB WB_Data_clean 0 <-- -MT_IIB Unblock 0 <-- -MT_IIB MEM_Inv 0 <-- +MT_IIB L1_GET_INSTR [0 ] 0 +MT_IIB L1_GETS [0 ] 0 +MT_IIB L1_GETX [0 ] 0 +MT_IIB L1_UPGRADE [0 ] 0 +MT_IIB L1_PUTX [0 ] 0 +MT_IIB L1_PUTX_old [0 ] 0 +MT_IIB L2_Replacement [0 ] 0 +MT_IIB L2_Replacement_clean [0 ] 0 +MT_IIB WB_Data [0 ] 0 +MT_IIB WB_Data_clean [0 ] 0 +MT_IIB Unblock [0 ] 0 +MT_IIB MEM_Inv [0 ] 0 -MT_IB L1_GET_INSTR 0 <-- -MT_IB L1_GETS 0 <-- -MT_IB L1_GETX 0 <-- -MT_IB L1_UPGRADE 0 <-- -MT_IB L1_PUTX 0 <-- -MT_IB L1_PUTX_old 0 <-- -MT_IB L2_Replacement 0 <-- -MT_IB L2_Replacement_clean 0 <-- -MT_IB WB_Data 0 <-- -MT_IB WB_Data_clean 0 <-- -MT_IB Unblock_Cancel 0 <-- -MT_IB MEM_Inv 0 <-- +MT_IB L1_GET_INSTR [0 ] 0 +MT_IB L1_GETS [0 ] 0 +MT_IB L1_GETX [0 ] 0 +MT_IB L1_UPGRADE [0 ] 0 +MT_IB L1_PUTX [0 ] 0 +MT_IB L1_PUTX_old [0 ] 0 +MT_IB L2_Replacement [0 ] 0 +MT_IB L2_Replacement_clean [0 ] 0 +MT_IB WB_Data [0 ] 0 +MT_IB WB_Data_clean [0 ] 0 +MT_IB Unblock_Cancel [0 ] 0 +MT_IB MEM_Inv [0 ] 0 -MT_SB L1_GET_INSTR 0 <-- -MT_SB L1_GETS 0 <-- -MT_SB L1_GETX 0 <-- -MT_SB L1_UPGRADE 0 <-- -MT_SB L1_PUTX 0 <-- -MT_SB L1_PUTX_old 0 <-- -MT_SB L2_Replacement 0 <-- -MT_SB L2_Replacement_clean 0 <-- -MT_SB Unblock 0 <-- -MT_SB MEM_Inv 0 <-- +MT_SB L1_GET_INSTR [0 ] 0 +MT_SB L1_GETS [0 ] 0 +MT_SB L1_GETX [0 ] 0 +MT_SB L1_UPGRADE [0 ] 0 +MT_SB L1_PUTX [0 ] 0 +MT_SB L1_PUTX_old [0 ] 0 +MT_SB L2_Replacement [0 ] 0 +MT_SB L2_Replacement_clean [0 ] 0 +MT_SB Unblock [0 ] 0 +MT_SB MEM_Inv [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1723 - memory_reads: 906 - memory_writes: 817 - memory_refreshes: 803 - memory_total_request_delays: 1221 - memory_delays_per_request: 0.708648 - memory_delays_in_input_queue: 188 - memory_delays_behind_head_of_bank_queue: 7 - memory_delays_stalled_at_head_of_bank_queue: 1026 - memory_stalls_for_bank_busy: 216 +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1621 + memory_reads: 855 + memory_writes: 766 + memory_refreshes: 719 + memory_total_request_delays: 1102 + memory_delays_per_request: 0.679827 + memory_delays_in_input_queue: 175 + memory_delays_behind_head_of_bank_queue: 2 + memory_delays_stalled_at_head_of_bank_queue: 925 + memory_stalls_for_bank_busy: 219 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 86 - memory_stalls_for_bus: 387 + memory_stalls_for_arbitration: 65 + memory_stalls_for_bus: 338 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 251 - memory_stalls_for_read_read_turnaround: 86 - accesses_per_bank: 63 53 48 94 79 59 62 65 55 57 52 50 48 47 45 40 39 56 50 45 64 47 43 53 58 51 52 54 52 47 50 45 + memory_stalls_for_read_write_turnaround: 216 + memory_stalls_for_read_read_turnaround: 87 + accesses_per_bank: 38 49 43 83 66 53 65 56 53 60 40 49 47 57 44 37 50 59 39 51 41 53 51 59 53 45 45 47 64 42 40 42 - --- Directory 0 --- + --- Directory --- - Event Counts - -Fetch 906 -Data 817 -Memory_Data 906 -Memory_Ack 817 -DMA_READ 0 -DMA_WRITE 0 -CleanReplacement 84 +Fetch [855 ] 855 +Data [766 ] 766 +Memory_Data [855 ] 855 +Memory_Ack [764 ] 764 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +CleanReplacement [85 ] 85 - Transitions - -I Fetch 906 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I Fetch [855 ] 855 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -ID Fetch 0 <-- -ID Data 0 <-- -ID Memory_Data 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- +ID Fetch [0 ] 0 +ID Data [0 ] 0 +ID Memory_Data [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 -ID_W Fetch 0 <-- -ID_W Data 0 <-- -ID_W Memory_Ack 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- +ID_W Fetch [0 ] 0 +ID_W Data [0 ] 0 +ID_W Memory_Ack [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 -M Data 817 -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- -M CleanReplacement 84 +M Data [766 ] 766 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 +M CleanReplacement [85 ] 85 -IM Fetch 0 <-- -IM Data 0 <-- -IM Memory_Data 906 -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- +IM Fetch [0 ] 0 +IM Data [0 ] 0 +IM Memory_Data [855 ] 855 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 -MI Fetch 0 <-- -MI Data 0 <-- -MI Memory_Ack 817 -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI Fetch [0 ] 0 +MI Data [0 ] 0 +MI Memory_Ack [764 ] 764 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -M_DRD Data 0 <-- -M_DRD DMA_READ 0 <-- -M_DRD DMA_WRITE 0 <-- +M_DRD Data [0 ] 0 +M_DRD DMA_READ [0 ] 0 +M_DRD DMA_WRITE [0 ] 0 -M_DRDI Fetch 0 <-- -M_DRDI Data 0 <-- -M_DRDI Memory_Ack 0 <-- -M_DRDI DMA_READ 0 <-- -M_DRDI DMA_WRITE 0 <-- +M_DRDI Fetch [0 ] 0 +M_DRDI Data [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 +M_DRDI DMA_READ [0 ] 0 +M_DRDI DMA_WRITE [0 ] 0 -M_DWR Data 0 <-- -M_DWR DMA_READ 0 <-- -M_DWR DMA_WRITE 0 <-- +M_DWR Data [0 ] 0 +M_DWR DMA_READ [0 ] 0 +M_DWR DMA_WRITE [0 ] 0 -M_DWRI Fetch 0 <-- -M_DWRI Data 0 <-- -M_DWRI Memory_Ack 0 <-- -M_DWRI DMA_READ 0 <-- -M_DWRI DMA_WRITE 0 <-- - +M_DWRI Fetch [0 ] 0 +M_DWRI Data [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 +M_DWRI DMA_READ [0 ] 0 +M_DWRI DMA_WRITE \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:36:48 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:37:00 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:22:52 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:33:26 +M5 executing on svvint09 command line: build/ALPHA_SE_MESI_CMP_directory/m5.fast -d build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory -re tests/run.py build/ALPHA_SE_MESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 385311 because Ruby Tester completed +Exiting @ tick 344871 because Ruby Tester completed diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208556 # Number of bytes of host memory used -host_seconds 0.90 # Real time elapsed on the host -host_tick_rate 429636 # Simulator tick rate (ticks/s) +host_mem_usage 209976 # Number of bytes of host memory used +host_seconds 0.54 # Real time elapsed on the host +host_tick_rate 638623 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000385 # Number of seconds simulated -sim_ticks 385311 # Number of ticks simulated +sim_seconds 0.000345 # Number of seconds simulated +sim_ticks 344871 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,114 @@ [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=6 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +buffer_size=0 +l2_select_num_bits=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +buffer_size=0 +number_of_TBEs=256 +recycle_latency=10 +request_latency=2 +response_latency=2 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=15 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +121,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,137 +162,34 @@ children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -buffer_size=0 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -buffer_size=0 -number_of_TBEs=256 -recycle_latency=10 -request_latency=2 -response_latency=2 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, unordered virtual_net_1: active, unordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:40:26 +Real time: Aug/05/2010 10:40:25 Profiler Stats -------------- -Elapsed_time_in_seconds: 7 -Elapsed_time_in_minutes: 0.116667 -Elapsed_time_in_hours: 0.00194444 -Elapsed_time_in_days: 8.10185e-05 +Elapsed_time_in_seconds: 1 +Elapsed_time_in_minutes: 0.0166667 +Elapsed_time_in_hours: 0.000277778 +Elapsed_time_in_days: 1.15741e-05 -Virtual_time_in_seconds: 1.19 -Virtual_time_in_minutes: 0.0198333 -Virtual_time_in_hours: 0.000330556 -Virtual_time_in_days: 1.37731e-05 +Virtual_time_in_seconds: 1.03 +Virtual_time_in_minutes: 0.0171667 +Virtual_time_in_hours: 0.000286111 +Virtual_time_in_days: 1.19213e-05 -Ruby_current_time: 382981 +Ruby_current_time: 372291 Ruby_start_time: 0 -Ruby_cycles: 382981 +Ruby_cycles: 372291 -mbytes_resident: 30.7617 -mbytes_total: 203.789 -resident_ratio: 0.150987 +mbytes_resident: 31.6016 +mbytes_total: 31.6094 +resident_ratio: 1 -ruby_cycles_executed: [ 382982 ] +ruby_cycles_executed: [ 372292 ] Busy Controller Counts: L2Cache-0:0 @@ -66,13 +66,28 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 999 average: 15.8288 | standard deviation: 1.12451 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 52 933 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1034 average: 15.8404 | standard deviation: 1.10398 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 46 974 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 256 max: 35174 count: 984 average: 6099.68 | standard deviation: 8576.16 | 88 23 79 106 74 53 72 37 25 27 17 28 22 12 10 11 8 12 6 5 2 6 2 1 3 5 6 2 2 2 2 0 2 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 4 3 3 1 1 5 2 0 3 1 1 2 0 3 6 1 5 8 0 4 7 3 1 2 4 2 3 2 2 5 3 3 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 1 2 4 1 1 3 0 0 2 2 0 4 1 1 1 2 0 2 3 2 0 2 0 0 3 3 3 2 0 2 1 1 0 0 0 1 0 1 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 256 max: 34854 count: 100 average: 7109.16 | standard deviation: 10187.8 | 11 1 8 10 5 6 6 3 4 6 0 4 5 1 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 1 1 0 1 1 0 0 0 1 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 0 0 0 1 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_3: [binsize: 256 max: 35174 count: 884 average: 5985.48 | standard deviation: 8373.45 | 77 22 71 96 69 47 66 34 21 21 17 24 17 11 10 10 7 12 6 4 2 6 2 1 2 4 6 2 2 2 2 0 1 5 1 2 1 2 1 0 1 4 2 2 4 5 5 5 2 4 1 3 3 3 1 1 5 2 0 3 1 1 1 0 3 5 1 4 7 0 3 6 3 1 2 3 2 3 2 2 3 2 2 1 2 5 1 3 3 2 4 4 6 2 2 3 3 2 1 0 2 2 1 1 3 0 0 1 1 0 4 1 0 1 2 0 2 3 1 0 2 0 0 2 3 3 2 0 1 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_NULL: [binsize: 256 max: 31997 count: 1019 average: 5668.53 | standard deviation: 8073.92 | 94 34 102 118 76 61 60 39 35 29 18 16 23 15 9 14 7 5 5 5 5 5 2 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 2 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 8 2 7 1 3 9 10 7 6 6 7 4 5 7 6 8 5 3 2 5 7 3 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 2 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 0 +miss_latency_IFETCH_NULL: [binsize: 8 max: 1286 count: 55 average: 671.836 | standard deviation: 242.921 | 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 1 1 0 0 0 0 1 0 0 0 0 1 1 2 2 0 0 1 0 0 1 0 0 1 0 2 3 1 4 1 0 0 1 0 0 0 0 1 0 1 2 2 1 0 0 1 0 0 1 0 0 1 0 1 1 1 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_NULL: [binsize: 256 max: 28569 count: 45 average: 4874.44 | standard deviation: 7882.18 | 6 2 5 9 2 2 3 2 0 0 1 1 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_NULL: [binsize: 256 max: 31997 count: 919 average: 6006.46 | standard deviation: 8225.99 | 86 24 69 94 73 58 57 37 35 29 17 15 23 15 9 13 7 5 5 4 4 5 1 1 1 3 6 1 3 1 0 1 0 2 0 0 1 0 1 1 2 3 0 2 3 1 4 3 0 1 1 1 4 4 1 2 0 2 3 1 1 0 1 0 1 1 2 4 6 5 2 1 3 7 2 7 1 2 8 10 6 6 6 7 4 5 7 5 8 5 3 2 5 7 2 1 2 3 2 2 0 2 3 2 2 0 0 1 0 0 3 1 0 0 1 0 2 1 2 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -102,10 +117,10 @@ Resource Usage -------------- page_size: 4096 -user_time: 1 +user_time: 0 system_time: 0 -page_reclaims: 8880 -page_faults: 0 +page_reclaims: 7050 +page_faults: 1907 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,1248 +128,1252 @@ Network Stats ------------- +total_msg_count_Request_Control: 5430 43440 +total_msg_count_Response_Data: 5289 380808 +total_msg_count_ResponseL2hit_Data: 138 9936 +total_msg_count_Writeback_Data: 5151 370872 +total_msg_count_Writeback_Control: 11015 88120 +total_msg_count_Unblock_Control: 5419 43352 +total_msgs: 32442 total_bytes: 936528 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.084797 - links_utilized_percent_switch_0_link_0: 0.0292998 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.140294 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.0899934 + links_utilized_percent_switch_0_link_0: 0.0311114 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.148875 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 927 7416 [ 0 0 927 0 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.152981 - links_utilized_percent_switch_1_link_0: 0.0632212 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.242741 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.161841 + links_utilized_percent_switch_1_link_0: 0.0667992 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.256882 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 1837 14696 [ 895 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Unblock_Control: 863 6904 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 1796 14368 [ 923 873 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 926 7408 [ 0 0 926 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 1876 15008 [ 923 874 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0719863 - links_utilized_percent_switch_2_link_0: 0.0313821 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.11259 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.0757203 + links_utilized_percent_switch_2_link_0: 0.0331058 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.118335 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 857 6856 [ 0 857 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 952 7616 [ 0 873 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 873 6984 [ 0 873 0 0 0 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.165204 - links_utilized_percent_switch_3_link_0: 0.117199 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.252885 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.125528 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.174693 + links_utilized_percent_switch_3_link_0: 0.124446 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.267197 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.132437 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 35 2520 [ 0 0 35 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Control: 895 7160 [ 895 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 898 7184 [ 898 0 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Response_Data: 863 62136 [ 0 0 863 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 895 64440 [ 0 0 895 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Control: 1752 14016 [ 895 857 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Unblock_Control: 898 7184 [ 0 0 898 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 863 6904 [ 0 863 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 772 55584 [ 0 0 772 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Control: 942 7536 [ 0 857 85 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Unblock_Control: 862 6896 [ 0 0 862 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 881 63432 [ 0 0 881 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 46 3312 [ 0 0 46 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 923 7384 [ 923 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 928 7424 [ 928 0 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 882 63504 [ 0 0 882 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 923 66456 [ 0 0 923 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Control: 1796 14368 [ 923 873 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Unblock_Control: 926 7408 [ 0 0 926 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 882 7056 [ 0 882 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 794 57168 [ 0 0 794 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Control: 953 7624 [ 0 874 79 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Unblock_Control: 880 7040 [ 0 0 880 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 0 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 0 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 101 -Ifetch 0 -Store 887 -L1_Replacement 547308 -Own_GETX 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Inv 0 -Ack 0 -Data 0 -Exclusive_Data 898 -Writeback_Ack 0 -Writeback_Ack_Data 895 -Writeback_Nack 0 -All_acks 809 -Use_Timeout 897 +Load [45 ] 45 +Ifetch [149 ] 149 +Store [1075 ] 1075 +L1_Replacement [528774 ] 528774 +Own_GETX [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Inv [0 ] 0 +Ack [0 ] 0 +Data [0 ] 0 +Exclusive_Data [927 ] 927 +Writeback_Ack [0 ] 0 +Writeback_Ack_Data [923 ] 923 +Writeback_Nack [0 ] 0 +All_acks [835 ] 835 +Use_Timeout [926 ] 926 - Transitions - -I Load 90 -I Ifetch 0 <-- -I Store 809 -I L1_Replacement 0 <-- -I Inv 0 <-- +I Load [39 ] 39 +I Ifetch [53 ] 53 +I Store [836 ] 836 +I L1_Replacement [0 ] 0 +I Inv [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L1_Replacement 0 <-- -S Fwd_GETS 0 <-- -S Fwd_DMA 0 <-- -S Inv 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L1_Replacement [0 ] 0 +S Fwd_GETS [0 ] 0 +S Fwd_DMA [0 ] 0 +S Inv [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L1_Replacement [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M L1_Replacement 89 -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- +M Load [0 ] 0 +M Ifetch [2 ] 2 +M Store [0 ] 0 +M L1_Replacement [88 ] 88 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L1_Replacement 3013 -M_W Own_GETX 0 <-- -M_W Fwd_GETX 0 <-- -M_W Fwd_GETS 0 <-- -M_W Fwd_DMA 0 <-- -M_W Inv 0 <-- -M_W Use_Timeout 89 +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [1 ] 1 +M_W L1_Replacement [1040 ] 1040 +M_W Own_GETX [0 ] 0 +M_W Fwd_GETX [0 ] 0 +M_W Fwd_GETS [0 ] 0 +M_W Fwd_DMA [0 ] 0 +M_W Inv [0 ] 0 +M_W Use_Timeout [90 ] 90 -MM Load 10 -MM Ifetch 0 <-- -MM Store 66 -MM L1_Replacement 807 -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- +MM Load [5 ] 5 +MM Ifetch [0 ] 0 +MM Store [72 ] 72 +MM L1_Replacement [835 ] 835 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 -MM_W Load 1 -MM_W Ifetch 0 <-- -MM_W Store 9 -MM_W L1_Replacement 30209 -MM_W Own_GETX 0 <-- -MM_W Fwd_GETX 0 <-- -MM_W Fwd_GETS 0 <-- -MM_W Fwd_DMA 0 <-- -MM_W Inv 0 <-- -MM_W Use_Timeout 808 +MM_W Load [1 ] 1 +MM_W Ifetch [0 ] 0 +MM_W Store [11 ] 11 +MM_W L1_Replacement [30786 ] 30786 +MM_W Own_GETX [0 ] 0 +MM_W Fwd_GETX [0 ] 0 +MM_W Fwd_GETS [0 ] 0 +MM_W Fwd_DMA [0 ] 0 +MM_W Inv [0 ] 0 +MM_W Use_Timeout [836 ] 836 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 444777 -IM Inv 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 809 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L1_Replacement [464217 ] 464217 +IM Inv [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [835 ] 835 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Fwd_GETS 0 <-- -SM Fwd_DMA 0 <-- -SM Inv 0 <-- -SM Ack 0 <-- -SM Data 0 <-- -SM Exclusive_Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Fwd_GETS [0 ] 0 +SM Fwd_DMA [0 ] 0 +SM Inv [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 +SM Exclusive_Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 17359 -OM Own_GETX 0 <-- -OM Fwd_GETX 0 <-- -OM Fwd_GETS 0 <-- -OM Fwd_DMA 0 <-- -OM Ack 0 <-- -OM All_acks 809 +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L1_Replacement [13588 ] 13588 +OM Own_GETX [0 ] 0 +OM Fwd_GETX [0 ] 0 +OM Fwd_GETS [0 ] 0 +OM Fwd_DMA [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [835 ] 835 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 51054 -IS Inv 0 <-- -IS Data 0 <-- -IS Exclusive_Data 89 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L1_Replacement [18220 ] 18220 +IS Inv [0 ] 0 +IS Data [0 ] 0 +IS Exclusive_Data [92 ] 92 -SI Load 0 <-- -SI Ifetch 0 <-- -SI Store 0 <-- -SI L1_Replacement 0 <-- -SI Fwd_GETS 0 <-- -SI Fwd_DMA 0 <-- -SI Inv 0 <-- -SI Writeback_Ack 0 <-- -SI Writeback_Ack_Data 0 <-- -SI Writeback_Nack 0 <-- +SI Load [0 ] 0 +SI Ifetch [0 ] 0 +SI Store [0 ] 0 +SI L1_Replacement [0 ] 0 +SI Fwd_GETS [0 ] 0 +SI Fwd_DMA [0 ] 0 +SI Inv [0 ] 0 +SI Writeback_Ack [0 ] 0 +SI Writeback_Ack_Data [0 ] 0 +SI Writeback_Nack [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L1_Replacement 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Ack_Data 0 <-- -OI Writeback_Nack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L1_Replacement [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Ack_Data [0 ] 0 +OI Writeback_Nack [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 3 -MI L1_Replacement 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 0 <-- -MI Writeback_Ack_Data 895 -MI Writeback_Nack 0 <-- +MI Load [0 ] 0 +MI Ifetch [94 ] 94 +MI Store [155 ] 155 +MI L1_Replacement [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [0 ] 0 +MI Writeback_Ack_Data [923 ] 923 +MI Writeback_Nack [0 ] 0 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L1_Replacement 0 <-- -II Inv 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Ack_Data 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L1_Replacement [0 ] 0 +II Inv [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Ack_Data [0 ] 0 +II Writeback_Nack [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 0 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] - --- L2Cache 0 --- + --- L2Cache --- - Event Counts - -L1_GETS 132 -L1_GETX 846 -L1_PUTO 0 -L1_PUTX 2074 -L1_PUTS_only 0 -L1_PUTS 0 -Fwd_GETX 0 -Fwd_GETS 0 -Fwd_DMA 0 -Own_GETX 0 -Inv 0 -IntAck 0 -ExtAck 0 -All_Acks 777 -Data 777 -Data_Exclusive 86 -L1_WBCLEANDATA 85 -L1_WBDIRTYDATA 810 -Writeback_Ack 857 -Writeback_Nack 0 -Unblock 0 -Exclusive_Unblock 898 -L2_Replacement 857 +L1_GETS [141 ] 141 +L1_GETX [855 ] 855 +L1_PUTO [0 ] 0 +L1_PUTX [2239 ] 2239 +L1_PUTS_only [0 ] 0 +L1_PUTS [0 ] 0 +Fwd_GETX [0 ] 0 +Fwd_GETS [0 ] 0 +Fwd_DMA [0 ] 0 +Own_GETX [0 ] 0 +Inv [0 ] 0 +IntAck [0 ] 0 +ExtAck [0 ] 0 +All_Acks [795 ] 795 +Data [795 ] 795 +Data_Exclusive [86 ] 86 +L1_WBCLEANDATA [83 ] 83 +L1_WBDIRTYDATA [840 ] 840 +Writeback_Ack [873 ] 873 +Writeback_Nack [0 ] 0 +Unblock [0 ] 0 +Exclusive_Unblock [926 ] 926 +L2_Replacement [874 ] 874 - Transitions - -NP L1_GETS 86 -NP L1_GETX 777 -NP L1_PUTO 0 <-- -NP L1_PUTX 0 <-- -NP L1_PUTS 0 <-- -NP Inv 0 <-- +NP L1_GETS [86 ] 86 +NP L1_GETX [796 ] 796 +NP L1_PUTO [0 ] 0 +NP L1_PUTX [0 ] 0 +NP L1_PUTS [0 ] 0 +NP Inv [0 ] 0 -I L1_GETS 0 <-- -I L1_GETX 0 <-- -I L1_PUTO 0 <-- -I L1_PUTX 0 <-- -I L1_PUTS 0 <-- -I Inv 0 <-- -I L2_Replacement 0 <-- +I L1_GETS [0 ] 0 +I L1_GETX [0 ] 0 +I L1_PUTO [0 ] 0 +I L1_PUTX [0 ] 0 +I L1_PUTS [0 ] 0 +I Inv [0 ] 0 +I L2_Replacement [0 ] 0 -ILS L1_GETS 0 <-- -ILS L1_GETX 0 <-- -ILS L1_PUTO 0 <-- -ILS L1_PUTX 0 <-- -ILS L1_PUTS_only 0 <-- -ILS L1_PUTS 0 <-- -ILS Inv 0 <-- -ILS L2_Replacement 0 <-- +ILS L1_GETS [0 ] 0 +ILS L1_GETX [0 ] 0 +ILS L1_PUTO [0 ] 0 +ILS L1_PUTX [0 ] 0 +ILS L1_PUTS_only [0 ] 0 +ILS L1_PUTS [0 ] 0 +ILS Inv [0 ] 0 +ILS L2_Replacement [0 ] 0 -ILX L1_GETS 0 <-- -ILX L1_GETX 0 <-- -ILX L1_PUTO 0 <-- -ILX L1_PUTX 895 -ILX L1_PUTS_only 0 <-- -ILX L1_PUTS 0 <-- -ILX Fwd_GETX 0 <-- -ILX Fwd_GETS 0 <-- -ILX Fwd_DMA 0 <-- -ILX Inv 0 <-- -ILX Data 0 <-- -ILX L2_Replacement 0 <-- +ILX L1_GETS [0 ] 0 +ILX L1_GETX [0 ] 0 +ILX L1_PUTO [0 ] 0 +ILX L1_PUTX [923 ] 923 +ILX L1_PUTS_only [0 ] 0 +ILX L1_PUTS [0 ] 0 +ILX Fwd_GETX [0 ] 0 +ILX Fwd_GETS [0 ] 0 +ILX Fwd_DMA [0 ] 0 +ILX Inv [0 ] 0 +ILX Data [0 ] 0 +ILX L2_Replacement [0 ] 0 -ILO L1_GETS 0 <-- -ILO L1_GETX 0 <-- -ILO L1_PUTO 0 <-- -ILO L1_PUTX 0 <-- -ILO L1_PUTS 0 <-- -ILO Fwd_GETX 0 <-- -ILO Fwd_GETS 0 <-- -ILO Fwd_DMA 0 <-- -ILO Inv 0 <-- -ILO Data 0 <-- -ILO L2_Replacement 0 <-- +ILO L1_GETS [0 ] 0 +ILO L1_GETX [0 ] 0 +ILO L1_PUTO [0 ] 0 +ILO L1_PUTX [0 ] 0 +ILO L1_PUTS [0 ] 0 +ILO Fwd_GETX [0 ] 0 +ILO Fwd_GETS [0 ] 0 +ILO Fwd_DMA [0 ] 0 +ILO Inv [0 ] 0 +ILO Data [0 ] 0 +ILO L2_Replacement [0 ] 0 -ILOX L1_GETS 0 <-- -ILOX L1_GETX 0 <-- -ILOX L1_PUTO 0 <-- -ILOX L1_PUTX 0 <-- -ILOX L1_PUTS 0 <-- -ILOX Fwd_GETX 0 <-- -ILOX Fwd_GETS 0 <-- -ILOX Fwd_DMA 0 <-- -ILOX Data 0 <-- +ILOX L1_GETS [0 ] 0 +ILOX L1_GETX [0 ] 0 +ILOX L1_PUTO [0 ] 0 +ILOX L1_PUTX [0 ] 0 +ILOX L1_PUTS [0 ] 0 +ILOX Fwd_GETX [0 ] 0 +ILOX Fwd_GETS [0 ] 0 +ILOX Fwd_DMA [0 ] 0 +ILOX Data [0 ] 0 -ILOS L1_GETS 0 <-- -ILOS L1_GETX 0 <-- -ILOS L1_PUTO 0 <-- -ILOS L1_PUTX 0 <-- -ILOS L1_PUTS_only 0 <-- -ILOS L1_PUTS 0 <-- -ILOS Fwd_GETX 0 <-- -ILOS Fwd_GETS 0 <-- -ILOS Fwd_DMA 0 <-- -ILOS Data 0 <-- -ILOS L2_Replacement 0 <-- +ILOS L1_GETS [0 ] 0 +ILOS L1_GETX [0 ] 0 +ILOS L1_PUTO [0 ] 0 +ILOS L1_PUTX [0 ] 0 +ILOS L1_PUTS_only [0 ] 0 +ILOS L1_PUTS [0 ] 0 +ILOS Fwd_GETX [0 ] 0 +ILOS Fwd_GETS [0 ] 0 +ILOS Fwd_DMA [0 ] 0 +ILOS Data [0 ] 0 +ILOS L2_Replacement [0 ] 0 -ILOSX L1_GETS 0 <-- -ILOSX L1_GETX 0 <-- -ILOSX L1_PUTO 0 <-- -ILOSX L1_PUTX 0 <-- -ILOSX L1_PUTS_only 0 <-- -ILOSX L1_PUTS 0 <-- -ILOSX Fwd_GETX 0 <-- -ILOSX Fwd_GETS 0 <-- -ILOSX Fwd_DMA 0 <-- -ILOSX Data 0 <-- +ILOSX L1_GETS [0 ] 0 +ILOSX L1_GETX [0 ] 0 +ILOSX L1_PUTO [0 ] 0 +ILOSX L1_PUTX [0 ] 0 +ILOSX L1_PUTS_only [0 ] 0 +ILOSX L1_PUTS [0 ] 0 +ILOSX Fwd_GETX [0 ] 0 +ILOSX Fwd_GETS [0 ] 0 +ILOSX Fwd_DMA [0 ] 0 +ILOSX Data [0 ] 0 -S L1_GETS 0 <-- -S L1_GETX 0 <-- -S L1_PUTX 0 <-- -S L1_PUTS 0 <-- -S Inv 0 <-- -S L2_Replacement 0 <-- +S L1_GETS [0 ] 0 +S L1_GETX [0 ] 0 +S L1_PUTX [0 ] 0 +S L1_PUTS [0 ] 0 +S Inv [0 ] 0 +S L2_Replacement [0 ] 0 -O L1_GETS 0 <-- -O L1_GETX 0 <-- -O L1_PUTX 0 <-- -O Fwd_GETX 0 <-- -O Fwd_GETS 0 <-- -O Fwd_DMA 0 <-- -O L2_Replacement 0 <-- +O L1_GETS [0 ] 0 +O L1_GETX [0 ] 0 +O L1_PUTX [0 ] 0 +O Fwd_GETX [0 ] 0 +O Fwd_GETS [0 ] 0 +O Fwd_DMA [0 ] 0 +O L2_Replacement [0 ] 0 -OLS L1_GETS 0 <-- -OLS L1_GETX 0 <-- -OLS L1_PUTX 0 <-- -OLS L1_PUTS_only 0 <-- -OLS L1_PUTS 0 <-- -OLS Fwd_GETX 0 <-- -OLS Fwd_GETS 0 <-- -OLS Fwd_DMA 0 <-- -OLS L2_Replacement 0 <-- +OLS L1_GETS [0 ] 0 +OLS L1_GETX [0 ] 0 +OLS L1_PUTX [0 ] 0 +OLS L1_PUTS_only [0 ] 0 +OLS L1_PUTS [0 ] 0 +OLS Fwd_GETX [0 ] 0 +OLS Fwd_GETS [0 ] 0 +OLS Fwd_DMA [0 ] 0 +OLS L2_Replacement [0 ] 0 -OLSX L1_GETS 0 <-- -OLSX L1_GETX 0 <-- -OLSX L1_PUTO 0 <-- -OLSX L1_PUTX 0 <-- -OLSX L1_PUTS_only 0 <-- -OLSX L1_PUTS 0 <-- -OLSX Fwd_GETX 0 <-- -OLSX Fwd_GETS 0 <-- -OLSX Fwd_DMA 0 <-- -OLSX L2_Replacement 0 <-- +OLSX L1_GETS [0 ] 0 +OLSX L1_GETX [0 ] 0 +OLSX L1_PUTO [0 ] 0 +OLSX L1_PUTX [0 ] 0 +OLSX L1_PUTS_only [0 ] 0 +OLSX L1_PUTS [0 ] 0 +OLSX Fwd_GETX [0 ] 0 +OLSX Fwd_GETS [0 ] 0 +OLSX Fwd_DMA [0 ] 0 +OLSX L2_Replacement [0 ] 0 -SLS L1_GETS 0 <-- -SLS L1_GETX 0 <-- -SLS L1_PUTX 0 <-- -SLS L1_PUTS_only 0 <-- -SLS L1_PUTS 0 <-- -SLS Inv 0 <-- -SLS L2_Replacement 0 <-- +SLS L1_GETS [0 ] 0 +SLS L1_GETX [0 ] 0 +SLS L1_PUTX [0 ] 0 +SLS L1_PUTS_only [0 ] 0 +SLS L1_PUTS [0 ] 0 +SLS Inv [0 ] 0 +SLS L2_Replacement [0 ] 0 -M L1_GETS 3 -M L1_GETX 32 -M L1_PUTO 0 <-- -M L1_PUTX 0 <-- -M L1_PUTS 0 <-- -M Fwd_GETX 0 <-- -M Fwd_GETS 0 <-- -M Fwd_DMA 0 <-- -M L2_Replacement 857 +M L1_GETS [6 ] 6 +M L1_GETX [40 ] 40 +M L1_PUTO [0 ] 0 +M L1_PUTX [0 ] 0 +M L1_PUTS [0 ] 0 +M Fwd_GETX [0 ] 0 +M Fwd_GETS [0 ] 0 +M Fwd_DMA [0 ] 0 +M L2_Replacement [874 ] 874 -IFGX L1_GETS 0 <-- -IFGX L1_GETX 0 <-- -IFGX L1_PUTO 0 <-- -IFGX L1_PUTX 0 <-- -IFGX L1_PUTS_only 0 <-- -IFGX L1_PUTS 0 <-- -IFGX Fwd_GETX 0 <-- -IFGX Fwd_GETS 0 <-- -IFGX Fwd_DMA 0 <-- -IFGX Inv 0 <-- -IFGX Data 0 <-- -IFGX Data_Exclusive 0 <-- -IFGX L2_Replacement 0 <-- +IFGX L1_GETS [0 ] 0 +IFGX L1_GETX [0 ] 0 +IFGX L1_PUTO [0 ] 0 +IFGX L1_PUTX [0 ] 0 +IFGX L1_PUTS_only [0 ] 0 +IFGX L1_PUTS [0 ] 0 +IFGX Fwd_GETX [0 ] 0 +IFGX Fwd_GETS [0 ] 0 +IFGX Fwd_DMA [0 ] 0 +IFGX Inv [0 ] 0 +IFGX Data [0 ] 0 +IFGX Data_Exclusive [0 ] 0 +IFGX L2_Replacement [0 ] 0 -IFGS L1_GETS 0 <-- -IFGS L1_GETX 0 <-- -IFGS L1_PUTO 0 <-- -IFGS L1_PUTX 0 <-- -IFGS L1_PUTS_only 0 <-- -IFGS L1_PUTS 0 <-- -IFGS Fwd_GETX 0 <-- -IFGS Fwd_GETS 0 <-- -IFGS Fwd_DMA 0 <-- -IFGS Inv 0 <-- -IFGS Data 0 <-- -IFGS Data_Exclusive 0 <-- -IFGS L2_Replacement 0 <-- +IFGS L1_GETS [0 ] 0 +IFGS L1_GETX [0 ] 0 +IFGS L1_PUTO [0 ] 0 +IFGS L1_PUTX [0 ] 0 +IFGS L1_PUTS_only [0 ] 0 +IFGS L1_PUTS [0 ] 0 +IFGS Fwd_GETX [0 ] 0 +IFGS Fwd_GETS [0 ] 0 +IFGS Fwd_DMA [0 ] 0 +IFGS Inv [0 ] 0 +IFGS Data [0 ] 0 +IFGS Data_Exclusive [0 ] 0 +IFGS L2_Replacement [0 ] 0 -ISFGS L1_GETS 0 <-- -ISFGS L1_GETX 0 <-- -ISFGS L1_PUTO 0 <-- -ISFGS L1_PUTX 0 <-- -ISFGS L1_PUTS_only 0 <-- -ISFGS L1_PUTS 0 <-- -ISFGS Fwd_GETX 0 <-- -ISFGS Fwd_GETS 0 <-- -ISFGS Fwd_DMA 0 <-- -ISFGS Inv 0 <-- -ISFGS Data 0 <-- -ISFGS L2_Replacement 0 <-- +ISFGS L1_GETS [0 ] 0 +ISFGS L1_GETX [0 ] 0 +ISFGS L1_PUTO [0 ] 0 +ISFGS L1_PUTX [0 ] 0 +ISFGS L1_PUTS_only [0 ] 0 +ISFGS L1_PUTS [0 ] 0 +ISFGS Fwd_GETX [0 ] 0 +ISFGS Fwd_GETS [0 ] 0 +ISFGS Fwd_DMA [0 ] 0 +ISFGS Inv [0 ] 0 +ISFGS Data [0 ] 0 +ISFGS L2_Replacement [0 ] 0 -IFGXX L1_GETS 0 <-- -IFGXX L1_GETX 0 <-- -IFGXX L1_PUTO 0 <-- -IFGXX L1_PUTX 0 <-- -IFGXX L1_PUTS_only 0 <-- -IFGXX L1_PUTS 0 <-- -IFGXX Fwd_GETX 0 <-- -IFGXX Fwd_GETS 0 <-- -IFGXX Fwd_DMA 0 <-- -IFGXX Inv 0 <-- -IFGXX IntAck 0 <-- -IFGXX All_Acks 0 <-- -IFGXX Data_Exclusive 0 <-- -IFGXX L2_Replacement 0 <-- +IFGXX L1_GETS [0 ] 0 +IFGXX L1_GETX [0 ] 0 +IFGXX L1_PUTO [0 ] 0 +IFGXX L1_PUTX [0 ] 0 +IFGXX L1_PUTS_only [0 ] 0 +IFGXX L1_PUTS [0 ] 0 +IFGXX Fwd_GETX [0 ] 0 +IFGXX Fwd_GETS [0 ] 0 +IFGXX Fwd_DMA [0 ] 0 +IFGXX Inv [0 ] 0 +IFGXX IntAck [0 ] 0 +IFGXX All_Acks [0 ] 0 +IFGXX Data_Exclusive [0 ] 0 +IFGXX L2_Replacement [0 ] 0 -OFGX L1_GETS 0 <-- -OFGX L1_GETX 0 <-- -OFGX L1_PUTO 0 <-- -OFGX L1_PUTX 0 <-- -OFGX L1_PUTS_only 0 <-- -OFGX L1_PUTS 0 <-- -OFGX Fwd_GETX 0 <-- -OFGX Fwd_GETS 0 <-- -OFGX Fwd_DMA 0 <-- -OFGX Inv 0 <-- -OFGX L2_Replacement 0 <-- +OFGX L1_GETS [0 ] 0 +OFGX L1_GETX [0 ] 0 +OFGX L1_PUTO [0 ] 0 +OFGX L1_PUTX [0 ] 0 +OFGX L1_PUTS_only [0 ] 0 +OFGX L1_PUTS [0 ] 0 +OFGX Fwd_GETX [0 ] 0 +OFGX Fwd_GETS [0 ] 0 +OFGX Fwd_DMA [0 ] 0 +OFGX Inv [0 ] 0 +OFGX L2_Replacement [0 ] 0 -OLSF L1_GETS 0 <-- -OLSF L1_GETX 0 <-- -OLSF L1_PUTO 0 <-- -OLSF L1_PUTX 0 <-- -OLSF L1_PUTS_only 0 <-- -OLSF L1_PUTS 0 <-- -OLSF Fwd_GETX 0 <-- -OLSF Fwd_GETS 0 <-- -OLSF Fwd_DMA 0 <-- -OLSF Inv 0 <-- -OLSF IntAck 0 <-- -OLSF All_Acks 0 <-- -OLSF L2_Replacement 0 <-- +OLSF L1_GETS [0 ] 0 +OLSF L1_GETX [0 ] 0 +OLSF L1_PUTO [0 ] 0 +OLSF L1_PUTX [0 ] 0 +OLSF L1_PUTS_only [0 ] 0 +OLSF L1_PUTS [0 ] 0 +OLSF Fwd_GETX [0 ] 0 +OLSF Fwd_GETS [0 ] 0 +OLSF Fwd_DMA [0 ] 0 +OLSF Inv [0 ] 0 +OLSF IntAck [0 ] 0 +OLSF All_Acks [0 ] 0 +OLSF L2_Replacement [0 ] 0 -ILOW L1_GETS 0 <-- -ILOW L1_GETX 0 <-- -ILOW L1_PUTO 0 <-- -ILOW L1_PUTX 0 <-- -ILOW L1_PUTS_only 0 <-- -ILOW L1_PUTS 0 <-- -ILOW Fwd_GETX 0 <-- -ILOW Fwd_GETS 0 <-- -ILOW Fwd_DMA 0 <-- -ILOW Inv 0 <-- -ILOW L1_WBCLEANDATA 0 <-- -ILOW L1_WBDIRTYDATA 0 <-- -ILOW Unblock 0 <-- -ILOW L2_Replacement 0 <-- +ILOW L1_GETS [0 ] 0 +ILOW L1_GETX [0 ] 0 +ILOW L1_PUTO [0 ] 0 +ILOW L1_PUTX [0 ] 0 +ILOW L1_PUTS_only [0 ] 0 +ILOW L1_PUTS [0 ] 0 +ILOW Fwd_GETX [0 ] 0 +ILOW Fwd_GETS [0 ] 0 +ILOW Fwd_DMA [0 ] 0 +ILOW Inv [0 ] 0 +ILOW L1_WBCLEANDATA [0 ] 0 +ILOW L1_WBDIRTYDATA [0 ] 0 +ILOW Unblock [0 ] 0 +ILOW L2_Replacement [0 ] 0 -ILOXW L1_GETS 0 <-- -ILOXW L1_GETX 0 <-- -ILOXW L1_PUTO 0 <-- -ILOXW L1_PUTX 0 <-- -ILOXW L1_PUTS_only 0 <-- -ILOXW L1_PUTS 0 <-- -ILOXW Fwd_GETX 0 <-- -ILOXW Fwd_GETS 0 <-- -ILOXW Fwd_DMA 0 <-- -ILOXW Inv 0 <-- -ILOXW L1_WBCLEANDATA 0 <-- -ILOXW L1_WBDIRTYDATA 0 <-- -ILOXW Unblock 0 <-- -ILOXW L2_Replacement 0 <-- +ILOXW L1_GETS [0 ] 0 +ILOXW L1_GETX [0 ] 0 +ILOXW L1_PUTO [0 ] 0 +ILOXW L1_PUTX [0 ] 0 +ILOXW L1_PUTS_only [0 ] 0 +ILOXW L1_PUTS [0 ] 0 +ILOXW Fwd_GETX [0 ] 0 +ILOXW Fwd_GETS [0 ] 0 +ILOXW Fwd_DMA [0 ] 0 +ILOXW Inv [0 ] 0 +ILOXW L1_WBCLEANDATA [0 ] 0 +ILOXW L1_WBDIRTYDATA [0 ] 0 +ILOXW Unblock [0 ] 0 +ILOXW L2_Replacement [0 ] 0 -ILOSW L1_GETS 0 <-- -ILOSW L1_GETX 0 <-- -ILOSW L1_PUTO 0 <-- -ILOSW L1_PUTX 0 <-- -ILOSW L1_PUTS_only 0 <-- -ILOSW L1_PUTS 0 <-- -ILOSW Fwd_GETX 0 <-- -ILOSW Fwd_GETS 0 <-- -ILOSW Fwd_DMA 0 <-- -ILOSW Inv 0 <-- -ILOSW L1_WBCLEANDATA 0 <-- -ILOSW L1_WBDIRTYDATA 0 <-- -ILOSW Unblock 0 <-- -ILOSW L2_Replacement 0 <-- +ILOSW L1_GETS [0 ] 0 +ILOSW L1_GETX [0 ] 0 +ILOSW L1_PUTO [0 ] 0 +ILOSW L1_PUTX [0 ] 0 +ILOSW L1_PUTS_only [0 ] 0 +ILOSW L1_PUTS [0 ] 0 +ILOSW Fwd_GETX [0 ] 0 +ILOSW Fwd_GETS [0 ] 0 +ILOSW Fwd_DMA [0 ] 0 +ILOSW Inv [0 ] 0 +ILOSW L1_WBCLEANDATA [0 ] 0 +ILOSW L1_WBDIRTYDATA [0 ] 0 +ILOSW Unblock [0 ] 0 +ILOSW L2_Replacement [0 ] 0 -ILOSXW L1_GETS 0 <-- -ILOSXW L1_GETX 0 <-- -ILOSXW L1_PUTO 0 <-- -ILOSXW L1_PUTX 0 <-- -ILOSXW L1_PUTS_only 0 <-- -ILOSXW L1_PUTS 0 <-- -ILOSXW Fwd_GETX 0 <-- -ILOSXW Fwd_GETS 0 <-- -ILOSXW Fwd_DMA 0 <-- -ILOSXW Inv 0 <-- -ILOSXW L1_WBCLEANDATA 0 <-- -ILOSXW L1_WBDIRTYDATA 0 <-- -ILOSXW Unblock 0 <-- -ILOSXW L2_Replacement 0 <-- +ILOSXW L1_GETS [0 ] 0 +ILOSXW L1_GETX [0 ] 0 +ILOSXW L1_PUTO [0 ] 0 +ILOSXW L1_PUTX [0 ] 0 +ILOSXW L1_PUTS_only [0 ] 0 +ILOSXW L1_PUTS [0 ] 0 +ILOSXW Fwd_GETX [0 ] 0 +ILOSXW Fwd_GETS [0 ] 0 +ILOSXW Fwd_DMA [0 ] 0 +ILOSXW Inv [0 ] 0 +ILOSXW L1_WBCLEANDATA [0 ] 0 +ILOSXW L1_WBDIRTYDATA [0 ] 0 +ILOSXW Unblock [0 ] 0 +ILOSXW L2_Replacement [0 ] 0 -SLSW L1_GETS 0 <-- -SLSW L1_GETX 0 <-- -SLSW L1_PUTO 0 <-- -SLSW L1_PUTX 0 <-- -SLSW L1_PUTS_only 0 <-- -SLSW L1_PUTS 0 <-- -SLSW Fwd_GETX 0 <-- -SLSW Fwd_GETS 0 <-- -SLSW Fwd_DMA 0 <-- -SLSW Inv 0 <-- -SLSW Unblock 0 <-- -SLSW L2_Replacement 0 <-- +SLSW L1_GETS [0 ] 0 +SLSW L1_GETX [0 ] 0 +SLSW L1_PUTO [0 ] 0 +SLSW L1_PUTX [0 ] 0 +SLSW L1_PUTS_only [0 ] 0 +SLSW L1_PUTS [0 ] 0 +SLSW Fwd_GETX [0 ] 0 +SLSW Fwd_GETS [0 ] 0 +SLSW Fwd_DMA [0 ] 0 +SLSW Inv [0 ] 0 +SLSW Unblock [0 ] 0 +SLSW L2_Replacement [0 ] 0 -OLSW L1_GETS 0 <-- -OLSW L1_GETX 0 <-- -OLSW L1_PUTO 0 <-- -OLSW L1_PUTX 0 <-- -OLSW L1_PUTS_only 0 <-- -OLSW L1_PUTS 0 <-- -OLSW Fwd_GETX 0 <-- -OLSW Fwd_GETS 0 <-- -OLSW Fwd_DMA 0 <-- -OLSW Inv 0 <-- -OLSW Unblock 0 <-- -OLSW L2_Replacement 0 <-- +OLSW L1_GETS [0 ] 0 +OLSW L1_GETX [0 ] 0 +OLSW L1_PUTO [0 ] 0 +OLSW L1_PUTX [0 ] 0 +OLSW L1_PUTS_only [0 ] 0 +OLSW L1_PUTS [0 ] 0 +OLSW Fwd_GETX [0 ] 0 +OLSW Fwd_GETS [0 ] 0 +OLSW Fwd_DMA [0 ] 0 +OLSW Inv [0 ] 0 +OLSW Unblock [0 ] 0 +OLSW L2_Replacement [0 ] 0 -ILSW L1_GETS 0 <-- -ILSW L1_GETX 0 <-- -ILSW L1_PUTO 0 <-- -ILSW L1_PUTX 0 <-- -ILSW L1_PUTS_only 0 <-- -ILSW L1_PUTS 0 <-- -ILSW Fwd_GETX 0 <-- -ILSW Fwd_GETS 0 <-- -ILSW Fwd_DMA 0 <-- -ILSW Inv 0 <-- -ILSW L1_WBCLEANDATA 0 <-- -ILSW Unblock 0 <-- -ILSW L2_Replacement 0 <-- +ILSW L1_GETS [0 ] 0 +ILSW L1_GETX [0 ] 0 +ILSW L1_PUTO [0 ] 0 +ILSW L1_PUTX [0 ] 0 +ILSW L1_PUTS_only [0 ] 0 +ILSW L1_PUTS [0 ] 0 +ILSW Fwd_GETX [0 ] 0 +ILSW Fwd_GETS [0 ] 0 +ILSW Fwd_DMA [0 ] 0 +ILSW Inv [0 ] 0 +ILSW L1_WBCLEANDATA [0 ] 0 +ILSW Unblock [0 ] 0 +ILSW L2_Replacement [0 ] 0 -IW L1_GETS 0 <-- -IW L1_GETX 0 <-- -IW L1_PUTO 0 <-- -IW L1_PUTX 0 <-- -IW L1_PUTS_only 0 <-- -IW L1_PUTS 0 <-- -IW Fwd_GETX 0 <-- -IW Fwd_GETS 0 <-- -IW Fwd_DMA 0 <-- -IW Inv 0 <-- -IW L1_WBCLEANDATA 0 <-- -IW L2_Replacement 0 <-- +IW L1_GETS [0 ] 0 +IW L1_GETX [0 ] 0 +IW L1_PUTO [0 ] 0 +IW L1_PUTX [0 ] 0 +IW L1_PUTS_only [0 ] 0 +IW L1_PUTS [0 ] 0 +IW Fwd_GETX [0 ] 0 +IW Fwd_GETS [0 ] 0 +IW Fwd_DMA [0 ] 0 +IW Inv [0 ] 0 +IW L1_WBCLEANDATA [0 ] 0 +IW L2_Replacement [0 ] 0 -OW L1_GETS 0 <-- -OW L1_GETX 0 <-- -OW L1_PUTO 0 <-- -OW L1_PUTX 0 <-- -OW L1_PUTS_only 0 <-- -OW L1_PUTS 0 <-- -OW Fwd_GETX 0 <-- -OW Fwd_GETS 0 <-- -OW Fwd_DMA 0 <-- -OW Inv 0 <-- -OW Unblock 0 <-- -OW L2_Replacement 0 <-- +OW L1_GETS [0 ] 0 +OW L1_GETX [0 ] 0 +OW L1_PUTO [0 ] 0 +OW L1_PUTX [0 ] 0 +OW L1_PUTS_only [0 ] 0 +OW L1_PUTS [0 ] 0 +OW Fwd_GETX [0 ] 0 +OW Fwd_GETS [0 ] 0 +OW Fwd_DMA [0 ] 0 +OW Inv [0 ] 0 +OW Unblock [0 ] 0 +OW L2_Replacement [0 ] 0 -SW L1_GETS 0 <-- -SW L1_GETX 0 <-- -SW L1_PUTO 0 <-- -SW L1_PUTX 0 <-- -SW L1_PUTS_only 0 <-- -SW L1_PUTS 0 <-- -SW Fwd_GETX 0 <-- -SW Fwd_GETS 0 <-- -SW Fwd_DMA 0 <-- -SW Inv 0 <-- -SW Unblock 0 <-- -SW L2_Replacement 0 <-- +SW L1_GETS [0 ] 0 +SW L1_GETX [0 ] 0 +SW L1_PUTO [0 ] 0 +SW L1_PUTX [0 ] 0 +SW L1_PUTS_only [0 ] 0 +SW L1_PUTS [0 ] 0 +SW Fwd_GETX [0 ] 0 +SW Fwd_GETS [0 ] 0 +SW Fwd_DMA [0 ] 0 +SW Inv [0 ] 0 +SW Unblock [0 ] 0 +SW L2_Replacement [0 ] 0 -OXW L1_GETS 0 <-- -OXW L1_GETX 0 <-- -OXW L1_PUTO 0 <-- -OXW L1_PUTX 0 <-- -OXW L1_PUTS_only 0 <-- -OXW L1_PUTS 0 <-- -OXW Fwd_GETX 0 <-- -OXW Fwd_GETS 0 <-- -OXW Fwd_DMA 0 <-- -OXW Inv 0 <-- -OXW Unblock 0 <-- -OXW L2_Replacement 0 <-- +OXW L1_GETS [0 ] 0 +OXW L1_GETX [0 ] 0 +OXW L1_PUTO [0 ] 0 +OXW L1_PUTX [0 ] 0 +OXW L1_PUTS_only [0 ] 0 +OXW L1_PUTS [0 ] 0 +OXW Fwd_GETX [0 ] 0 +OXW Fwd_GETS [0 ] 0 +OXW Fwd_DMA [0 ] 0 +OXW Inv [0 ] 0 +OXW Unblock [0 ] 0 +OXW L2_Replacement [0 ] 0 -OLSXW L1_GETS 0 <-- -OLSXW L1_GETX 0 <-- -OLSXW L1_PUTO 0 <-- -OLSXW L1_PUTX 0 <-- -OLSXW L1_PUTS_only 0 <-- -OLSXW L1_PUTS 0 <-- -OLSXW Fwd_GETX 0 <-- -OLSXW Fwd_GETS 0 <-- -OLSXW Fwd_DMA 0 <-- -OLSXW Inv 0 <-- -OLSXW Unblock 0 <-- -OLSXW L2_Replacement 0 <-- +OLSXW L1_GETS [0 ] 0 +OLSXW L1_GETX [0 ] 0 +OLSXW L1_PUTO [0 ] 0 +OLSXW L1_PUTX [0 ] 0 +OLSXW L1_PUTS_only [0 ] 0 +OLSXW L1_PUTS [0 ] 0 +OLSXW Fwd_GETX [0 ] 0 +OLSXW Fwd_GETS [0 ] 0 +OLSXW Fwd_DMA [0 ] 0 +OLSXW Inv [0 ] 0 +OLSXW Unblock [0 ] 0 +OLSXW L2_Replacement [0 ] 0 -ILXW L1_GETS 0 <-- -ILXW L1_GETX 0 <-- -ILXW L1_PUTO 0 <-- -ILXW L1_PUTX 0 <-- -ILXW L1_PUTS_only 0 <-- -ILXW L1_PUTS 0 <-- -ILXW Fwd_GETX 0 <-- -ILXW Fwd_GETS 0 <-- -ILXW Fwd_DMA 0 <-- -ILXW Inv 0 <-- -ILXW Data 0 <-- -ILXW L1_WBCLEANDATA 85 -ILXW L1_WBDIRTYDATA 810 -ILXW Unblock 0 <-- -ILXW L2_Replacement 0 <-- +ILXW L1_GETS [49 ] 49 +ILXW L1_GETX [1 ] 1 +ILXW L1_PUTO [0 ] 0 +ILXW L1_PUTX [0 ] 0 +ILXW L1_PUTS_only [0 ] 0 +ILXW L1_PUTS [0 ] 0 +ILXW Fwd_GETX [0 ] 0 +ILXW Fwd_GETS [0 ] 0 +ILXW Fwd_DMA [0 ] 0 +ILXW Inv [0 ] 0 +ILXW Data [0 ] 0 +ILXW L1_WBCLEANDATA [83 ] 83 +ILXW L1_WBDIRTYDATA [840 ] 840 +ILXW Unblock [0 ] 0 +ILXW L2_Replacement [0 ] 0 -IFLS L1_GETS 0 <-- -IFLS L1_GETX 0 <-- -IFLS L1_PUTO 0 <-- -IFLS L1_PUTX 0 <-- -IFLS L1_PUTS_only 0 <-- -IFLS L1_PUTS 0 <-- -IFLS Fwd_GETX 0 <-- -IFLS Fwd_GETS 0 <-- -IFLS Fwd_DMA 0 <-- -IFLS Inv 0 <-- -IFLS Unblock 0 <-- -IFLS L2_Replacement 0 <-- +IFLS L1_GETS [0 ] 0 +IFLS L1_GETX [0 ] 0 +IFLS L1_PUTO [0 ] 0 +IFLS L1_PUTX [0 ] 0 +IFLS L1_PUTS_only [0 ] 0 +IFLS L1_PUTS [0 ] 0 +IFLS Fwd_GETX [0 ] 0 +IFLS Fwd_GETS [0 ] 0 +IFLS Fwd_DMA [0 ] 0 +IFLS Inv [0 ] 0 +IFLS Unblock [0 ] 0 +IFLS L2_Replacement [0 ] 0 -IFLO L1_GETS 0 <-- -IFLO L1_GETX 0 <-- -IFLO L1_PUTO 0 <-- -IFLO L1_PUTX 0 <-- -IFLO L1_PUTS_only 0 <-- -IFLO L1_PUTS 0 <-- -IFLO Fwd_GETX 0 <-- -IFLO Fwd_GETS 0 <-- -IFLO Fwd_DMA 0 <-- -IFLO Inv 0 <-- -IFLO Unblock 0 <-- -IFLO L2_Replacement 0 <-- +IFLO L1_GETS [0 ] 0 +IFLO L1_GETX [0 ] 0 +IFLO L1_PUTO [0 ] 0 +IFLO L1_PUTX [0 ] 0 +IFLO L1_PUTS_only [0 ] 0 +IFLO L1_PUTS [0 ] 0 +IFLO Fwd_GETX [0 ] 0 +IFLO Fwd_GETS [0 ] 0 +IFLO Fwd_DMA [0 ] 0 +IFLO Inv [0 ] 0 +IFLO Unblock [0 ] 0 +IFLO L2_Replacement [0 ] 0 -IFLOX L1_GETS 0 <-- -IFLOX L1_GETX 0 <-- -IFLOX L1_PUTO 0 <-- -IFLOX L1_PUTX 0 <-- -IFLOX L1_PUTS_only 0 <-- -IFLOX L1_PUTS 0 <-- -IFLOX Fwd_GETX 0 <-- -IFLOX Fwd_GETS 0 <-- -IFLOX Fwd_DMA 0 <-- -IFLOX Inv 0 <-- -IFLOX Unblock 0 <-- -IFLOX Exclusive_Unblock 0 <-- -IFLOX L2_Replacement 0 <-- +IFLOX L1_GETS [0 ] 0 +IFLOX L1_GETX [0 ] 0 +IFLOX L1_PUTO [0 ] 0 +IFLOX L1_PUTX [0 ] 0 +IFLOX L1_PUTS_only [0 ] 0 +IFLOX L1_PUTS [0 ] 0 +IFLOX Fwd_GETX [0 ] 0 +IFLOX Fwd_GETS [0 ] 0 +IFLOX Fwd_DMA [0 ] 0 +IFLOX Inv [0 ] 0 +IFLOX Unblock [0 ] 0 +IFLOX Exclusive_Unblock [0 ] 0 +IFLOX L2_Replacement [0 ] 0 -IFLOXX L1_GETS 0 <-- -IFLOXX L1_GETX 0 <-- -IFLOXX L1_PUTO 0 <-- -IFLOXX L1_PUTX 0 <-- -IFLOXX L1_PUTS_only 0 <-- -IFLOXX L1_PUTS 0 <-- -IFLOXX Fwd_GETX 0 <-- -IFLOXX Fwd_GETS 0 <-- -IFLOXX Fwd_DMA 0 <-- -IFLOXX Inv 0 <-- -IFLOXX Unblock 0 <-- -IFLOXX Exclusive_Unblock 0 <-- -IFLOXX L2_Replacement 0 <-- +IFLOXX L1_GETS [0 ] 0 +IFLOXX L1_GETX [0 ] 0 +IFLOXX L1_PUTO [0 ] 0 +IFLOXX L1_PUTX [0 ] 0 +IFLOXX L1_PUTS_only [0 ] 0 +IFLOXX L1_PUTS [0 ] 0 +IFLOXX Fwd_GETX [0 ] 0 +IFLOXX Fwd_GETS [0 ] 0 +IFLOXX Fwd_DMA [0 ] 0 +IFLOXX Inv [0 ] 0 +IFLOXX Unblock [0 ] 0 +IFLOXX Exclusive_Unblock [0 ] 0 +IFLOXX L2_Replacement [0 ] 0 -IFLOSX L1_GETS 0 <-- -IFLOSX L1_GETX 0 <-- -IFLOSX L1_PUTO 0 <-- -IFLOSX L1_PUTX 0 <-- -IFLOSX L1_PUTS_only 0 <-- -IFLOSX L1_PUTS 0 <-- -IFLOSX Fwd_GETX 0 <-- -IFLOSX Fwd_GETS 0 <-- -IFLOSX Fwd_DMA 0 <-- -IFLOSX Inv 0 <-- -IFLOSX Unblock 0 <-- -IFLOSX Exclusive_Unblock 0 <-- -IFLOSX L2_Replacement 0 <-- +IFLOSX L1_GETS [0 ] 0 +IFLOSX L1_GETX [0 ] 0 +IFLOSX L1_PUTO [0 ] 0 +IFLOSX L1_PUTX [0 ] 0 +IFLOSX L1_PUTS_only [0 ] 0 +IFLOSX L1_PUTS [0 ] 0 +IFLOSX Fwd_GETX [0 ] 0 +IFLOSX Fwd_GETS [0 ] 0 +IFLOSX Fwd_DMA [0 ] 0 +IFLOSX Inv [0 ] 0 +IFLOSX Unblock [0 ] 0 +IFLOSX Exclusive_Unblock [0 ] 0 +IFLOSX L2_Replacement [0 ] 0 -IFLXO L1_GETS 0 <-- -IFLXO L1_GETX 0 <-- -IFLXO L1_PUTO 0 <-- -IFLXO L1_PUTX 0 <-- -IFLXO L1_PUTS_only 0 <-- -IFLXO L1_PUTS 0 <-- -IFLXO Fwd_GETX 0 <-- -IFLXO Fwd_GETS 0 <-- -IFLXO Fwd_DMA 0 <-- -IFLXO Inv 0 <-- -IFLXO Exclusive_Unblock 0 <-- -IFLXO L2_Replacement 0 <-- +IFLXO L1_GETS [0 ] 0 +IFLXO L1_GETX [0 ] 0 +IFLXO L1_PUTO [0 ] 0 +IFLXO L1_PUTX [0 ] 0 +IFLXO L1_PUTS_only [0 ] 0 +IFLXO L1_PUTS [0 ] 0 +IFLXO Fwd_GETX [0 ] 0 +IFLXO Fwd_GETS [0 ] 0 +IFLXO Fwd_DMA [0 ] 0 +IFLXO Inv [0 ] 0 +IFLXO Exclusive_Unblock [0 ] 0 +IFLXO L2_Replacement [0 ] 0 -IGS L1_GETS 0 <-- -IGS L1_GETX 0 <-- -IGS L1_PUTO 0 <-- -IGS L1_PUTX 122 -IGS L1_PUTS_only 0 <-- -IGS L1_PUTS 0 <-- -IGS Fwd_GETX 0 <-- -IGS Fwd_GETS 0 <-- -IGS Fwd_DMA 0 <-- -IGS Own_GETX 0 <-- -IGS Inv 0 <-- -IGS Data 0 <-- -IGS Data_Exclusive 86 -IGS Unblock 0 <-- -IGS Exclusive_Unblock 86 -IGS L2_Replacement 0 <-- +IGS L1_GETS [0 ] 0 +IGS L1_GETX [0 ] 0 +IGS L1_PUTO [0 ] 0 +IGS L1_PUTX [62 ] 62 +IGS L1_PUTS_only [0 ] 0 +IGS L1_PUTS [0 ] 0 +IGS Fwd_GETX [0 ] 0 +IGS Fwd_GETS [0 ] 0 +IGS Fwd_DMA [0 ] 0 +IGS Own_GETX [0 ] 0 +IGS Inv [0 ] 0 +IGS Data [0 ] 0 +IGS Data_Exclusive [86 ] 86 +IGS Unblock [0 ] 0 +IGS Exclusive_Unblock [85 ] 85 +IGS L2_Replacement [0 ] 0 -IGM L1_GETS 0 <-- -IGM L1_GETX 0 <-- -IGM L1_PUTO 0 <-- -IGM L1_PUTX 0 <-- -IGM L1_PUTS_only 0 <-- -IGM L1_PUTS 0 <-- -IGM Fwd_GETX 0 <-- -IGM Fwd_GETS 0 <-- -IGM Fwd_DMA 0 <-- -IGM Own_GETX 0 <-- -IGM Inv 0 <-- -IGM ExtAck 0 <-- -IGM Data 777 -IGM Data_Exclusive 0 <-- -IGM L2_Replacement 0 <-- +IGM L1_GETS [0 ] 0 +IGM L1_GETX [0 ] 0 +IGM L1_PUTO [0 ] 0 +IGM L1_PUTX [0 ] 0 +IGM L1_PUTS_only [0 ] 0 +IGM L1_PUTS [0 ] 0 +IGM Fwd_GETX [0 ] 0 +IGM Fwd_GETS [0 ] 0 +IGM Fwd_DMA [0 ] 0 +IGM Own_GETX [0 ] 0 +IGM Inv [0 ] 0 +IGM ExtAck [0 ] 0 +IGM Data [795 ] 795 +IGM Data_Exclusive [0 ] 0 +IGM L2_Replacement [0 ] 0 -IGMLS L1_GETS 0 <-- -IGMLS L1_GETX 0 <-- -IGMLS L1_PUTO 0 <-- -IGMLS L1_PUTX 0 <-- -IGMLS L1_PUTS_only 0 <-- -IGMLS L1_PUTS 0 <-- -IGMLS Inv 0 <-- -IGMLS IntAck 0 <-- -IGMLS ExtAck 0 <-- -IGMLS All_Acks 0 <-- -IGMLS Data 0 <-- -IGMLS Data_Exclusive 0 <-- -IGMLS L2_Replacement 0 <-- +IGMLS L1_GETS [0 ] 0 +IGMLS L1_GETX [0 ] 0 +IGMLS L1_PUTO [0 ] 0 +IGMLS L1_PUTX [0 ] 0 +IGMLS L1_PUTS_only [0 ] 0 +IGMLS L1_PUTS [0 ] 0 +IGMLS Inv [0 ] 0 +IGMLS IntAck [0 ] 0 +IGMLS ExtAck [0 ] 0 +IGMLS All_Acks [0 ] 0 +IGMLS Data [0 ] 0 +IGMLS Data_Exclusive [0 ] 0 +IGMLS L2_Replacement [0 ] 0 -IGMO L1_GETS 0 <-- -IGMO L1_GETX 0 <-- -IGMO L1_PUTO 0 <-- -IGMO L1_PUTX 1052 -IGMO L1_PUTS_only 0 <-- -IGMO L1_PUTS 0 <-- -IGMO Fwd_GETX 0 <-- -IGMO Fwd_GETS 0 <-- -IGMO Fwd_DMA 0 <-- -IGMO Own_GETX 0 <-- -IGMO ExtAck 0 <-- -IGMO All_Acks 777 -IGMO Exclusive_Unblock 777 -IGMO L2_Replacement 0 <-- +IGMO L1_GETS [0 ] 0 +IGMO L1_GETX [0 ] 0 +IGMO L1_PUTO [0 ] 0 +IGMO L1_PUTX [1243 ] 1243 +IGMO L1_PUTS_only [0 ] 0 +IGMO L1_PUTS [0 ] 0 +IGMO Fwd_GETX [0 ] 0 +IGMO Fwd_GETS [0 ] 0 +IGMO Fwd_DMA [0 ] 0 +IGMO Own_GETX [0 ] 0 +IGMO ExtAck [0 ] 0 +IGMO All_Acks [795 ] 795 +IGMO Exclusive_Unblock [795 ] 795 +IGMO L2_Replacement [0 ] 0 -IGMIO L1_GETS 0 <-- -IGMIO L1_GETX 0 <-- -IGMIO L1_PUTO 0 <-- -IGMIO L1_PUTX 0 <-- -IGMIO L1_PUTS_only 0 <-- -IGMIO L1_PUTS 0 <-- -IGMIO Fwd_GETX 0 <-- -IGMIO Fwd_GETS 0 <-- -IGMIO Fwd_DMA 0 <-- -IGMIO Own_GETX 0 <-- -IGMIO ExtAck 0 <-- -IGMIO All_Acks 0 <-- +IGMIO L1_GETS [0 ] 0 +IGMIO L1_GETX [0 ] 0 +IGMIO L1_PUTO [0 ] 0 +IGMIO L1_PUTX [0 ] 0 +IGMIO L1_PUTS_only [0 ] 0 +IGMIO L1_PUTS [0 ] 0 +IGMIO Fwd_GETX [0 ] 0 +IGMIO Fwd_GETS [0 ] 0 +IGMIO Fwd_DMA [0 ] 0 +IGMIO Own_GETX [0 ] 0 +IGMIO ExtAck [0 ] 0 +IGMIO All_Acks [0 ] 0 -OGMIO L1_GETS 0 <-- -OGMIO L1_GETX 0 <-- -OGMIO L1_PUTO 0 <-- -OGMIO L1_PUTX 0 <-- -OGMIO L1_PUTS_only 0 <-- -OGMIO L1_PUTS 0 <-- -OGMIO Fwd_GETX 0 <-- -OGMIO Fwd_GETS 0 <-- -OGMIO Fwd_DMA 0 <-- -OGMIO Own_GETX 0 <-- -OGMIO ExtAck 0 <-- -OGMIO All_Acks 0 <-- +OGMIO L1_GETS [0 ] 0 +OGMIO L1_GETX [0 ] 0 +OGMIO L1_PUTO [0 ] 0 +OGMIO L1_PUTX [0 ] 0 +OGMIO L1_PUTS_only [0 ] 0 +OGMIO L1_PUTS [0 ] 0 +OGMIO Fwd_GETX [0 ] 0 +OGMIO Fwd_GETS [0 ] 0 +OGMIO Fwd_DMA [0 ] 0 +OGMIO Own_GETX [0 ] 0 +OGMIO ExtAck [0 ] 0 +OGMIO All_Acks [0 ] 0 -IGMIOF L1_GETS 0 <-- -IGMIOF L1_GETX 0 <-- -IGMIOF L1_PUTO 0 <-- -IGMIOF L1_PUTX 0 <-- -IGMIOF L1_PUTS_only 0 <-- -IGMIOF L1_PUTS 0 <-- -IGMIOF IntAck 0 <-- -IGMIOF All_Acks 0 <-- -IGMIOF Data_Exclusive 0 <-- +IGMIOF L1_GETS [0 ] 0 +IGMIOF L1_GETX [0 ] 0 +IGMIOF L1_PUTO [0 ] 0 +IGMIOF L1_PUTX [0 ] 0 +IGMIOF L1_PUTS_only [0 ] 0 +IGMIOF L1_PUTS [0 ] 0 +IGMIOF IntAck [0 ] 0 +IGMIOF All_Acks [0 ] 0 +IGMIOF Data_Exclusive [0 ] 0 -IGMIOFS L1_GETS 0 <-- -IGMIOFS L1_GETX 0 <-- -IGMIOFS L1_PUTO 0 <-- -IGMIOFS L1_PUTX 0 <-- -IGMIOFS L1_PUTS_only 0 <-- -IGMIOFS L1_PUTS 0 <-- -IGMIOFS Fwd_GETX 0 <-- -IGMIOFS Fwd_GETS 0 <-- -IGMIOFS Fwd_DMA 0 <-- -IGMIOFS Inv 0 <-- -IGMIOFS Data 0 <-- -IGMIOFS L2_Replacement 0 <-- +IGMIOFS L1_GETS [0 ] 0 +IGMIOFS L1_GETX [0 ] 0 +IGMIOFS L1_PUTO [0 ] 0 +IGMIOFS L1_PUTX [0 ] 0 +IGMIOFS L1_PUTS_only [0 ] 0 +IGMIOFS L1_PUTS [0 ] 0 +IGMIOFS Fwd_GETX [0 ] 0 +IGMIOFS Fwd_GETS [0 ] 0 +IGMIOFS Fwd_DMA [0 ] 0 +IGMIOFS Inv [0 ] 0 +IGMIOFS Data [0 ] 0 +IGMIOFS L2_Replacement [0 ] 0 -OGMIOF L1_GETS 0 <-- -OGMIOF L1_GETX 0 <-- -OGMIOF L1_PUTO 0 <-- -OGMIOF L1_PUTX 0 <-- -OGMIOF L1_PUTS_only 0 <-- -OGMIOF L1_PUTS 0 <-- -OGMIOF IntAck 0 <-- -OGMIOF All_Acks 0 <-- +OGMIOF L1_GETS [0 ] 0 +OGMIOF L1_GETX [0 ] 0 +OGMIOF L1_PUTO [0 ] 0 +OGMIOF L1_PUTX [0 ] 0 +OGMIOF L1_PUTS_only [0 ] 0 +OGMIOF L1_PUTS [0 ] 0 +OGMIOF IntAck [0 ] 0 +OGMIOF All_Acks [0 ] 0 -II L1_GETS 0 <-- -II L1_GETX 0 <-- -II L1_PUTO 0 <-- -II L1_PUTX 0 <-- -II L1_PUTS_only 0 <-- -II L1_PUTS 0 <-- -II IntAck 0 <-- -II All_Acks 0 <-- +II L1_GETS [0 ] 0 +II L1_GETX [0 ] 0 +II L1_PUTO [0 ] 0 +II L1_PUTX [0 ] 0 +II L1_PUTS_only [0 ] 0 +II L1_PUTS [0 ] 0 +II IntAck [0 ] 0 +II All_Acks [0 ] 0 -MM L1_GETS 0 <-- -MM L1_GETX 0 <-- -MM L1_PUTO 0 <-- -MM L1_PUTX 5 -MM L1_PUTS_only 0 <-- -MM L1_PUTS 0 <-- -MM Fwd_GETX 0 <-- -MM Fwd_GETS 0 <-- -MM Fwd_DMA 0 <-- -MM Inv 0 <-- -MM Exclusive_Unblock 32 -MM L2_Replacement 0 <-- +MM L1_GETS [0 ] 0 +MM L1_GETX [0 ] 0 +MM L1_PUTO [0 ] 0 +MM L1_PUTX [11 ] 11 +MM L1_PUTS_only [0 ] 0 +MM L1_PUTS [0 ] 0 +MM Fwd_GETX [0 ] 0 +MM Fwd_GETS [0 ] 0 +MM Fwd_DMA [0 ] 0 +MM Inv [0 ] 0 +MM Exclusive_Unblock [40 ] 40 +MM L2_Replacement [0 ] 0 -SS L1_GETS 0 <-- -SS L1_GETX 0 <-- -SS L1_PUTO 0 <-- -SS L1_PUTX 0 <-- -SS L1_PUTS_only 0 <-- -SS L1_PUTS 0 <-- -SS Fwd_GETX 0 <-- -SS Fwd_GETS 0 <-- -SS Fwd_DMA 0 <-- -SS Inv 0 <-- -SS Unblock 0 <-- -SS L2_Replacement 0 <-- +SS L1_GETS [0 ] 0 +SS L1_GETX [0 ] 0 +SS L1_PUTO [0 ] 0 +SS L1_PUTX [0 ] 0 +SS L1_PUTS_only [0 ] 0 +SS L1_PUTS [0 ] 0 +SS Fwd_GETX [0 ] 0 +SS Fwd_GETS [0 ] 0 +SS Fwd_DMA [0 ] 0 +SS Inv [0 ] 0 +SS Unblock [0 ] 0 +SS L2_Replacement [0 ] 0 -OO L1_GETS 0 <-- -OO L1_GETX 0 <-- -OO L1_PUTO 0 <-- -OO L1_PUTX 0 <-- -OO L1_PUTS_only 0 <-- -OO L1_PUTS 0 <-- -OO Fwd_GETX 0 <-- -OO Fwd_GETS 0 <-- -OO Fwd_DMA 0 <-- -OO Inv 0 <-- -OO Unblock 0 <-- -OO Exclusive_Unblock 3 -OO L2_Replacement 0 <-- +OO L1_GETS [0 ] 0 +OO L1_GETX [0 ] 0 +OO L1_PUTO [0 ] 0 +OO L1_PUTX [0 ] 0 +OO L1_PUTS_only [0 ] 0 +OO L1_PUTS [0 ] 0 +OO Fwd_GETX [0 ] 0 +OO Fwd_GETS [0 ] 0 +OO Fwd_DMA [0 ] 0 +OO Inv [0 ] 0 +OO Unblock [0 ] 0 +OO Exclusive_Unblock [6 ] 6 +OO L2_Replacement [0 ] 0 -OLSS L1_GETS 0 <-- -OLSS L1_GETX 0 <-- -OLSS L1_PUTO 0 <-- -OLSS L1_PUTX 0 <-- -OLSS L1_PUTS_only 0 <-- -OLSS L1_PUTS 0 <-- -OLSS Fwd_GETX 0 <-- -OLSS Fwd_GETS 0 <-- -OLSS Fwd_DMA 0 <-- -OLSS Inv 0 <-- -OLSS Unblock 0 <-- -OLSS L2_Replacement 0 <-- +OLSS L1_GETS [0 ] 0 +OLSS L1_GETX [0 ] 0 +OLSS L1_PUTO [0 ] 0 +OLSS L1_PUTX [0 ] 0 +OLSS L1_PUTS_only [0 ] 0 +OLSS L1_PUTS [0 ] 0 +OLSS Fwd_GETX [0 ] 0 +OLSS Fwd_GETS [0 ] 0 +OLSS Fwd_DMA [0 ] 0 +OLSS Inv [0 ] 0 +OLSS Unblock [0 ] 0 +OLSS L2_Replacement [0 ] 0 -OLSXS L1_GETS 0 <-- -OLSXS L1_GETX 0 <-- -OLSXS L1_PUTO 0 <-- -OLSXS L1_PUTX 0 <-- -OLSXS L1_PUTS_only 0 <-- -OLSXS L1_PUTS 0 <-- -OLSXS Fwd_GETX 0 <-- -OLSXS Fwd_GETS 0 <-- -OLSXS Fwd_DMA 0 <-- -OLSXS Inv 0 <-- -OLSXS Unblock 0 <-- -OLSXS L2_Replacement 0 <-- +OLSXS L1_GETS [0 ] 0 +OLSXS L1_GETX [0 ] 0 +OLSXS L1_PUTO [0 ] 0 +OLSXS L1_PUTX [0 ] 0 +OLSXS L1_PUTS_only [0 ] 0 +OLSXS L1_PUTS [0 ] 0 +OLSXS Fwd_GETX [0 ] 0 +OLSXS Fwd_GETS [0 ] 0 +OLSXS Fwd_DMA [0 ] 0 +OLSXS Inv [0 ] 0 +OLSXS Unblock [0 ] 0 +OLSXS L2_Replacement [0 ] 0 -SLSS L1_GETS 0 <-- -SLSS L1_GETX 0 <-- -SLSS L1_PUTO 0 <-- -SLSS L1_PUTX 0 <-- -SLSS L1_PUTS_only 0 <-- -SLSS L1_PUTS 0 <-- -SLSS Fwd_GETX 0 <-- -SLSS Fwd_GETS 0 <-- -SLSS Fwd_DMA 0 <-- -SLSS Inv 0 <-- -SLSS Unblock 0 <-- -SLSS L2_Replacement 0 <-- +SLSS L1_GETS [0 ] 0 +SLSS L1_GETX [0 ] 0 +SLSS L1_PUTO [0 ] 0 +SLSS L1_PUTX [0 ] 0 +SLSS L1_PUTS_only [0 ] 0 +SLSS L1_PUTS [0 ] 0 +SLSS Fwd_GETX [0 ] 0 +SLSS Fwd_GETS [0 ] 0 +SLSS Fwd_DMA [0 ] 0 +SLSS Inv [0 ] 0 +SLSS Unblock [0 ] 0 +SLSS L2_Replacement [0 ] 0 -OI L1_GETS 0 <-- -OI L1_GETX 0 <-- -OI L1_PUTO 0 <-- -OI L1_PUTX 0 <-- -OI L1_PUTS_only 0 <-- -OI L1_PUTS 0 <-- -OI Fwd_GETX 0 <-- -OI Fwd_GETS 0 <-- -OI Fwd_DMA 0 <-- -OI Writeback_Ack 0 <-- -OI Writeback_Nack 0 <-- -OI L2_Replacement 0 <-- +OI L1_GETS [0 ] 0 +OI L1_GETX [0 ] 0 +OI L1_PUTO [0 ] 0 +OI L1_PUTX [0 ] 0 +OI L1_PUTS_only [0 ] 0 +OI L1_PUTS [0 ] 0 +OI Fwd_GETX [0 ] 0 +OI Fwd_GETS [0 ] 0 +OI Fwd_DMA [0 ] 0 +OI Writeback_Ack [0 ] 0 +OI Writeback_Nack [0 ] 0 +OI L2_Replacement [0 ] 0 -MI L1_GETS 43 -MI L1_GETX 37 -MI L1_PUTO 0 <-- -MI L1_PUTX 0 <-- -MI L1_PUTS_only 0 <-- -MI L1_PUTS 0 <-- -MI Fwd_GETX 0 <-- -MI Fwd_GETS 0 <-- -MI Fwd_DMA 0 <-- -MI Writeback_Ack 857 -MI L2_Replacement 0 <-- +MI L1_GETS [0 ] 0 +MI L1_GETX [18 ] 18 +MI L1_PUTO [0 ] 0 +MI L1_PUTX [0 ] 0 +MI L1_PUTS_only [0 ] 0 +MI L1_PUTS [0 ] 0 +MI Fwd_GETX [0 ] 0 +MI Fwd_GETS [0 ] 0 +MI Fwd_DMA [0 ] 0 +MI Writeback_Ack [873 ] 873 +MI L2_Replacement [0 ] 0 -MII L1_GETS 0 <-- -MII L1_GETX 0 <-- -MII L1_PUTO 0 <-- -MII L1_PUTX 0 <-- -MII L1_PUTS_only 0 <-- -MII L1_PUTS 0 <-- -MII Writeback_Ack 0 <-- -MII Writeback_Nack 0 <-- -MII L2_Replacement 0 <-- +MII L1_GETS [0 ] 0 +MII L1_GETX [0 ] 0 +MII L1_PUTO [0 ] 0 +MII L1_PUTX [0 ] 0 +MII L1_PUTS_only [0 ] 0 +MII L1_PUTS [0 ] 0 +MII Writeback_Ack [0 ] 0 +MII Writeback_Nack [0 ] 0 +MII L2_Replacement [0 ] 0 -OLSI L1_GETS 0 <-- -OLSI L1_GETX 0 <-- -OLSI L1_PUTO 0 <-- -OLSI L1_PUTX 0 <-- -OLSI L1_PUTS_only 0 <-- -OLSI L1_PUTS 0 <-- -OLSI Fwd_GETX 0 <-- -OLSI Fwd_GETS 0 <-- -OLSI Fwd_DMA 0 <-- -OLSI Writeback_Ack 0 <-- -OLSI L2_Replacement 0 <-- +OLSI L1_GETS [0 ] 0 +OLSI L1_GETX [0 ] 0 +OLSI L1_PUTO [0 ] 0 +OLSI L1_PUTX [0 ] 0 +OLSI L1_PUTS_only [0 ] 0 +OLSI L1_PUTS [0 ] 0 +OLSI Fwd_GETX [0 ] 0 +OLSI Fwd_GETS [0 ] 0 +OLSI Fwd_DMA [0 ] 0 +OLSI Writeback_Ack [0 ] 0 +OLSI L2_Replacement [0 ] 0 -ILSI L1_GETS 0 <-- -ILSI L1_GETX 0 <-- -ILSI L1_PUTO 0 <-- -ILSI L1_PUTX 0 <-- -ILSI L1_PUTS_only 0 <-- -ILSI L1_PUTS 0 <-- -ILSI IntAck 0 <-- -ILSI All_Acks 0 <-- -ILSI Writeback_Ack 0 <-- -ILSI L2_Replacement 0 <-- +ILSI L1_GETS [0 ] 0 +ILSI L1_GETX [0 ] 0 +ILSI L1_PUTO [0 ] 0 +ILSI L1_PUTX [0 ] 0 +ILSI L1_PUTS_only [0 ] 0 +ILSI L1_PUTS [0 ] 0 +ILSI IntAck [0 ] 0 +ILSI All_Acks [0 ] 0 +ILSI Writeback_Ack [0 ] 0 +ILSI L2_Replacement [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1635 - memory_reads: 863 - memory_writes: 772 - memory_refreshes: 798 - memory_total_request_delays: 689 - memory_delays_per_request: 0.421407 - memory_delays_in_input_queue: 101 - memory_delays_behind_head_of_bank_queue: 15 - memory_delays_stalled_at_head_of_bank_queue: 573 - memory_stalls_for_bank_busy: 170 +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1676 + memory_reads: 882 + memory_writes: 794 + memory_refreshes: 776 + memory_total_request_delays: 684 + memory_delays_per_request: 0.408115 + memory_delays_in_input_queue: 96 + memory_delays_behind_head_of_bank_queue: 16 + memory_delays_stalled_at_head_of_bank_queue: 572 + memory_stalls_for_bank_busy: 161 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 35 + memory_stalls_for_arbitration: 32 memory_stalls_for_bus: 229 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 73 - memory_stalls_for_read_read_turnaround: 66 - accesses_per_bank: 29 65 49 82 66 72 63 36 52 53 42 57 62 51 33 45 44 34 49 49 50 37 55 51 60 45 63 61 47 41 45 47 + memory_stalls_for_read_write_turnaround: 92 + memory_stalls_for_read_read_turnaround: 58 + accesses_per_bank: 47 54 48 87 71 72 66 51 62 62 38 48 48 50 38 58 54 41 58 48 53 30 45 51 53 45 55 52 44 43 42 62 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 782 -GETS 98 -PUTX 857 -PUTO 0 -PUTO_SHARERS 0 -Unblock 0 -Last_Unblock 0 -Exclusive_Unblock 862 -Clean_Writeback 85 -Dirty_Writeback 772 -Memory_Data 863 -Memory_Ack 772 -DMA_READ 0 -DMA_WRITE 0 -Data 0 +GETX [807 ] 807 +GETS [86 ] 86 +PUTX [873 ] 873 +PUTO [0 ] 0 +PUTO_SHARERS [0 ] 0 +Unblock [0 ] 0 +Last_Unblock [0 ] 0 +Exclusive_Unblock [880 ] 880 +Clean_Writeback [79 ] 79 +Dirty_Writeback [794 ] 794 +Memory_Data [882 ] 882 +Memory_Ack [793 ] 793 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Data [0 ] 0 - Transitions - -I GETX 777 -I GETS 86 -I PUTX 0 <-- -I PUTO 0 <-- -I Memory_Data 0 <-- -I Memory_Ack 767 -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [796 ] 796 +I GETS [86 ] 86 +I PUTX [0 ] 0 +I PUTO [0 ] 0 +I Memory_Data [0 ] 0 +I Memory_Ack [791 ] 791 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -S GETX 0 <-- -S GETS 0 <-- -S PUTX 0 <-- -S PUTO 0 <-- -S Memory_Data 0 <-- -S Memory_Ack 0 <-- -S DMA_READ 0 <-- -S DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUTX [0 ] 0 +S PUTO [0 ] 0 +S Memory_Data [0 ] 0 +S Memory_Ack [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUTX 0 <-- -O PUTO 0 <-- -O PUTO_SHARERS 0 <-- -O Memory_Data 0 <-- -O Memory_Ack 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUTX [0 ] 0 +O PUTO [0 ] 0 +O PUTO_SHARERS [0 ] 0 +O Memory_Data [0 ] 0 +O Memory_Ack [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -M GETX 0 <-- -M GETS 0 <-- -M PUTX 857 -M PUTO 0 <-- -M PUTO_SHARERS 0 <-- -M Memory_Data 0 <-- -M Memory_Ack 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [0 ] 0 +M GETS [0 ] 0 +M PUTX [873 ] 873 +M PUTO [0 ] 0 +M PUTO_SHARERS [0 ] 0 +M Memory_Data [0 ] 0 +M Memory_Ack [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -IS GETX 0 <-- -IS GETS 0 <-- -IS PUTX 0 <-- -IS PUTO 0 <-- -IS PUTO_SHARERS 0 <-- -IS Unblock 0 <-- -IS Exclusive_Unblock 86 -IS Memory_Data 86 -IS Memory_Ack 1 -IS DMA_READ 0 <-- -IS DMA_WRITE 0 <-- +IS GETX [0 ] 0 +IS GETS [0 ] 0 +IS PUTX [0 ] 0 +IS PUTO [0 ] 0 +IS PUTO_SHARERS [0 ] 0 +IS Unblock [0 ] 0 +IS Exclusive_Unblock [85 ] 85 +IS Memory_Data [86 ] 86 +IS Memory_Ack [1 ] 1 +IS DMA_READ [0 ] 0 +IS DMA_WRITE [0 ] 0 -SS GETX 0 <-- -SS GETS 0 <-- -SS PUTX 0 <-- -SS PUTO 0 <-- -SS PUTO_SHARERS 0 <-- -SS Unblock 0 <-- -SS Last_Unblock 0 <-- -SS Memory_Data 0 <-- -SS Memory_Ack 0 <-- -SS DMA_READ 0 <-- -SS DMA_WRITE 0 <-- +SS GETX [0 ] 0 +SS GETS [0 ] 0 +SS PUTX [0 ] 0 +SS PUTO [0 ] 0 +SS PUTO_SHARERS [0 ] 0 +SS Unblock [0 ] 0 +SS Last_Unblock [0 ] 0 +SS Memory_Data [0 ] 0 +SS Memory_Ack [0 ] 0 +SS DMA_READ [0 ] 0 +SS DMA_WRITE [0 ] 0 -OO GETX 0 <-- -OO GETS 0 <-- -OO PUTX 0 <-- -OO PUTO 0 <-- -OO PUTO_SHARERS 0 <-- -OO Unblock 0 <-- -OO Last_Unblock 0 <-- -OO Memory_Data 0 <-- -OO Memory_Ack 0 <-- -OO DMA_READ 0 <-- -OO DMA_WRITE 0 <-- +OO GETX [0 ] 0 +OO GETS [0 ] 0 +OO PUTX [0 ] 0 +OO PUTO [0 ] 0 +OO PUTO_SHARERS [0 ] 0 +OO Unblock [0 ] 0 +OO Last_Unblock [0 ] 0 +OO Memory_Data [0 ] 0 +OO Memory_Ack [0 ] 0 +OO DMA_READ [0 ] 0 +OO DMA_WRITE [0 ] 0 -MO GETX 0 <-- -MO GETS 0 <-- -MO PUTX 0 <-- -MO PUTO 0 <-- -MO PUTO_SHARERS 0 <-- -MO Unblock 0 <-- -MO Exclusive_Unblock 0 <-- -MO Memory_Data 0 <-- -MO Memory_Ack 0 <-- -MO DMA_READ 0 <-- -MO DMA_WRITE 0 <-- +MO GETX [0 ] 0 +MO GETS [0 ] 0 +MO PUTX [0 ] 0 +MO PUTO [0 ] 0 +MO PUTO_SHARERS [0 ] 0 +MO Unblock [0 ] 0 +MO Exclusive_Unblock [0 ] 0 +MO Memory_Data [0 ] 0 +MO Memory_Ack [0 ] 0 +MO DMA_READ [0 ] 0 +MO DMA_WRITE [0 ] 0 -MM GETX 0 <-- -MM GETS 0 <-- -MM PUTX 0 <-- -MM PUTO 0 <-- -MM PUTO_SHARERS 0 <-- -MM Exclusive_Unblock 776 -MM Memory_Data 777 -MM Memory_Ack 4 -MM DMA_READ 0 <-- -MM DMA_WRITE 0 <-- +MM GETX [0 ] 0 +MM GETS [0 ] 0 +MM PUTX [0 ] 0 +MM PUTO [0 ] 0 +MM PUTO_SHARERS [0 ] 0 +MM Exclusive_Unblock [795 ] 795 +MM Memory_Data [796 ] 796 +MM Memory_Ack [1 ] 1 +MM DMA_READ [0 ] 0 +MM DMA_WRITE [0 ] 0 -MI GETX 5 -MI GETS 12 -MI PUTX 0 <-- -MI PUTO 0 <-- -MI PUTO_SHARERS 0 <-- -MI Unblock 0 <-- -MI Clean_Writeback 85 -MI Dirty_Writeback 772 -MI Memory_Data 0 <-- -MI Memory_Ack 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- +MI GETX [11 ] 11 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTO [0 ] 0 +MI PUTO_SHARERS [0 ] 0 +MI Unblock [0 ] 0 +MI Clean_Writeback [79 ] 79 +MI Dirty_Writeback [794 ] 794 +MI Memory_Data [0 ] 0 +MI Memory_Ack [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 -MIS GETX 0 <-- -MIS GETS 0 <-- -MIS PUTX 0 <-- -MIS PUTO 0 <-- -MIS PUTO_SHARERS 0 <-- -MIS Unblock 0 <-- -MIS Clean_Writeback 0 <-- -MIS Dirty_Writeback 0 <-- -MIS Memory_Data 0 <-- -MIS Memory_Ack 0 <-- -MIS DMA_READ 0 <-- -MIS DMA_WRITE 0 <-- +MIS GETX [0 ] 0 +MIS GETS [0 ] 0 +MIS PUTX [0 ] 0 +MIS PUTO [0 ] 0 +MIS PUTO_SHARERS [0 ] 0 +MIS Unblock [0 ] 0 +MIS Clean_Writeback [0 ] 0 +MIS Dirty_Writeback [0 ] 0 +MIS Memory_Data [0 ] 0 +MIS Memory_Ack [0 ] 0 +MIS DMA_READ [0 ] 0 +MIS DMA_WRITE [0 ] 0 -OS GETX 0 <-- -OS GETS 0 <-- -OS PUTX 0 <-- -OS PUTO 0 <-- -OS PUTO_SHARERS 0 <-- -OS Unblock 0 <-- -OS Clean_Writeback 0 <-- -OS Dirty_Writeback 0 <-- -OS Memory_Data 0 <-- -OS Memory_Ack 0 <-- -OS DMA_READ 0 <-- -OS DMA_WRITE 0 <-- +OS GETX [0 ] 0 +OS GETS [0 ] 0 +OS PUTX [0 ] 0 +OS PUTO [0 ] 0 +OS PUTO_SHARERS [0 ] 0 +OS Unblock [0 ] 0 +OS Clean_Writeback [0 ] 0 +OS Dirty_Writeback [0 ] 0 +OS Memory_Data [0 ] 0 +OS Memory_Ack [0 ] 0 +OS DMA_READ [0 ] 0 +OS DMA_WRITE [0 ] 0 -OSS GETX 0 <-- -OSS GETS 0 <-- -OSS PUTX 0 <-- -OSS PUTO 0 <-- -OSS PUTO_SHARERS 0 <-- -OSS Unblock 0 <-- -OSS Clean_Writeback 0 <-- -OSS Dirty_Writeback 0 <-- -OSS Memory_Data 0 <-- -OSS Memory_Ack 0 <-- -OSS DMA_READ 0 <-- -OSS DMA_WRITE 0 <-- +OSS GETX [0 ] 0 +OSS GETS [0 ] 0 +OSS PUTX [0 ] 0 +OSS PUTO [0 ] 0 +OSS PUTO_SHARERS [0 ] 0 +OSS Unblock [0 ] 0 +OSS Clean_Writeback [0 ] 0 +OSS Dirty_Writeback [0 ] 0 +OSS Memory_Data [0 ] 0 +OSS Memory_Ack [0 ] 0 +OSS DMA_READ [0 ] 0 +OSS DMA_WRITE [0 ] 0 -XI_M GETX 0 <-- -XI_M GETS 0 <-- -XI_M PUTX 0 <-- -XI_M PUTO 0 <-- -XI_M PUTO_SHARERS 0 <-- -XI_M Memory_Data 0 <-- -XI_M Memory_Ack 0 <-- -XI_M DMA_READ 0 <-- -XI_M DMA_WRITE 0 <-- +XI_M GETX [0 ] 0 +XI_M GETS [0 ] 0 +XI_M PUTX [0 ] 0 +XI_M PUTO [0 ] 0 +XI_M PUTO_SHARERS [0 ] 0 +XI_M Memory_Data [0 ] 0 +XI_M Memory_Ack [0 ] 0 +XI_M DMA_READ [0 ] 0 +XI_M DMA_WRITE [0 ] 0 -XI_U GETX 0 <-- -XI_U GETS 0 <-- -XI_U PUTX 0 <-- -XI_U PUTO 0 <-- -XI_U PUTO_SHARERS 0 <-- -XI_U Exclusive_Unblock 0 <-- -XI_U Memory_Ack 0 <-- -XI_U DMA_READ 0 <-- -XI_U DMA_WRITE 0 <-- +XI_U GETX [0 ] 0 +XI_U GETS [0 ] 0 +XI_U PUTX [0 ] 0 +XI_U PUTO [0 ] 0 +XI_U PUTO_SHARERS [0 ] 0 +XI_U Exclusive_Unblock [0 ] 0 +XI_U Memory_Ack [0 ] 0 +XI_U DMA_READ [0 ] 0 +XI_U DMA_WRITE [0 ] 0 -OI_D GETX 0 <-- -OI_D GETS 0 <-- -OI_D PUTX 0 <-- -OI_D PUTO 0 <-- -OI_D PUTO_SHARERS 0 <-- -OI_D DMA_READ 0 <-- -OI_D DMA_WRITE 0 <-- -OI_D Data 0 <-- - +OI_D GETX [0 ] 0 +OI_D GETS [0 ] 0 +OI_D PUTX [0 ] 0 +OI_D PUTO [0 ] 0 +OI_D PUTO_SHARERS [0 ] 0 +OI_D DMA_READ [0 ] 0 +OI_D DMA_WRITE [0 ] 0 +OI_D Data \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:39:50 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:40:19 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:34:54 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:40:24 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_directory/m5.fast -d build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory -re tests/run.py build/ALPHA_SE_MOESI_CMP_directory/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_directory Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 382981 because Ruby Tester completed +Exiting @ tick 372291 because Ruby Tester completed diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_directory/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208684 # Number of bytes of host memory used -host_seconds 6.96 # Real time elapsed on the host -host_tick_rate 55013 # Simulator tick rate (ticks/s) +host_mem_usage 210064 # Number of bytes of host memory used +host_seconds 0.80 # Real time elapsed on the host +host_tick_rate 465329 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000383 # Number of seconds simulated -sim_ticks 382981 # Number of ticks simulated +sim_seconds 0.000372 # Number of seconds simulated +sim_ticks 372291 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,125 @@ [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 l2_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=5 +distributed_persistent=true +fixed_timeout_latency=100 +l2_select_num_bits=0 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +N_tokens=2 +buffer_size=0 +dynamic_timeout_enabled=true +fixed_timeout_latency=300 +l1_request_latency=2 +l1_response_latency=2 +l2_select_num_bits=0 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +retry_threshold=1 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l2_cntrl0] +type=L2Cache_Controller +children=L2cacheMemory +L2cacheMemory=system.l2_cntrl0.L2cacheMemory +N_tokens=2 +buffer_size=0 +filtering_enabled=true +l2_request_latency=5 +l2_response_latency=5 +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.l2_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=0 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +132,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,147 +173,34 @@ children=ext_links0 ext_links1 ext_links2 int_links0 int_links1 int_links2 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 +name=Crossbar num_int_nodes=4 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -N_tokens=2 -buffer_size=0 -dynamic_timeout_enabled=true -fixed_timeout_latency=300 -l1_request_latency=2 -l1_response_latency=2 -l2_select_num_bits=0 -number_of_TBEs=256 -recycle_latency=10 -retry_threshold=1 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.l2_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=L2Cache_Controller -children=L2cacheMemory -L2cacheMemory=system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory -N_tokens=2 -buffer_size=0 -filtering_enabled=true -l2_request_latency=10 -l2_response_latency=10 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - [system.ruby.network.topology.ext_links2] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links2.ext_node +ext_node=system.dir_cntrl0 int_node=2 latency=1 weight=1 -[system.ruby.network.topology.ext_links2.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links2.ext_node.directory -directory_latency=6 -distributed_persistent=true -fixed_timeout_latency=300 -l2_select_num_bits=0 -memBuffer=system.ruby.network.topology.ext_links2.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links2.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, unordered @@ -34,7 +34,7 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:58:52 +Real time: Aug/05/2010 10:45:27 Profiler Stats -------------- @@ -43,20 +43,20 @@ Elapsed_time_in_hours: 0 Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.69 -Virtual_time_in_minutes: 0.0115 -Virtual_time_in_hours: 0.000191667 -Virtual_time_in_days: 7.98611e-06 +Virtual_time_in_seconds: 0.75 +Virtual_time_in_minutes: 0.0125 +Virtual_time_in_hours: 0.000208333 +Virtual_time_in_days: 8.68056e-06 -Ruby_current_time: 275491 +Ruby_current_time: 273851 Ruby_start_time: 0 -Ruby_cycles: 275491 +Ruby_cycles: 273851 -mbytes_resident: 30.7305 -mbytes_total: 203.652 -resident_ratio: 0.150935 +mbytes_resident: 31.5859 +mbytes_total: 31.5938 +resident_ratio: 1 -ruby_cycles_executed: [ 275492 ] +ruby_cycles_executed: [ 273852 ] Busy Controller Counts: L1Cache-0:0 @@ -66,13 +66,36 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 981 average: 15.8389 | standard deviation: 1.13074 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 39 928 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 1015 average: 15.8108 | standard deviation: 1.12266 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 71 929 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 24779 count: 966 average: 4458.37 | standard deviation: 6768.43 | 97 8 26 62 82 65 44 31 43 37 32 21 22 21 13 17 18 13 11 4 12 15 6 1 6 11 3 4 7 3 4 1 4 5 3 4 3 2 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 2 1 1 0 1 1 1 1 3 0 0 1 2 0 1 0 0 2 1 0 0 0 1 2 1 0 1 0 2 3 1 0 1 2 0 1 1 7 1 0 4 3 0 3 3 5 2 1 2 0 3 1 2 3 1 0 5 3 1 4 2 4 1 2 3 0 2 3 1 1 1 2 6 0 0 2 0 4 3 1 2 3 1 3 2 2 2 2 3 1 5 0 2 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 22427 count: 100 average: 4703.38 | standard deviation: 6898.45 | 12 2 2 7 12 6 4 3 6 3 1 1 1 3 1 2 2 0 1 0 1 2 0 0 2 0 0 0 0 0 0 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 2 2 0 1 0 1 1 0 0 0 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 128 max: 24779 count: 866 average: 4430.08 | standard deviation: 6756.74 | 85 6 24 55 70 59 40 28 37 34 31 20 21 18 12 15 16 13 10 4 11 13 6 1 4 11 3 4 7 3 4 1 3 5 3 3 3 1 2 3 1 2 0 0 1 1 0 0 0 0 2 0 1 0 1 0 2 1 0 0 0 0 2 2 0 0 1 0 0 0 0 0 0 1 0 2 0 2 1 0 1 1 2 1 1 1 0 1 1 1 1 3 0 0 1 1 0 1 0 0 1 1 0 0 0 1 2 1 0 1 0 2 2 1 0 1 2 0 1 1 5 1 0 2 1 0 2 3 4 1 1 2 0 2 1 1 3 1 0 5 3 1 4 1 3 1 2 3 0 1 3 1 1 1 1 5 0 0 2 0 4 3 0 2 3 1 3 2 1 2 2 3 1 5 0 1 0 0 1 0 2 1 0 3 2 1 1 1 2 0 2 0 2 1 0 0 0 0 0 0 ] +miss_latency: [binsize: 256 max: 25954 count: 1000 average: 4306.83 | standard deviation: 6237.5 | 90 103 157 85 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1385 count: 59 average: 543.102 | standard deviation: 246.871 | 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 1 1 2 0 1 0 6 3 1 0 0 0 0 0 1 1 2 1 1 3 2 0 0 0 0 0 1 1 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 21253 count: 41 average: 5185.15 | standard deviation: 6664.34 | 3 0 2 1 2 3 5 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST: [binsize: 256 max: 25954 count: 900 average: 4513.56 | standard deviation: 6344.01 | 83 72 134 72 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 115 count: 78 average: 10.8205 | standard deviation: 28.5871 | 0 16 15 20 21 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] +miss_latency_L2Cache: [binsize: 8 max: 1002 count: 20 average: 461.5 | standard deviation: 273.391 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 2 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 256 max: 25954 count: 902 average: 4763.59 | standard deviation: 6403.26 | 6 96 154 81 75 57 42 27 20 32 16 10 14 7 9 7 5 3 3 5 3 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 3 1 0 3 1 5 2 3 0 1 3 3 2 1 0 1 7 2 4 2 6 3 7 9 5 8 5 9 8 8 4 6 2 0 7 4 10 7 3 3 0 1 6 2 1 1 1 2 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 902 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 4 count: 1 average: 4 | standard deviation: 0 | 0 0 0 0 1 ] +miss_latency_IFETCH_L2Cache: [binsize: 4 max: 568 count: 7 average: 329.571 | standard deviation: 182.864 | 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1385 count: 51 average: 582.98 | standard deviation: 229.926 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 0 0 0 0 0 1 0 1 0 6 3 1 0 0 0 0 0 0 1 2 1 1 3 2 0 0 0 0 0 1 0 0 0 1 0 1 2 3 1 0 0 0 0 0 1 0 0 0 1 0 2 1 1 0 0 0 0 0 0 0 1 0 0 0 2 0 0 1 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 3 average: 2.33333 | standard deviation: 1.22474 | 0 1 0 2 ] +miss_latency_LD_L2Cache: [binsize: 8 max: 843 count: 2 average: 551.5 | standard deviation: 412.244 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 128 max: 21253 count: 36 average: 5874.47 | standard deviation: 6836.32 | 0 0 1 1 2 3 4 1 0 0 2 2 2 0 1 1 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 115 count: 74 average: 11.2568 | standard deviation: 29.2947 | 0 15 15 18 20 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 2 1 ] +miss_latency_ST_L2Cache: [binsize: 8 max: 1002 count: 11 average: 529.091 | standard deviation: 293.469 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 256 max: 25954 count: 815 average: 4976.13 | standard deviation: 6494.33 | 5 70 132 69 74 52 40 25 20 31 16 10 14 6 9 6 5 3 2 5 2 8 7 2 2 4 3 2 3 2 2 0 2 1 1 3 2 1 0 3 1 4 2 3 0 1 3 3 2 0 0 1 7 2 4 2 6 3 6 8 5 7 4 9 8 7 4 6 2 0 7 4 9 7 3 2 0 1 6 2 1 1 1 1 0 1 2 1 1 0 1 2 1 1 0 1 1 0 0 1 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -104,8 +127,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8875 -page_faults: 0 +page_reclaims: 7004 +page_faults: 1904 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -113,792 +136,918 @@ Network Stats ------------- +total_msg_count_Request_Control: 5485 43880 +total_msg_count_Response_Data: 2871 206712 +total_msg_count_ResponseL2hit_Data: 51 3672 +total_msg_count_Response_Control: 9 72 +total_msg_count_Writeback_Data: 5349 385128 +total_msg_count_Writeback_Control: 246 1968 +total_msg_count_Persistent_Control: 2292 18336 +total_msgs: 16303 total_bytes: 659768 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.110194 - links_utilized_percent_switch_0_link_0: 0.0410177 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.179371 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.115928 + links_utilized_percent_switch_0_link_0: 0.0432124 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.188643 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 932 67104 [ 0 0 0 0 932 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 923 7384 [ 0 923 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 977 70344 [ 0 0 0 0 977 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.092866 - links_utilized_percent_switch_1_link_0: 0.0408816 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.14485 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.0997532 + links_utilized_percent_switch_1_link_0: 0.0435821 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.155924 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 28 2016 [ 0 0 0 0 28 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Data: 729 52488 [ 0 0 0 0 729 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Control: 2 16 [ 0 0 0 0 2 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Data: 796 57312 [ 0 0 0 0 796 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_1_link_1_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.0881086 - links_utilized_percent_switch_2_link_0: 0.0370475 bw: 640000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.13917 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.09541 + links_utilized_percent_switch_2_link_0: 0.040428 bw: 640000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.150392 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_0_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Response_Data: 845 60840 [ 0 0 0 0 845 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 7 504 [ 0 0 0 0 7 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 905 65160 [ 0 0 0 0 905 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 10 720 [ 0 0 0 0 10 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 switch_3_inlinks: 3 switch_3_outlinks: 3 -links_utilized_percent_switch_3: 0.156502 - links_utilized_percent_switch_3_link_0: 0.157791 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_1: 0.163526 bw: 160000 base_latency: 1 - links_utilized_percent_switch_3_link_2: 0.14819 bw: 160000 base_latency: 1 +links_utilized_percent_switch_3: 0.167305 + links_utilized_percent_switch_3_link_0: 0.165875 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 0.174328 bw: 160000 base_latency: 1 + links_utilized_percent_switch_3_link_2: 0.161712 bw: 160000 base_latency: 1 - outgoing_messages_switch_3_link_0_Response_Data: 873 62856 [ 0 0 0 0 873 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 27 1944 [ 0 0 0 0 27 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_0_Writeback_Data: 66 4752 [ 0 0 0 0 66 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Request_Control: 870 6960 [ 0 870 0 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Writeback_Data: 866 62352 [ 0 0 0 0 866 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_1_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Request_Control: 844 6752 [ 0 0 844 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Response_Data: 31 2232 [ 0 0 0 0 31 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Writeback_Data: 735 52920 [ 0 0 0 0 735 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Data: 931 67032 [ 0 0 0 0 931 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_ResponseL2hit_Data: 17 1224 [ 0 0 0 0 17 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Response_Control: 3 24 [ 0 0 0 0 3 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Data: 61 4392 [ 0 0 0 0 61 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 1 8 [ 0 0 0 0 1 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Request_Control: 922 7376 [ 0 922 0 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Writeback_Data: 916 65952 [ 0 0 0 0 916 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Request_Control: 906 7248 [ 0 0 906 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Response_Data: 26 1872 [ 0 0 0 0 26 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Writeback_Data: 806 58032 [ 0 0 0 0 806 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_3_link_2_Writeback_Control: 81 648 [ 0 0 0 0 81 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_3_link_2_Persistent_Control: 346 2768 [ 0 0 0 346 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_2_Persistent_Control: 382 3056 [ 0 0 0 382 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 58 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 58 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 58 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 865 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 865 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - --- L1Cache 0 --- + system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.39306% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.6069% + + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 865 100% + + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 867 -L1_Replacement 395000 -Data_Shared 1 -Data_Owner 0 -Data_All_Tokens 965 -Ack 0 -Ack_All_Tokens 0 -Transient_GETX 0 -Transient_Local_GETX 0 -Transient_GETS 0 -Transient_Local_GETS 0 -Transient_GETS_Last_Token 0 -Transient_Local_GETS_Last_Token 0 -Persistent_GETX 0 -Persistent_GETS 0 -Own_Lock_or_Unlock 346 -Request_Timeout 545 -Use_TimeoutStarverX 0 -Use_TimeoutStarverS 0 -Use_TimeoutNoStarvers 867 +Load [41 ] 41 +Ifetch [59 ] 59 +Store [901 ] 901 +Atomic [0 ] 0 +L1_Replacement [388292 ] 388292 +Data_Shared [9 ] 9 +Data_Owner [2 ] 2 +Data_All_Tokens [998 ] 998 +Ack [2 ] 2 +Ack_All_Tokens [2 ] 2 +Transient_GETX [0 ] 0 +Transient_Local_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_Local_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +Transient_Local_GETS_Last_Token [0 ] 0 +Persistent_GETX [0 ] 0 +Persistent_GETS [0 ] 0 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [382 ] 382 +Request_Timeout [674 ] 674 +Use_TimeoutStarverX [0 ] 0 +Use_TimeoutStarverS [0 ] 0 +Use_TimeoutNoStarvers [912 ] 912 +Use_TimeoutNoStarvers_NoMig [0 ] 0 - Transitions - -NP Load 88 -NP Ifetch 0 <-- -NP Store 781 -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 97 -NP Ack 0 <-- -NP Transient_GETX 0 <-- -NP Transient_Local_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Transient_Local_GETS 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 171 +NP Load [38 ] 38 +NP Ifetch [58 ] 58 +NP Store [826 ] 826 +NP Atomic [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [87 ] 87 +NP Ack [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_Local_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Transient_Local_GETS [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [175 ] 175 -I Load 0 <-- -I Ifetch 0 <-- -I Store 0 <-- -I L1_Replacement 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Transient_GETX 0 <-- -I Transient_Local_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_Local_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I Transient_Local_GETS_Last_Token 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I Load [0 ] 0 +I Ifetch [0 ] 0 +I Store [0 ] 0 +I Atomic [0 ] 0 +I L1_Replacement [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_Local_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_Local_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I Transient_Local_GETS_Last_Token [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 1 -S L1_Replacement 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Transient_GETX 0 <-- -S Transient_Local_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_Local_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S Transient_Local_GETS_Last_Token 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S Load [0 ] 0 +S Ifetch [1 ] 1 +S Store [1 ] 1 +S Atomic [0 ] 0 +S L1_Replacement [8 ] 8 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_Local_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_Local_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S Transient_Local_GETS_Last_Token [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L1_Replacement 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Transient_GETX 0 <-- -O Transient_Local_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_Local_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O Transient_Local_GETS_Last_Token 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O Atomic [0 ] 0 +O L1_Replacement [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_Local_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_Local_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O Transient_Local_GETS_Last_Token [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M Load 0 <-- -M Ifetch 0 <-- -M Store 0 <-- -M L1_Replacement 86 -M Transient_GETX 0 <-- -M Transient_Local_GETX 0 <-- -M Transient_GETS 0 <-- -M Transient_Local_GETS 0 <-- -M Persistent_GETX 0 <-- -M Persistent_GETS 0 <-- -M Own_Lock_or_Unlock 2 +M Load [0 ] 0 +M Ifetch [0 ] 0 +M Store [0 ] 0 +M Atomic [0 ] 0 +M L1_Replacement [83 ] 83 +M Transient_GETX [0 ] 0 +M Transient_Local_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M Transient_Local_GETS [0 ] 0 +M Persistent_GETX [0 ] 0 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [12 ] 12 -MM Load 12 -MM Ifetch 0 <-- -MM Store 74 -MM L1_Replacement 780 -MM Transient_GETX 0 <-- -MM Transient_Local_GETX 0 <-- -MM Transient_GETS 0 <-- -MM Transient_Local_GETS 0 <-- -MM Persistent_GETX 0 <-- -MM Persistent_GETS 0 <-- -MM Own_Lock_or_Unlock 17 +MM Load [2 ] 2 +MM Ifetch [0 ] 0 +MM Store [64 ] 64 +MM Atomic [0 ] 0 +MM L1_Replacement [826 ] 826 +MM Transient_GETX [0 ] 0 +MM Transient_Local_GETX [0 ] 0 +MM Transient_GETS [0 ] 0 +MM Transient_Local_GETS [0 ] 0 +MM Persistent_GETX [0 ] 0 +MM Persistent_GETS [0 ] 0 +MM Own_Lock_or_Unlock [27 ] 27 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L1_Replacement 2958 -M_W Transient_GETX 0 <-- -M_W Transient_Local_GETX 0 <-- -M_W Transient_GETS 0 <-- -M_W Transient_Local_GETS 0 <-- -M_W Persistent_GETX 0 <-- -M_W Persistent_GETS 0 <-- -M_W Own_Lock_or_Unlock 2 -M_W Use_TimeoutStarverX 0 <-- -M_W Use_TimeoutStarverS 0 <-- -M_W Use_TimeoutNoStarvers 86 +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [1 ] 1 +M_W Atomic [0 ] 0 +M_W L1_Replacement [1338 ] 1338 +M_W Transient_GETX [0 ] 0 +M_W Transient_Local_GETX [0 ] 0 +M_W Transient_GETS [0 ] 0 +M_W Transient_Local_GETS [0 ] 0 +M_W Persistent_GETX [0 ] 0 +M_W Persistent_GETS [0 ] 0 +M_W Own_Lock_or_Unlock [1 ] 1 +M_W Use_TimeoutStarverX [0 ] 0 +M_W Use_TimeoutStarverS [0 ] 0 +M_W Use_TimeoutNoStarvers [85 ] 85 +M_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 11 -MM_W L1_Replacement 29196 -MM_W Transient_GETX 0 <-- -MM_W Transient_Local_GETX 0 <-- -MM_W Transient_GETS 0 <-- -MM_W Transient_Local_GETS 0 <-- -MM_W Persistent_GETX 0 <-- -MM_W Persistent_GETS 0 <-- -MM_W Own_Lock_or_Unlock 33 -MM_W Use_TimeoutStarverX 0 <-- -MM_W Use_TimeoutStarverS 0 <-- -MM_W Use_TimeoutNoStarvers 781 +MM_W Load [1 ] 1 +MM_W Ifetch [0 ] 0 +MM_W Store [9 ] 9 +MM_W Atomic [0 ] 0 +MM_W L1_Replacement [30069 ] 30069 +MM_W Transient_GETX [0 ] 0 +MM_W Transient_Local_GETX [0 ] 0 +MM_W Transient_GETS [0 ] 0 +MM_W Transient_Local_GETS [0 ] 0 +MM_W Persistent_GETX [0 ] 0 +MM_W Persistent_GETS [0 ] 0 +MM_W Own_Lock_or_Unlock [26 ] 26 +MM_W Use_TimeoutStarverX [0 ] 0 +MM_W Use_TimeoutStarverS [0 ] 0 +MM_W Use_TimeoutNoStarvers [827 ] 827 +MM_W Use_TimeoutNoStarvers_NoMig [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L1_Replacement 329936 -IM Data_Shared 0 <-- -IM Data_Owner 0 <-- -IM Data_All_Tokens 780 -IM Ack 0 <-- -IM Transient_GETX 0 <-- -IM Transient_Local_GETX 0 <-- -IM Transient_GETS 0 <-- -IM Transient_Local_GETS 0 <-- -IM Transient_GETS_Last_Token 0 <-- -IM Transient_Local_GETS_Last_Token 0 <-- -IM Persistent_GETX 0 <-- -IM Persistent_GETS 0 <-- -IM Own_Lock_or_Unlock 112 -IM Request_Timeout 465 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM Atomic [0 ] 0 +IM L1_Replacement [341249 ] 341249 +IM Data_Shared [0 ] 0 +IM Data_Owner [2 ] 2 +IM Data_All_Tokens [823 ] 823 +IM Ack [2 ] 2 +IM Transient_GETX [0 ] 0 +IM Transient_Local_GETX [0 ] 0 +IM Transient_GETS [0 ] 0 +IM Transient_Local_GETS [0 ] 0 +IM Transient_GETS_Last_Token [0 ] 0 +IM Transient_Local_GETS_Last_Token [0 ] 0 +IM Persistent_GETX [0 ] 0 +IM Persistent_GETS [0 ] 0 +IM Persistent_GETS_Last_Token [0 ] 0 +IM Own_Lock_or_Unlock [124 ] 124 +IM Request_Timeout [608 ] 608 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L1_Replacement 0 <-- -SM Data_Shared 0 <-- -SM Data_Owner 0 <-- -SM Data_All_Tokens 1 -SM Ack 0 <-- -SM Transient_GETX 0 <-- -SM Transient_Local_GETX 0 <-- -SM Transient_GETS 0 <-- -SM Transient_Local_GETS 0 <-- -SM Transient_GETS_Last_Token 0 <-- -SM Transient_Local_GETS_Last_Token 0 <-- -SM Persistent_GETX 0 <-- -SM Persistent_GETS 0 <-- -SM Own_Lock_or_Unlock 0 <-- -SM Request_Timeout 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM Atomic [0 ] 0 +SM L1_Replacement [0 ] 0 +SM Data_Shared [0 ] 0 +SM Data_Owner [0 ] 0 +SM Data_All_Tokens [1 ] 1 +SM Ack [0 ] 0 +SM Transient_GETX [0 ] 0 +SM Transient_Local_GETX [0 ] 0 +SM Transient_GETS [0 ] 0 +SM Transient_Local_GETS [0 ] 0 +SM Transient_GETS_Last_Token [0 ] 0 +SM Transient_Local_GETS_Last_Token [0 ] 0 +SM Persistent_GETX [0 ] 0 +SM Persistent_GETS [0 ] 0 +SM Persistent_GETS_Last_Token [0 ] 0 +SM Own_Lock_or_Unlock [0 ] 0 +SM Request_Timeout [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L1_Replacement 0 <-- -OM Data_Shared 0 <-- -OM Data_All_Tokens 0 <-- -OM Ack 0 <-- -OM Ack_All_Tokens 0 <-- -OM Transient_GETX 0 <-- -OM Transient_Local_GETX 0 <-- -OM Transient_GETS 0 <-- -OM Transient_Local_GETS 0 <-- -OM Transient_GETS_Last_Token 0 <-- -OM Transient_Local_GETS_Last_Token 0 <-- -OM Persistent_GETX 0 <-- -OM Persistent_GETS 0 <-- -OM Own_Lock_or_Unlock 0 <-- -OM Request_Timeout 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM Atomic [0 ] 0 +OM L1_Replacement [0 ] 0 +OM Data_Shared [0 ] 0 +OM Data_All_Tokens [0 ] 0 +OM Ack [0 ] 0 +OM Ack_All_Tokens [2 ] 2 +OM Transient_GETX [0 ] 0 +OM Transient_Local_GETX [0 ] 0 +OM Transient_GETS [0 ] 0 +OM Transient_Local_GETS [0 ] 0 +OM Transient_GETS_Last_Token [0 ] 0 +OM Transient_Local_GETS_Last_Token [0 ] 0 +OM Persistent_GETX [0 ] 0 +OM Persistent_GETS [0 ] 0 +OM Persistent_GETS_Last_Token [0 ] 0 +OM Own_Lock_or_Unlock [1 ] 1 +OM Request_Timeout [1 ] 1 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L1_Replacement 32044 -IS Data_Shared 1 -IS Data_Owner 0 <-- -IS Data_All_Tokens 87 -IS Ack 0 <-- -IS Transient_GETX 0 <-- -IS Transient_Local_GETX 0 <-- -IS Transient_GETS 0 <-- -IS Transient_Local_GETS 0 <-- -IS Transient_GETS_Last_Token 0 <-- -IS Transient_Local_GETS_Last_Token 0 <-- -IS Persistent_GETX 0 <-- -IS Persistent_GETS 0 <-- -IS Own_Lock_or_Unlock 9 -IS Request_Timeout 80 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS Atomic [0 ] 0 +IS L1_Replacement [14719 ] 14719 +IS Data_Shared [9 ] 9 +IS Data_Owner [0 ] 0 +IS Data_All_Tokens [87 ] 87 +IS Ack [0 ] 0 +IS Transient_GETX [0 ] 0 +IS Transient_Local_GETX [0 ] 0 +IS Transient_GETS [0 ] 0 +IS Transient_Local_GETS [0 ] 0 +IS Transient_GETS_Last_Token [0 ] 0 +IS Transient_Local_GETS_Last_Token [0 ] 0 +IS Persistent_GETX [0 ] 0 +IS Persistent_GETS [0 ] 0 +IS Persistent_GETS_Last_Token [0 ] 0 +IS Own_Lock_or_Unlock [16 ] 16 +IS Request_Timeout [65 ] 65 -I_L Load 0 <-- -I_L Ifetch 0 <-- -I_L Store 0 <-- -I_L L1_Replacement 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_Local_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_Local_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L Transient_Local_GETS_Last_Token 0 <-- -I_L Persistent_GETX 0 <-- -I_L Persistent_GETS 0 <-- -I_L Own_Lock_or_Unlock 0 <-- +I_L Load [0 ] 0 +I_L Ifetch [0 ] 0 +I_L Store [0 ] 0 +I_L Atomic [0 ] 0 +I_L L1_Replacement [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_Local_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_Local_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L Transient_Local_GETS_Last_Token [0 ] 0 +I_L Persistent_GETX [0 ] 0 +I_L Persistent_GETS [0 ] 0 +I_L Persistent_GETS_Last_Token [0 ] 0 +I_L Own_Lock_or_Unlock [0 ] 0 -S_L Load 0 <-- -S_L Ifetch 0 <-- -S_L Store 0 <-- -S_L L1_Replacement 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_Local_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_Local_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L Transient_Local_GETS_Last_Token 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L Load [0 ] 0 +S_L Ifetch [0 ] 0 +S_L Store [0 ] 0 +S_L Atomic [0 ] 0 +S_L L1_Replacement [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_Local_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_Local_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L Transient_Local_GETS_Last_Token [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -IM_L Load 0 <-- -IM_L Ifetch 0 <-- -IM_L Store 0 <-- -IM_L L1_Replacement 0 <-- -IM_L Data_Shared 0 <-- -IM_L Data_Owner 0 <-- -IM_L Data_All_Tokens 0 <-- -IM_L Ack 0 <-- -IM_L Transient_GETX 0 <-- -IM_L Transient_Local_GETX 0 <-- -IM_L Transient_GETS 0 <-- -IM_L Transient_Local_GETS 0 <-- -IM_L Transient_GETS_Last_Token 0 <-- -IM_L Transient_Local_GETS_Last_Token 0 <-- -IM_L Persistent_GETX 0 <-- -IM_L Persistent_GETS 0 <-- -IM_L Own_Lock_or_Unlock 0 <-- -IM_L Request_Timeout 0 <-- +IM_L Load [0 ] 0 +IM_L Ifetch [0 ] 0 +IM_L Store [0 ] 0 +IM_L Atomic [0 ] 0 +IM_L L1_Replacement [0 ] 0 +IM_L Data_Shared [0 ] 0 +IM_L Data_Owner [0 ] 0 +IM_L Data_All_Tokens [0 ] 0 +IM_L Ack [0 ] 0 +IM_L Transient_GETX [0 ] 0 +IM_L Transient_Local_GETX [0 ] 0 +IM_L Transient_GETS [0 ] 0 +IM_L Transient_Local_GETS [0 ] 0 +IM_L Transient_GETS_Last_Token [0 ] 0 +IM_L Transient_Local_GETS_Last_Token [0 ] 0 +IM_L Persistent_GETX [0 ] 0 +IM_L Persistent_GETS [0 ] 0 +IM_L Own_Lock_or_Unlock [0 ] 0 +IM_L Request_Timeout [0 ] 0 -SM_L Load 0 <-- -SM_L Ifetch 0 <-- -SM_L Store 0 <-- -SM_L L1_Replacement 0 <-- -SM_L Data_Shared 0 <-- -SM_L Data_Owner 0 <-- -SM_L Data_All_Tokens 0 <-- -SM_L Ack 0 <-- -SM_L Transient_GETX 0 <-- -SM_L Transient_Local_GETX 0 <-- -SM_L Transient_GETS 0 <-- -SM_L Transient_Local_GETS 0 <-- -SM_L Transient_GETS_Last_Token 0 <-- -SM_L Transient_Local_GETS_Last_Token 0 <-- -SM_L Persistent_GETX 0 <-- -SM_L Persistent_GETS 0 <-- -SM_L Own_Lock_or_Unlock 0 <-- -SM_L Request_Timeout 0 <-- +SM_L Load [0 ] 0 +SM_L Ifetch [0 ] 0 +SM_L Store [0 ] 0 +SM_L Atomic [0 ] 0 +SM_L L1_Replacement [0 ] 0 +SM_L Data_Shared [0 ] 0 +SM_L Data_Owner [0 ] 0 +SM_L Data_All_Tokens [0 ] 0 +SM_L Ack [0 ] 0 +SM_L Transient_GETX [0 ] 0 +SM_L Transient_Local_GETX [0 ] 0 +SM_L Transient_GETS [0 ] 0 +SM_L Transient_Local_GETS [0 ] 0 +SM_L Transient_GETS_Last_Token [0 ] 0 +SM_L Transient_Local_GETS_Last_Token [0 ] 0 +SM_L Persistent_GETX [0 ] 0 +SM_L Persistent_GETS [0 ] 0 +SM_L Persistent_GETS_Last_Token [0 ] 0 +SM_L Own_Lock_or_Unlock [0 ] 0 +SM_L Request_Timeout [0 ] 0 -IS_L Load 0 <-- -IS_L Ifetch 0 <-- -IS_L Store 0 <-- -IS_L L1_Replacement 0 <-- -IS_L Data_Shared 0 <-- -IS_L Data_Owner 0 <-- -IS_L Data_All_Tokens 0 <-- -IS_L Ack 0 <-- -IS_L Transient_GETX 0 <-- -IS_L Transient_Local_GETX 0 <-- -IS_L Transient_GETS 0 <-- -IS_L Transient_Local_GETS 0 <-- -IS_L Transient_GETS_Last_Token 0 <-- -IS_L Transient_Local_GETS_Last_Token 0 <-- -IS_L Persistent_GETX 0 <-- -IS_L Persistent_GETS 0 <-- -IS_L Own_Lock_or_Unlock 0 <-- -IS_L Request_Timeout 0 <-- +IS_L Load [0 ] 0 +IS_L Ifetch [0 ] 0 +IS_L Store [0 ] 0 +IS_L Atomic [0 ] 0 +IS_L L1_Replacement [0 ] 0 +IS_L Data_Shared [0 ] 0 +IS_L Data_Owner [0 ] 0 +IS_L Data_All_Tokens [0 ] 0 +IS_L Ack [0 ] 0 +IS_L Transient_GETX [0 ] 0 +IS_L Transient_Local_GETX [0 ] 0 +IS_L Transient_GETS [0 ] 0 +IS_L Transient_Local_GETS [0 ] 0 +IS_L Transient_GETS_Last_Token [0 ] 0 +IS_L Transient_Local_GETS_Last_Token [0 ] 0 +IS_L Persistent_GETX [0 ] 0 +IS_L Persistent_GETS [0 ] 0 +IS_L Own_Lock_or_Unlock [0 ] 0 +IS_L Request_Timeout [0 ] 0 -Cache Stats: system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_demand_misses: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_total_hw_prefetches: 0 +Cache Stats: system.l2_cntrl0.L2cacheMemory + system.l2_cntrl0.L2cacheMemory_total_misses: 906 + system.l2_cntrl0.L2cacheMemory_total_demand_misses: 906 + system.l2_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l2_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links1.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l2_cntrl0.L2cacheMemory_request_type_GETS: 9.60265% + system.l2_cntrl0.L2cacheMemory_request_type_GETX: 90.3974% - --- L2Cache 0 --- + system.l2_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 906 100% + + --- L2Cache --- - Event Counts - -L1_GETS 88 -L1_GETS_Last_Token 0 -L1_GETX 782 -L1_INV 0 -Transient_GETX 0 -Transient_GETS 0 -Transient_GETS_Last_Token 0 -L2_Replacement 781 -Writeback_Tokens 0 -Writeback_Shared_Data 0 -Writeback_All_Tokens 866 -Writeback_Owned 0 -Data_Shared 0 -Data_Owner 0 -Data_All_Tokens 0 -Ack 0 -Ack_All_Tokens 0 -Persistent_GETX 161 -Persistent_GETS 12 -Own_Lock_or_Unlock 173 +L1_GETS [95 ] 95 +L1_GETS_Last_Token [1 ] 1 +L1_GETX [826 ] 826 +L1_INV [0 ] 0 +Transient_GETX [0 ] 0 +Transient_GETS [0 ] 0 +Transient_GETS_Last_Token [0 ] 0 +L2_Replacement [857 ] 857 +Writeback_Tokens [0 ] 0 +Writeback_Shared_Data [8 ] 8 +Writeback_All_Tokens [908 ] 908 +Writeback_Owned [0 ] 0 +Data_Shared [0 ] 0 +Data_Owner [0 ] 0 +Data_All_Tokens [0 ] 0 +Ack [0 ] 0 +Ack_All_Tokens [0 ] 0 +Persistent_GETX [173 ] 173 +Persistent_GETS [18 ] 18 +Persistent_GETS_Last_Token [0 ] 0 +Own_Lock_or_Unlock [191 ] 191 - Transitions - -NP L1_GETS 87 -NP L1_GETX 756 -NP L1_INV 0 <-- -NP Transient_GETX 0 <-- -NP Transient_GETS 0 <-- -NP Writeback_Tokens 0 <-- -NP Writeback_Shared_Data 0 <-- -NP Writeback_All_Tokens 783 -NP Writeback_Owned 0 <-- -NP Data_Shared 0 <-- -NP Data_Owner 0 <-- -NP Data_All_Tokens 0 <-- -NP Ack 0 <-- -NP Persistent_GETX 0 <-- -NP Persistent_GETS 0 <-- -NP Own_Lock_or_Unlock 145 +NP L1_GETS [87 ] 87 +NP L1_GETX [816 ] 816 +NP L1_INV [0 ] 0 +NP Transient_GETX [0 ] 0 +NP Transient_GETS [0 ] 0 +NP Writeback_Tokens [0 ] 0 +NP Writeback_Shared_Data [7 ] 7 +NP Writeback_All_Tokens [852 ] 852 +NP Writeback_Owned [0 ] 0 +NP Data_Shared [0 ] 0 +NP Data_Owner [0 ] 0 +NP Data_All_Tokens [0 ] 0 +NP Ack [0 ] 0 +NP Persistent_GETX [0 ] 0 +NP Persistent_GETS [0 ] 0 +NP Persistent_GETS_Last_Token [0 ] 0 +NP Own_Lock_or_Unlock [168 ] 168 -I L1_GETS 0 <-- -I L1_GETS_Last_Token 0 <-- -I L1_GETX 0 <-- -I L1_INV 0 <-- -I Transient_GETX 0 <-- -I Transient_GETS 0 <-- -I Transient_GETS_Last_Token 0 <-- -I L2_Replacement 30 -I Writeback_Tokens 0 <-- -I Writeback_Shared_Data 0 <-- -I Writeback_All_Tokens 24 -I Writeback_Owned 0 <-- -I Data_Shared 0 <-- -I Data_Owner 0 <-- -I Data_All_Tokens 0 <-- -I Ack 0 <-- -I Persistent_GETX 0 <-- -I Persistent_GETS 0 <-- -I Own_Lock_or_Unlock 0 <-- +I L1_GETS [0 ] 0 +I L1_GETS_Last_Token [0 ] 0 +I L1_GETX [0 ] 0 +I L1_INV [0 ] 0 +I Transient_GETX [0 ] 0 +I Transient_GETS [0 ] 0 +I Transient_GETS_Last_Token [0 ] 0 +I L2_Replacement [28 ] 28 +I Writeback_Tokens [0 ] 0 +I Writeback_Shared_Data [1 ] 1 +I Writeback_All_Tokens [5 ] 5 +I Writeback_Owned [0 ] 0 +I Data_Shared [0 ] 0 +I Data_Owner [0 ] 0 +I Data_All_Tokens [0 ] 0 +I Ack [0 ] 0 +I Persistent_GETX [0 ] 0 +I Persistent_GETS [0 ] 0 +I Persistent_GETS_Last_Token [0 ] 0 +I Own_Lock_or_Unlock [0 ] 0 -S L1_GETS 0 <-- -S L1_GETS_Last_Token 0 <-- -S L1_GETX 0 <-- -S L1_INV 0 <-- -S Transient_GETX 0 <-- -S Transient_GETS 0 <-- -S Transient_GETS_Last_Token 0 <-- -S L2_Replacement 0 <-- -S Writeback_Tokens 0 <-- -S Writeback_Shared_Data 0 <-- -S Writeback_All_Tokens 0 <-- -S Writeback_Owned 0 <-- -S Data_Shared 0 <-- -S Data_Owner 0 <-- -S Data_All_Tokens 0 <-- -S Ack 0 <-- -S Persistent_GETX 0 <-- -S Persistent_GETS 0 <-- -S Own_Lock_or_Unlock 0 <-- +S L1_GETS [0 ] 0 +S L1_GETS_Last_Token [1 ] 1 +S L1_GETX [2 ] 2 +S L1_INV [0 ] 0 +S Transient_GETX [0 ] 0 +S Transient_GETS [0 ] 0 +S Transient_GETS_Last_Token [0 ] 0 +S L2_Replacement [5 ] 5 +S Writeback_Tokens [0 ] 0 +S Writeback_Shared_Data [0 ] 0 +S Writeback_All_Tokens [0 ] 0 +S Writeback_Owned [0 ] 0 +S Data_Shared [0 ] 0 +S Data_Owner [0 ] 0 +S Data_All_Tokens [0 ] 0 +S Ack [0 ] 0 +S Persistent_GETX [0 ] 0 +S Persistent_GETS [0 ] 0 +S Persistent_GETS_Last_Token [0 ] 0 +S Own_Lock_or_Unlock [0 ] 0 -O L1_GETS 0 <-- -O L1_GETS_Last_Token 0 <-- -O L1_GETX 1 -O L1_INV 0 <-- -O Transient_GETX 0 <-- -O Transient_GETS 0 <-- -O Transient_GETS_Last_Token 0 <-- -O L2_Replacement 0 <-- -O Writeback_Tokens 0 <-- -O Writeback_Shared_Data 0 <-- -O Writeback_All_Tokens 0 <-- -O Data_Shared 0 <-- -O Data_All_Tokens 0 <-- -O Ack 0 <-- -O Ack_All_Tokens 0 <-- -O Persistent_GETX 0 <-- -O Persistent_GETS 0 <-- -O Own_Lock_or_Unlock 0 <-- +O L1_GETS [0 ] 0 +O L1_GETS_Last_Token [0 ] 0 +O L1_GETX [1 ] 1 +O L1_INV [0 ] 0 +O Transient_GETX [0 ] 0 +O Transient_GETS [0 ] 0 +O Transient_GETS_Last_Token [0 ] 0 +O L2_Replacement [7 ] 7 +O Writeback_Tokens [0 ] 0 +O Writeback_Shared_Data [0 ] 0 +O Writeback_All_Tokens [0 ] 0 +O Data_Shared [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Ack [0 ] 0 +O Ack_All_Tokens [0 ] 0 +O Persistent_GETX [0 ] 0 +O Persistent_GETS [0 ] 0 +O Persistent_GETS_Last_Token [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 -M L1_GETS 1 -M L1_GETX 25 -M L1_INV 0 <-- -M Transient_GETX 0 <-- -M Transient_GETS 0 <-- -M L2_Replacement 751 -M Persistent_GETX 26 -M Persistent_GETS 2 -M Own_Lock_or_Unlock 0 <-- +M L1_GETS [8 ] 8 +M L1_GETX [7 ] 7 +M L1_INV [0 ] 0 +M Transient_GETX [0 ] 0 +M Transient_GETS [0 ] 0 +M L2_Replacement [814 ] 814 +M Persistent_GETX [26 ] 26 +M Persistent_GETS [0 ] 0 +M Own_Lock_or_Unlock [0 ] 0 -I_L L1_GETS 0 <-- -I_L L1_GETX 0 <-- -I_L L1_INV 0 <-- -I_L Transient_GETX 0 <-- -I_L Transient_GETS 0 <-- -I_L Transient_GETS_Last_Token 0 <-- -I_L L2_Replacement 0 <-- -I_L Writeback_Tokens 0 <-- -I_L Writeback_Shared_Data 0 <-- -I_L Writeback_All_Tokens 59 -I_L Writeback_Owned 0 <-- -I_L Data_Shared 0 <-- -I_L Data_Owner 0 <-- -I_L Data_All_Tokens 0 <-- -I_L Ack 0 <-- -I_L Persistent_GETX 135 -I_L Persistent_GETS 10 -I_L Own_Lock_or_Unlock 28 +I_L L1_GETS [0 ] 0 +I_L L1_GETX [0 ] 0 +I_L L1_INV [0 ] 0 +I_L Transient_GETX [0 ] 0 +I_L Transient_GETS [0 ] 0 +I_L Transient_GETS_Last_Token [0 ] 0 +I_L L2_Replacement [3 ] 3 +I_L Writeback_Tokens [0 ] 0 +I_L Writeback_Shared_Data [0 ] 0 +I_L Writeback_All_Tokens [51 ] 51 +I_L Writeback_Owned [0 ] 0 +I_L Data_Shared [0 ] 0 +I_L Data_Owner [0 ] 0 +I_L Data_All_Tokens [0 ] 0 +I_L Ack [0 ] 0 +I_L Persistent_GETX [147 ] 147 +I_L Persistent_GETS [18 ] 18 +I_L Own_Lock_or_Unlock [23 ] 23 -S_L L1_GETS 0 <-- -S_L L1_GETS_Last_Token 0 <-- -S_L L1_GETX 0 <-- -S_L L1_INV 0 <-- -S_L Transient_GETX 0 <-- -S_L Transient_GETS 0 <-- -S_L Transient_GETS_Last_Token 0 <-- -S_L L2_Replacement 0 <-- -S_L Writeback_Tokens 0 <-- -S_L Writeback_Shared_Data 0 <-- -S_L Writeback_All_Tokens 0 <-- -S_L Writeback_Owned 0 <-- -S_L Data_Shared 0 <-- -S_L Data_Owner 0 <-- -S_L Data_All_Tokens 0 <-- -S_L Ack 0 <-- -S_L Persistent_GETX 0 <-- -S_L Persistent_GETS 0 <-- -S_L Own_Lock_or_Unlock 0 <-- +S_L L1_GETS [0 ] 0 +S_L L1_GETS_Last_Token [0 ] 0 +S_L L1_GETX [0 ] 0 +S_L L1_INV [0 ] 0 +S_L Transient_GETX [0 ] 0 +S_L Transient_GETS [0 ] 0 +S_L Transient_GETS_Last_Token [0 ] 0 +S_L L2_Replacement [0 ] 0 +S_L Writeback_Tokens [0 ] 0 +S_L Writeback_Shared_Data [0 ] 0 +S_L Writeback_All_Tokens [0 ] 0 +S_L Writeback_Owned [0 ] 0 +S_L Data_Shared [0 ] 0 +S_L Data_Owner [0 ] 0 +S_L Data_All_Tokens [0 ] 0 +S_L Ack [0 ] 0 +S_L Persistent_GETX [0 ] 0 +S_L Persistent_GETS [0 ] 0 +S_L Persistent_GETS_Last_Token [0 ] 0 +S_L Own_Lock_or_Unlock [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links2.ext_node.memBuffer: - memory_total_requests: 1599 - memory_reads: 842 - memory_writes: 756 - memory_refreshes: 574 - memory_total_request_delays: 1024 - memory_delays_per_request: 0.6404 - memory_delays_in_input_queue: 172 - memory_delays_behind_head_of_bank_queue: 2 - memory_delays_stalled_at_head_of_bank_queue: 850 - memory_stalls_for_bank_busy: 171 +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1720 + memory_reads: 902 + memory_writes: 818 + memory_refreshes: 571 + memory_total_request_delays: 1302 + memory_delays_per_request: 0.756977 + memory_delays_in_input_queue: 202 + memory_delays_behind_head_of_bank_queue: 0 + memory_delays_stalled_at_head_of_bank_queue: 1100 + memory_stalls_for_bank_busy: 220 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 68 - memory_stalls_for_bus: 354 + memory_stalls_for_arbitration: 97 + memory_stalls_for_bus: 424 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 184 - memory_stalls_for_read_read_turnaround: 73 - accesses_per_bank: 49 42 55 87 81 71 69 52 62 53 36 48 32 44 42 54 55 42 39 43 42 41 41 55 58 45 50 41 45 33 49 43 + memory_stalls_for_read_write_turnaround: 268 + memory_stalls_for_read_read_turnaround: 91 + accesses_per_bank: 61 42 48 69 122 69 58 56 55 51 54 41 43 47 55 55 46 45 53 50 43 51 55 52 43 56 60 54 49 40 40 57 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 771 -GETS 89 -Lockdown 173 -Unlockdown 173 -Own_Lock_or_Unlock 0 -Data_Owner 0 -Data_All_Tokens 766 -Ack_Owner 0 -Ack_Owner_All_Tokens 81 -Tokens 0 -Ack_All_Tokens 0 -Request_Timeout 0 -Memory_Data 842 -Memory_Ack 755 -DMA_READ 0 -DMA_WRITE 0 -DMA_WRITE_All_Tokens 0 +GETX [828 ] 828 +GETS [87 ] 87 +Lockdown [191 ] 191 +Unlockdown [191 ] 191 +Own_Lock_or_Unlock [0 ] 0 +Own_Lock_or_Unlock_Tokens [0 ] 0 +Data_Owner [7 ] 7 +Data_All_Tokens [825 ] 825 +Ack_Owner [0 ] 0 +Ack_Owner_All_Tokens [76 ] 76 +Tokens [2 ] 2 +Ack_All_Tokens [3 ] 3 +Request_Timeout [0 ] 0 +Memory_Data [902 ] 902 +Memory_Ack [817 ] 817 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +DMA_WRITE_All_Tokens [0 ] 0 - Transitions - -O GETX 751 -O GETS 87 -O Lockdown 5 -O Own_Lock_or_Unlock 0 <-- -O Data_Owner 0 <-- -O Data_All_Tokens 0 <-- -O Tokens 0 <-- -O Ack_All_Tokens 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- -O DMA_WRITE_All_Tokens 0 <-- +O GETX [811 ] 811 +O GETS [83 ] 83 +O Lockdown [6 ] 6 +O Unlockdown [0 ] 0 +O Own_Lock_or_Unlock [0 ] 0 +O Own_Lock_or_Unlock_Tokens [0 ] 0 +O Data_Owner [0 ] 0 +O Data_All_Tokens [0 ] 0 +O Tokens [0 ] 0 +O Ack_All_Tokens [3 ] 3 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 +O DMA_WRITE_All_Tokens [0 ] 0 -NO GETX 4 -NO GETS 0 <-- -NO Lockdown 151 -NO Own_Lock_or_Unlock 0 <-- -NO Data_Owner 0 <-- -NO Data_All_Tokens 756 -NO Ack_Owner 0 <-- -NO Ack_Owner_All_Tokens 81 -NO Tokens 0 <-- -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NO GETX [8 ] 8 +NO GETS [4 ] 4 +NO Lockdown [168 ] 168 +NO Unlockdown [0 ] 0 +NO Own_Lock_or_Unlock [0 ] 0 +NO Own_Lock_or_Unlock_Tokens [0 ] 0 +NO Data_Owner [7 ] 7 +NO Data_All_Tokens [811 ] 811 +NO Ack_Owner [0 ] 0 +NO Ack_Owner_All_Tokens [76 ] 76 +NO Tokens [1 ] 1 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -L GETX 2 -L GETS 0 <-- -L Lockdown 0 <-- -L Unlockdown 172 -L Own_Lock_or_Unlock 0 <-- -L Data_Owner 0 <-- -L Data_All_Tokens 10 -L Ack_Owner 0 <-- -L Ack_Owner_All_Tokens 0 <-- -L Tokens 0 <-- -L DMA_READ 0 <-- -L DMA_WRITE 0 <-- +L GETX [0 ] 0 +L GETS [0 ] 0 +L Lockdown [0 ] 0 +L Unlockdown [189 ] 189 +L Own_Lock_or_Unlock [0 ] 0 +L Own_Lock_or_Unlock_Tokens [0 ] 0 +L Data_Owner [0 ] 0 +L Data_All_Tokens [14 ] 14 +L Ack_Owner [0 ] 0 +L Ack_Owner_All_Tokens [0 ] 0 +L Tokens [1 ] 1 +L DMA_READ [0 ] 0 +L DMA_WRITE [0 ] 0 +L DMA_WRITE_All_Tokens [0 ] 0 -O_W GETX 4 -O_W GETS 2 -O_W Lockdown 1 -O_W Unlockdown 0 <-- -O_W Own_Lock_or_Unlock 0 <-- -O_W Data_Owner 0 <-- -O_W Ack_Owner 0 <-- -O_W Tokens 0 <-- -O_W Ack_All_Tokens 0 <-- -O_W Memory_Data 0 <-- -O_W Memory_Ack 755 -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- +O_W GETX [9 ] 9 +O_W GETS [0 ] 0 +O_W Lockdown [3 ] 3 +O_W Unlockdown [0 ] 0 +O_W Own_Lock_or_Unlock [0 ] 0 +O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_W Data_Owner [0 ] 0 +O_W Data_All_Tokens [0 ] 0 +O_W Ack_Owner [0 ] 0 +O_W Tokens [0 ] 0 +O_W Ack_All_Tokens [0 ] 0 +O_W Memory_Data [1 ] 1 +O_W Memory_Ack [815 ] 815 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W DMA_WRITE_All_Tokens [0 ] 0 -L_O_W GETX 10 -L_O_W GETS 0 <-- -L_O_W Lockdown 0 <-- -L_O_W Unlockdown 1 -L_O_W Own_Lock_or_Unlock 0 <-- -L_O_W Data_Owner 0 <-- -L_O_W Ack_Owner 0 <-- -L_O_W Tokens 0 <-- -L_O_W Ack_All_Tokens 0 <-- -L_O_W Memory_Data 5 -L_O_W Memory_Ack 0 <-- -L_O_W DMA_READ 0 <-- -L_O_W DMA_WRITE 0 <-- +L_O_W GETX [0 ] 0 +L_O_W GETS [0 ] 0 +L_O_W Lockdown [0 ] 0 +L_O_W Unlockdown [2 ] 2 +L_O_W Own_Lock_or_Unlock [0 ] 0 +L_O_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_O_W Data_Owner [0 ] 0 +L_O_W Data_All_Tokens [0 ] 0 +L_O_W Ack_Owner [0 ] 0 +L_O_W Tokens [0 ] 0 +L_O_W Ack_All_Tokens [0 ] 0 +L_O_W Memory_Data [7 ] 7 +L_O_W Memory_Ack [2 ] 2 +L_O_W DMA_READ [0 ] 0 +L_O_W DMA_WRITE [0 ] 0 +L_O_W DMA_WRITE_All_Tokens [0 ] 0 -L_NO_W GETX 0 <-- -L_NO_W GETS 0 <-- -L_NO_W Lockdown 0 <-- -L_NO_W Unlockdown 0 <-- -L_NO_W Own_Lock_or_Unlock 0 <-- -L_NO_W Data_Owner 0 <-- -L_NO_W Ack_Owner 0 <-- -L_NO_W Tokens 0 <-- -L_NO_W Ack_All_Tokens 0 <-- -L_NO_W Memory_Data 16 -L_NO_W DMA_READ 0 <-- -L_NO_W DMA_WRITE 0 <-- +L_NO_W GETX [0 ] 0 +L_NO_W GETS [0 ] 0 +L_NO_W Lockdown [0 ] 0 +L_NO_W Unlockdown [0 ] 0 +L_NO_W Own_Lock_or_Unlock [0 ] 0 +L_NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +L_NO_W Data_Owner [0 ] 0 +L_NO_W Data_All_Tokens [0 ] 0 +L_NO_W Ack_Owner [0 ] 0 +L_NO_W Tokens [0 ] 0 +L_NO_W Ack_All_Tokens [0 ] 0 +L_NO_W Memory_Data [14 ] 14 +L_NO_W DMA_READ [0 ] 0 +L_NO_W DMA_WRITE [0 ] 0 +L_NO_W DMA_WRITE_All_Tokens [0 ] 0 -DR_L_W GETX 0 <-- -DR_L_W GETS 0 <-- -DR_L_W Lockdown 0 <-- -DR_L_W Unlockdown 0 <-- -DR_L_W Own_Lock_or_Unlock 0 <-- -DR_L_W Data_Owner 0 <-- -DR_L_W Ack_Owner 0 <-- -DR_L_W Tokens 0 <-- -DR_L_W Ack_All_Tokens 0 <-- -DR_L_W Request_Timeout 0 <-- -DR_L_W Memory_Data 0 <-- -DR_L_W DMA_READ 0 <-- -DR_L_W DMA_WRITE 0 <-- +DR_L_W GETX [0 ] 0 +DR_L_W GETS [0 ] 0 +DR_L_W Lockdown [0 ] 0 +DR_L_W Unlockdown [0 ] 0 +DR_L_W Own_Lock_or_Unlock [0 ] 0 +DR_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L_W Data_Owner [0 ] 0 +DR_L_W Data_All_Tokens [0 ] 0 +DR_L_W Ack_Owner [0 ] 0 +DR_L_W Tokens [0 ] 0 +DR_L_W Ack_All_Tokens [0 ] 0 +DR_L_W Request_Timeout [0 ] 0 +DR_L_W Memory_Data [0 ] 0 +DR_L_W DMA_READ [0 ] 0 +DR_L_W DMA_WRITE [0 ] 0 +DR_L_W DMA_WRITE_All_Tokens [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W Lockdown 16 -NO_W Unlockdown 0 <-- -NO_W Own_Lock_or_Unlock 0 <-- -NO_W Data_Owner 0 <-- -NO_W Ack_Owner 0 <-- -NO_W Tokens 0 <-- -NO_W Ack_All_Tokens 0 <-- -NO_W Memory_Data 821 -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- +DW_L_W GETX [0 ] 0 +DW_L_W GETS [0 ] 0 +DW_L_W Lockdown [0 ] 0 +DW_L_W Unlockdown [0 ] 0 +DW_L_W Own_Lock_or_Unlock [0 ] 0 +DW_L_W Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L_W Data_Owner [0 ] 0 +DW_L_W Data_All_Tokens [0 ] 0 +DW_L_W Ack_Owner [0 ] 0 +DW_L_W Tokens [0 ] 0 +DW_L_W Ack_All_Tokens [0 ] 0 +DW_L_W Request_Timeout [0 ] 0 +DW_L_W Memory_Ack [0 ] 0 +DW_L_W DMA_READ [0 ] 0 +DW_L_W DMA_WRITE [0 ] 0 +DW_L_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW_W GETX 0 <-- -O_DW_W GETS 0 <-- -O_DW_W Data_Owner 0 <-- -O_DW_W Ack_Owner 0 <-- -O_DW_W Tokens 0 <-- -O_DW_W Ack_All_Tokens 0 <-- -O_DW_W Memory_Ack 0 <-- -O_DW_W DMA_READ 0 <-- -O_DW_W DMA_WRITE 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W Lockdown [14 ] 14 +NO_W Unlockdown [0 ] 0 +NO_W Own_Lock_or_Unlock [0 ] 0 +NO_W Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_W Data_Owner [0 ] 0 +NO_W Data_All_Tokens [0 ] 0 +NO_W Ack_Owner [0 ] 0 +NO_W Tokens [0 ] 0 +NO_W Ack_All_Tokens [0 ] 0 +NO_W Memory_Data [880 ] 880 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W DMA_WRITE_All_Tokens [0 ] 0 -O_DR_W GETX 0 <-- -O_DR_W GETS 0 <-- -O_DR_W Lockdown 0 <-- -O_DR_W Unlockdown 0 <-- -O_DR_W Own_Lock_or_Unlock 0 <-- -O_DR_W Data_Owner 0 <-- -O_DR_W Ack_Owner 0 <-- -O_DR_W Tokens 0 <-- -O_DR_W Ack_All_Tokens 0 <-- -O_DR_W Memory_Data 0 <-- -O_DR_W DMA_READ 0 <-- -O_DR_W DMA_WRITE 0 <-- +O_DW_W GETX [0 ] 0 +O_DW_W GETS [0 ] 0 +O_DW_W Lockdown [0 ] 0 +O_DW_W Unlockdown [0 ] 0 +O_DW_W Own_Lock_or_Unlock [0 ] 0 +O_DW_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW_W Data_Owner [0 ] 0 +O_DW_W Data_All_Tokens [0 ] 0 +O_DW_W Ack_Owner [0 ] 0 +O_DW_W Tokens [0 ] 0 +O_DW_W Ack_All_Tokens [0 ] 0 +O_DW_W Request_Timeout [0 ] 0 +O_DW_W Memory_Ack [0 ] 0 +O_DW_W DMA_READ [0 ] 0 +O_DW_W DMA_WRITE [0 ] 0 +O_DW_W DMA_WRITE_All_Tokens [0 ] 0 -O_DW GETX 0 <-- -O_DW GETS 0 <-- -O_DW Lockdown 0 <-- -O_DW Own_Lock_or_Unlock 0 <-- -O_DW Data_Owner 0 <-- -O_DW Data_All_Tokens 0 <-- -O_DW Ack_Owner 0 <-- -O_DW Ack_Owner_All_Tokens 0 <-- -O_DW Tokens 0 <-- -O_DW Ack_All_Tokens 0 <-- -O_DW DMA_READ 0 <-- -O_DW DMA_WRITE 0 <-- +O_DR_W GETX [0 ] 0 +O_DR_W GETS [0 ] 0 +O_DR_W Lockdown [0 ] 0 +O_DR_W Unlockdown [0 ] 0 +O_DR_W Own_Lock_or_Unlock [0 ] 0 +O_DR_W Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DR_W Data_Owner [0 ] 0 +O_DR_W Data_All_Tokens [0 ] 0 +O_DR_W Ack_Owner [0 ] 0 +O_DR_W Tokens [0 ] 0 +O_DR_W Ack_All_Tokens [0 ] 0 +O_DR_W Request_Timeout [0 ] 0 +O_DR_W Memory_Data [0 ] 0 +O_DR_W DMA_READ [0 ] 0 +O_DR_W DMA_WRITE [0 ] 0 +O_DR_W DMA_WRITE_All_Tokens [0 ] 0 -NO_DW GETX 0 <-- -NO_DW GETS 0 <-- -NO_DW Lockdown 0 <-- -NO_DW Own_Lock_or_Unlock 0 <-- -NO_DW Data_Owner 0 <-- -NO_DW Data_All_Tokens 0 <-- -NO_DW Tokens 0 <-- -NO_DW Request_Timeout 0 <-- -NO_DW DMA_READ 0 <-- -NO_DW DMA_WRITE 0 <-- +O_DW GETX [0 ] 0 +O_DW GETS [0 ] 0 +O_DW Lockdown [0 ] 0 +O_DW Unlockdown [0 ] 0 +O_DW Own_Lock_or_Unlock [0 ] 0 +O_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +O_DW Data_Owner [0 ] 0 +O_DW Data_All_Tokens [0 ] 0 +O_DW Ack_Owner [0 ] 0 +O_DW Ack_Owner_All_Tokens [0 ] 0 +O_DW Tokens [0 ] 0 +O_DW Ack_All_Tokens [0 ] 0 +O_DW Request_Timeout [0 ] 0 +O_DW DMA_READ [0 ] 0 +O_DW DMA_WRITE [0 ] 0 +O_DW DMA_WRITE_All_Tokens [0 ] 0 -NO_DR GETX 0 <-- -NO_DR GETS 0 <-- -NO_DR Lockdown 0 <-- -NO_DR Own_Lock_or_Unlock 0 <-- -NO_DR Data_Owner 0 <-- -NO_DR Data_All_Tokens 0 <-- -NO_DR Tokens 0 <-- -NO_DR Request_Timeout 0 <-- -NO_DR DMA_READ 0 <-- -NO_DR DMA_WRITE 0 <-- +NO_DW GETX [0 ] 0 +NO_DW GETS [0 ] 0 +NO_DW Lockdown [0 ] 0 +NO_DW Unlockdown [0 ] 0 +NO_DW Own_Lock_or_Unlock [0 ] 0 +NO_DW Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DW Data_Owner [0 ] 0 +NO_DW Data_All_Tokens [0 ] 0 +NO_DW Tokens [0 ] 0 +NO_DW Request_Timeout [0 ] 0 +NO_DW DMA_READ [0 ] 0 +NO_DW DMA_WRITE [0 ] 0 +NO_DW DMA_WRITE_All_Tokens [0 ] 0 -DW_L GETX 0 <-- -DW_L GETS 0 <-- -DW_L Lockdown 0 <-- -DW_L Unlockdown 0 <-- -DW_L Own_Lock_or_Unlock 0 <-- -DW_L Data_Owner 0 <-- -DW_L Data_All_Tokens 0 <-- -DW_L Ack_Owner 0 <-- -DW_L Ack_Owner_All_Tokens 0 <-- -DW_L Tokens 0 <-- -DW_L Request_Timeout 0 <-- -DW_L DMA_READ 0 <-- -DW_L DMA_WRITE 0 <-- +NO_DR GETX [0 ] 0 +NO_DR GETS [0 ] 0 +NO_DR Lockdown [0 ] 0 +NO_DR Unlockdown [0 ] 0 +NO_DR Own_Lock_or_Unlock [0 ] 0 +NO_DR Own_Lock_or_Unlock_Tokens [0 ] 0 +NO_DR Data_Owner [0 ] 0 +NO_DR Data_All_Tokens [0 ] 0 +NO_DR Tokens [0 ] 0 +NO_DR Request_Timeout [0 ] 0 +NO_DR DMA_READ [0 ] 0 +NO_DR DMA_WRITE [0 ] 0 +NO_DR DMA_WRITE_All_Tokens [0 ] 0 -DR_L GETX 0 <-- -DR_L GETS 0 <-- -DR_L Lockdown 0 <-- -DR_L Unlockdown 0 <-- -DR_L Own_Lock_or_Unlock 0 <-- -DR_L Data_Owner 0 <-- -DR_L Data_All_Tokens 0 <-- -DR_L Ack_Owner 0 <-- -DR_L Ack_Owner_All_Tokens 0 <-- -DR_L Tokens 0 <-- -DR_L Request_Timeout 0 <-- -DR_L DMA_READ 0 <-- -DR_L DMA_WRITE 0 <-- +DW_L GETX [0 ] 0 +DW_L GETS [0 ] 0 +DW_L Lockdown [0 ] 0 +DW_L Unlockdown [0 ] 0 +DW_L Own_Lock_or_Unlock [0 ] 0 +DW_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DW_L Data_Owner [0 ] 0 +DW_L Data_All_Tokens [0 ] 0 +DW_L Ack_Owner [0 ] 0 +DW_L Ack_Owner_All_Tokens [0 ] 0 +DW_L Tokens [0 ] 0 +DW_L Request_Timeout [0 ] 0 +DW_L DMA_READ [0 ] 0 +DW_L DMA_WRITE [0 ] 0 +DW_L DMA_WRITE_All_Tokens [0 ] 0 +DR_L GETX [0 ] 0 +DR_L GETS [0 ] 0 +DR_L Lockdown [0 ] 0 +DR_L Unlockdown [0 ] 0 +DR_L Own_Lock_or_Unlock [0 ] 0 +DR_L Own_Lock_or_Unlock_Tokens [0 ] 0 +DR_L Data_Owner [0 ] 0 +DR_L Data_All_Tokens [0 ] 0 +DR_L Ack_Owner [0 ] 0 +DR_L Ack_Owner_All_Tokens [0 ] 0 +DR_L Tokens [0 ] 0 +DR_L Request_Timeout [0 ] 0 +DR_L DMA_READ [0 ] 0 +DR_L DMA_WRITE [0 ] 0 +DR_L DMA_WRITE_All_Tokens \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:58:42 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:58:52 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 10:41:36 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:45:27 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_CMP_token/m5.fast -d build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token -re tests/run.py build/ALPHA_SE_MOESI_CMP_token/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_CMP_token Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 275491 because Ruby Tester completed +Exiting @ tick 273851 because Ruby Tester completed diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_CMP_token/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208544 # Number of bytes of host memory used +host_mem_usage 210052 # Number of bytes of host memory used host_seconds 0.53 # Real time elapsed on the host -host_tick_rate 518969 # Simulator tick rate (ticks/s) +host_tick_rate 516678 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000275 # Number of seconds simulated -sim_ticks 275491 # Number of ticks simulated +sim_seconds 0.000274 # Number of seconds simulated +sim_ticks 273851 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,114 @@ [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer probeFilter +buffer_size=0 +directory=system.dir_cntrl0.directory +memBuffer=system.dir_cntrl0.memBuffer +memory_controller_latency=2 +number_of_TBEs=256 +probeFilter=system.dir_cntrl0.probeFilter +probe_filter_enabled=false +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.dir_cntrl0.probeFilter] +type=RubyCache +assoc=4 +latency=1 +replacement_policy=PSEUDO_LRU +size=1024 +start_index_bit=6 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=L2cacheMemory sequencer +L1DcacheMemory=system.l1_cntrl0.sequencer.dcache +L1IcacheMemory=system.l1_cntrl0.sequencer.icache +L2cacheMemory=system.l1_cntrl0.L2cacheMemory +buffer_size=0 +cache_response_latency=10 +issue_latency=2 +no_mig_atomic=true +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.L2cacheMemory] +type=RubyCache +assoc=2 +latency=10 +replacement_policy=PSEUDO_LRU +size=512 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=dcache icache +dcache=system.l1_cntrl0.sequencer.dcache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.dcache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=2 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +121,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,117 +162,26 @@ children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=L2cacheMemory sequencer -L1DcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -L1IcacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -L2cacheMemory=system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory -buffer_size=0 -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory] -type=RubyCache -assoc=2 -latency=15 -replacement_policy=PSEUDO_LRU -size=512 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=dcache icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -memory_controller_latency=12 -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,29 +34,29 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 14:59:23 +Real time: Aug/05/2010 14:46:32 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.7 -Virtual_time_in_minutes: 0.0116667 -Virtual_time_in_hours: 0.000194444 -Virtual_time_in_days: 8.10185e-06 +Virtual_time_in_seconds: 0.69 +Virtual_time_in_minutes: 0.0115 +Virtual_time_in_hours: 0.000191667 +Virtual_time_in_days: 7.98611e-06 -Ruby_current_time: 222961 +Ruby_current_time: 213851 Ruby_start_time: 0 -Ruby_cycles: 222961 +Ruby_cycles: 213851 -mbytes_resident: 30.5156 -mbytes_total: 203.461 -resident_ratio: 0.150021 +mbytes_resident: 31.293 +mbytes_total: 31.3008 +resident_ratio: 1 -ruby_cycles_executed: [ 222962 ] +ruby_cycles_executed: [ 213852 ] Busy Controller Counts: L1Cache-0:0 @@ -65,13 +65,35 @@ Busy Bank Count:0 -sequencer_requests_outstanding: [binsize: 1 max: 16 count: 998 average: 15.7946 | standard deviation: 1.13528 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 84 899 ] +sequencer_requests_outstanding: [binsize: 1 max: 16 count: 963 average: 15.8069 | standard deviation: 1.15034 | 0 1 1 1 1 1 1 1 1 1 1 1 1 1 2 65 883 ] All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- -miss_latency: [binsize: 128 max: 23668 count: 983 average: 3530.64 | standard deviation: 5276.54 | 101 19 29 85 80 66 72 59 50 28 40 22 22 14 14 10 5 3 6 7 5 5 2 3 4 1 2 1 1 1 0 2 0 1 2 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 1 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 3 3 3 2 2 0 1 2 2 5 6 1 9 3 2 3 2 3 3 2 3 8 2 2 2 3 2 3 5 4 1 4 1 1 0 4 3 3 1 3 4 1 1 3 0 1 0 1 0 0 1 2 0 0 1 0 1 0 1 0 1 0 1 2 1 0 0 1 1 2 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ] -miss_latency_2: [binsize: 128 max: 19690 count: 100 average: 3024.87 | standard deviation: 5133.9 | 15 3 2 5 6 12 9 4 5 2 7 1 5 2 1 0 2 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 2 1 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 128 max: 23668 count: 883 average: 3587.92 | standard deviation: 5292.25 | 86 16 27 80 74 54 63 55 45 26 33 21 17 12 13 10 3 3 5 7 5 4 2 3 4 1 2 1 1 1 0 2 0 1 1 0 0 0 1 1 1 3 0 1 1 1 0 1 0 1 0 1 0 3 2 0 1 2 2 2 3 1 3 2 2 4 4 3 0 2 0 3 1 1 0 4 4 3 0 3 2 0 0 0 2 2 3 2 2 0 1 2 2 5 6 1 9 3 2 1 2 3 3 2 3 6 1 2 2 3 1 3 5 4 1 4 1 1 0 3 2 3 1 3 3 1 1 2 0 1 0 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 2 0 1 0 1 0 0 1 0 2 0 0 1 0 1 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 ] +miss_latency: [binsize: 128 max: 23081 count: 948 average: 3529.13 | standard deviation: 5116.76 | 71 12 47 82 73 59 68 59 47 38 28 25 17 14 12 7 10 4 1 9 4 5 5 7 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 4 4 5 5 1 4 3 3 3 3 3 3 4 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 8 max: 1215 count: 59 average: 478.39 | standard deviation: 246.067 | 2 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 128 max: 15642 count: 41 average: 3000.32 | standard deviation: 4886.74 | 5 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 128 max: 23081 count: 848 average: 3766.95 | standard deviation: 5236.59 | 61 10 32 62 58 52 60 56 43 35 27 24 17 14 12 5 10 4 0 9 4 5 5 6 3 3 6 3 1 0 4 1 3 0 3 2 2 3 2 4 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 4 3 4 4 1 4 3 3 3 3 3 3 4 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 1 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 1 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 1 max: 118 count: 65 average: 15.8923 | standard deviation: 35.394 | 0 9 14 16 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] +miss_latency_L2Cache: [binsize: 128 max: 19544 count: 29 average: 3519.03 | standard deviation: 5619.12 | 6 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Directory: [binsize: 128 max: 23081 count: 854 average: 3796.87 | standard deviation: 5197.84 | 0 10 46 78 72 57 67 59 47 38 27 25 16 14 12 7 10 3 1 9 4 5 5 6 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 4 0 6 1 1 1 3 1 4 0 4 2 3 4 5 4 1 4 3 3 3 3 3 3 3 1 2 3 2 4 2 2 0 0 2 1 6 3 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 854 +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 2 average: 2.5 | standard deviation: 1 | 0 0 1 1 ] +miss_latency_IFETCH_L2Cache: [binsize: 1 max: 123 count: 3 average: 50 | standard deviation: 63.2218 | 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 8 max: 1215 count: 54 average: 519.815 | standard deviation: 213.139 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 2 3 1 1 0 0 2 0 2 0 0 0 0 1 0 3 2 2 0 0 1 0 0 0 0 0 1 1 4 0 0 1 2 1 0 0 1 0 1 0 2 1 2 1 2 0 0 0 0 0 0 0 1 0 1 1 0 0 1 0 0 0 0 1 2 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache: [binsize: 1 max: 4 count: 5 average: 3 | standard deviation: 0.707107 | 0 0 1 3 1 ] +miss_latency_LD_Directory: [binsize: 128 max: 15642 count: 36 average: 3416.61 | standard deviation: 5082.33 | 0 0 3 6 1 3 2 3 3 2 1 1 0 0 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 118 count: 58 average: 17.4655 | standard deviation: 37.1906 | 0 9 12 12 17 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 2 1 0 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST_L2Cache: [binsize: 128 max: 19544 count: 26 average: 3919.31 | standard deviation: 5809.69 | 3 2 1 4 1 2 1 0 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_Directory: [binsize: 128 max: 23081 count: 764 average: 4046.41 | standard deviation: 5309.16 | 0 8 31 58 57 50 59 56 43 35 26 24 16 14 12 5 10 3 0 9 4 5 5 5 3 3 5 3 1 0 4 1 3 0 3 2 2 2 2 3 1 0 0 2 0 0 2 0 1 2 1 2 1 1 2 4 0 3 2 1 2 2 5 2 2 2 1 1 1 2 1 1 4 3 1 2 2 0 1 0 1 0 3 1 2 3 0 6 1 1 1 3 1 4 0 4 2 3 3 4 3 1 4 3 3 3 3 3 3 3 1 2 2 2 4 2 1 0 0 2 1 6 2 4 1 0 2 0 0 0 3 3 1 1 1 1 0 0 1 0 0 1 0 1 0 0 0 0 0 1 2 1 0 1 0 0 0 1 0 1 1 0 0 2 0 0 1 1 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,8 +125,8 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8816 -page_faults: 0 +page_reclaims: 6929 +page_faults: 1882 swaps: 0 block_inputs: 0 block_outputs: 0 @@ -112,451 +134,665 @@ Network Stats ------------- +total_msg_count_Request_Control: 2568 20544 +total_msg_count_Response_Data: 2562 184464 +total_msg_count_Writeback_Data: 2281 164232 +total_msg_count_Writeback_Control: 5351 42808 +total_msg_count_Unblock_Control: 2559 20472 +total_msgs: 15321 total_bytes: 432520 + switch_0_inlinks: 2 switch_0_outlinks: 2 -links_utilized_percent_switch_0: 0.13187 - links_utilized_percent_switch_0_link_0: 0.0481867 bw: 640000 base_latency: 1 - links_utilized_percent_switch_0_link_1: 0.215553 bw: 160000 base_latency: 1 +links_utilized_percent_switch_0: 0.13593 + links_utilized_percent_switch_0_link_0: 0.0498829 bw: 640000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.221977 bw: 160000 base_latency: 1 - outgoing_messages_switch_0_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_0_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Data: 761 54792 [ 0 0 0 0 0 761 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Writeback_Control: 936 7488 [ 0 0 849 0 0 87 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 switch_1_inlinks: 2 switch_1_outlinks: 2 -links_utilized_percent_switch_1: 0.123292 - links_utilized_percent_switch_1_link_0: 0.0538379 bw: 640000 base_latency: 1 - links_utilized_percent_switch_1_link_1: 0.192747 bw: 160000 base_latency: 1 +links_utilized_percent_switch_1: 0.127495 + links_utilized_percent_switch_1_link_0: 0.0554358 bw: 640000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 0.199555 bw: 160000 base_latency: 1 - outgoing_messages_switch_1_link_0_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Data: 772 55584 [ 0 0 0 0 0 772 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_0_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_1_link_1_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Writeback_Control: 849 6792 [ 0 0 0 849 0 0 0 0 0 0 ] base_latency: 1 switch_2_inlinks: 2 switch_2_outlinks: 2 -links_utilized_percent_switch_2: 0.20415 - links_utilized_percent_switch_2_link_0: 0.192747 bw: 160000 base_latency: 1 - links_utilized_percent_switch_2_link_1: 0.215553 bw: 160000 base_latency: 1 +links_utilized_percent_switch_2: 0.210637 + links_utilized_percent_switch_2_link_0: 0.199531 bw: 160000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 0.221743 bw: 160000 base_latency: 1 - outgoing_messages_switch_2_link_0_Response_Data: 860 61920 [ 0 0 0 0 860 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_0_Writeback_Control: 855 6840 [ 0 0 0 855 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Request_Control: 860 6880 [ 0 0 860 0 0 0 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Data: 773 55656 [ 0 0 0 0 0 773 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Writeback_Control: 937 7496 [ 0 0 855 0 0 82 0 0 0 0 ] base_latency: 1 - outgoing_messages_switch_2_link_1_Unblock_Control: 858 6864 [ 0 0 0 0 0 858 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Response_Data: 854 61488 [ 0 0 0 0 854 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 848 6784 [ 0 0 0 848 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Request_Control: 856 6848 [ 0 0 856 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Data: 760 54720 [ 0 0 0 0 0 760 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Writeback_Control: 935 7480 [ 0 0 849 0 0 86 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Unblock_Control: 853 6824 [ 0 0 0 0 0 853 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 57 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 57 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 100% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_misses: 889 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_demand_misses: 889 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_total_hw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 57 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_LD: 9.67379% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_type_ST: 90.3262% +Cache Stats: system.l1_cntrl0.sequencer.dcache + system.l1_cntrl0.sequencer.dcache_total_misses: 840 + system.l1_cntrl0.sequencer.dcache_total_demand_misses: 840 + system.l1_cntrl0.sequencer.dcache_total_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_access_mode_type_SupervisorMode: 889 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.dcache_request_size: [binsize: 1 max: 4 count: 889 average: 1.29021 | standard deviation: 0.887856 | 0 803 0 0 86 ] + system.l1_cntrl0.sequencer.dcache_request_type_LD: 4.28571% + system.l1_cntrl0.sequencer.dcache_request_type_ST: 95.7143% -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_misses: 860 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_demand_misses: 860 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_total_hw_prefetches: 0 + system.l1_cntrl0.sequencer.dcache_access_mode_type_SupervisorMode: 840 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_LD: 9.76744% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_type_ST: 90.2326% +Cache Stats: system.l1_cntrl0.L2cacheMemory + system.l1_cntrl0.L2cacheMemory_total_misses: 856 + system.l1_cntrl0.L2cacheMemory_total_demand_misses: 856 + system.l1_cntrl0.L2cacheMemory_total_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.L2cacheMemory_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_access_mode_type_SupervisorMode: 860 100% - system.ruby.network.topology.ext_links0.ext_node.L2cacheMemory_request_size: [binsize: 1 max: 4 count: 860 average: 1.29302 | standard deviation: 0.89169 | 0 776 0 0 84 ] + system.l1_cntrl0.L2cacheMemory_request_type_LD: 4.20561% + system.l1_cntrl0.L2cacheMemory_request_type_ST: 89.486% + system.l1_cntrl0.L2cacheMemory_request_type_IFETCH: 6.30841% - --- L1Cache 0 --- + system.l1_cntrl0.L2cacheMemory_access_mode_type_SupervisorMode: 856 100% + + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 887 -L2_Replacement 855 -L1_to_L2 318465 -L2_to_L1D 29 -L2_to_L1I 0 -Other_GETX 0 -Other_GETS 0 -Ack 0 -Shared_Ack 0 -Data 0 -Shared_Data 0 -Exclusive_Data 860 -Writeback_Ack 855 -Writeback_Nack 0 -All_acks 0 -All_acks_no_sharers 859 +Load [41 ] 41 +Ifetch [106 ] 106 +Store [906 ] 906 +L2_Replacement [849 ] 849 +L1_to_L2 [303164 ] 303164 +Trigger_L2_to_L1D [38 ] 38 +Trigger_L2_to_L1I [3 ] 3 +Complete_L2_to_L1 [41 ] 41 +Other_GETX [0 ] 0 +Other_GETS [0 ] 0 +Merged_GETS [0 ] 0 +Other_GETS_No_Mig [0 ] 0 +Invalidate [0 ] 0 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Data [0 ] 0 +Shared_Data [0 ] 0 +Exclusive_Data [854 ] 854 +Writeback_Ack [848 ] 848 +Writeback_Nack [0 ] 0 +All_acks [0 ] 0 +All_acks_no_sharers [853 ] 853 - Transitions - -I Load 84 -I Ifetch 0 <-- -I Store 776 -I L2_Replacement 0 <-- -I L1_to_L2 0 <-- -I L2_to_L1D 0 <-- -I L2_to_L1I 0 <-- -I Other_GETX 0 <-- -I Other_GETS 0 <-- +I Load [36 ] 36 +I Ifetch [54 ] 54 +I Store [766 ] 766 +I L2_Replacement [0 ] 0 +I L1_to_L2 [0 ] 0 +I Trigger_L2_to_L1D [0 ] 0 +I Trigger_L2_to_L1I [0 ] 0 +I Other_GETX [0 ] 0 +I Other_GETS [0 ] 0 +I Other_GETS_No_Mig [0 ] 0 +I Invalidate [0 ] 0 -S Load 0 <-- -S Ifetch 0 <-- -S Store 0 <-- -S L2_Replacement 0 <-- -S L1_to_L2 0 <-- -S L2_to_L1D 0 <-- -S L2_to_L1I 0 <-- -S Other_GETX 0 <-- -S Other_GETS 0 <-- +S Load [0 ] 0 +S Ifetch [0 ] 0 +S Store [0 ] 0 +S L2_Replacement [0 ] 0 +S L1_to_L2 [0 ] 0 +S Trigger_L2_to_L1D [0 ] 0 +S Trigger_L2_to_L1I [0 ] 0 +S Other_GETX [0 ] 0 +S Other_GETS [0 ] 0 +S Other_GETS_No_Mig [0 ] 0 +S Invalidate [0 ] 0 -O Load 0 <-- -O Ifetch 0 <-- -O Store 0 <-- -O L2_Replacement 0 <-- -O L1_to_L2 0 <-- -O L2_to_L1D 0 <-- -O L2_to_L1I 0 <-- -O Other_GETX 0 <-- -O Other_GETS 0 <-- +O Load [0 ] 0 +O Ifetch [0 ] 0 +O Store [0 ] 0 +O L2_Replacement [0 ] 0 +O L1_to_L2 [0 ] 0 +O Trigger_L2_to_L1D [0 ] 0 +O Trigger_L2_to_L1I [0 ] 0 +O Other_GETX [0 ] 0 +O Other_GETS [0 ] 0 +O Merged_GETS [0 ] 0 +O Other_GETS_No_Mig [0 ] 0 +O Invalidate [0 ] 0 -M Load 0 <-- -M Ifetch 0 <-- -M Store 1 -M L2_Replacement 82 -M L1_to_L2 82 -M L2_to_L1D 0 <-- -M L2_to_L1I 0 <-- -M Other_GETX 0 <-- -M Other_GETS 0 <-- +M Load [0 ] 0 +M Ifetch [1 ] 1 +M Store [1 ] 1 +M L2_Replacement [87 ] 87 +M L1_to_L2 [88 ] 88 +M Trigger_L2_to_L1D [1 ] 1 +M Trigger_L2_to_L1I [0 ] 0 +M Other_GETX [0 ] 0 +M Other_GETS [0 ] 0 +M Merged_GETS [0 ] 0 +M Other_GETS_No_Mig [0 ] 0 +M Invalidate [0 ] 0 -MM Load 16 -MM Ifetch 0 <-- -MM Store 102 -MM L2_Replacement 773 -MM L1_to_L2 804 -MM L2_to_L1D 29 -MM L2_to_L1I 0 <-- -MM Other_GETX 0 <-- -MM Other_GETS 0 <-- +MM Load [5 ] 5 +MM Ifetch [4 ] 4 +MM Store [82 ] 82 +MM L2_Replacement [762 ] 762 +MM L1_to_L2 [804 ] 804 +MM Trigger_L2_to_L1D [37 ] 37 +MM Trigger_L2_to_L1I [3 ] 3 +MM Other_GETX [0 ] 0 +MM Other_GETS [0 ] 0 +MM Merged_GETS [0 ] 0 +MM Other_GETS_No_Mig [0 ] 0 +MM Invalidate [0 ] 0 -IM Load 0 <-- -IM Ifetch 0 <-- -IM Store 0 <-- -IM L2_Replacement 0 <-- -IM L1_to_L2 276294 -IM Other_GETX 0 <-- -IM Other_GETS 0 <-- -IM Ack 0 <-- -IM Data 0 <-- -IM Exclusive_Data 776 +IM Load [0 ] 0 +IM Ifetch [0 ] 0 +IM Store [0 ] 0 +IM L2_Replacement [0 ] 0 +IM L1_to_L2 [275518 ] 275518 +IM Other_GETX [0 ] 0 +IM Other_GETS [0 ] 0 +IM Other_GETS_No_Mig [0 ] 0 +IM Invalidate [0 ] 0 +IM Ack [0 ] 0 +IM Data [0 ] 0 +IM Exclusive_Data [764 ] 764 -SM Load 0 <-- -SM Ifetch 0 <-- -SM Store 0 <-- -SM L2_Replacement 0 <-- -SM L1_to_L2 0 <-- -SM Other_GETX 0 <-- -SM Other_GETS 0 <-- -SM Ack 0 <-- -SM Data 0 <-- +SM Load [0 ] 0 +SM Ifetch [0 ] 0 +SM Store [0 ] 0 +SM L2_Replacement [0 ] 0 +SM L1_to_L2 [0 ] 0 +SM Other_GETX [0 ] 0 +SM Other_GETS [0 ] 0 +SM Other_GETS_No_Mig [0 ] 0 +SM Invalidate [0 ] 0 +SM Ack [0 ] 0 +SM Data [0 ] 0 -OM Load 0 <-- -OM Ifetch 0 <-- -OM Store 0 <-- -OM L2_Replacement 0 <-- -OM L1_to_L2 0 <-- -OM Other_GETX 0 <-- -OM Other_GETS 0 <-- -OM Ack 0 <-- -OM All_acks 0 <-- -OM All_acks_no_sharers 0 <-- +OM Load [0 ] 0 +OM Ifetch [0 ] 0 +OM Store [0 ] 0 +OM L2_Replacement [0 ] 0 +OM L1_to_L2 [0 ] 0 +OM Other_GETX [0 ] 0 +OM Other_GETS [0 ] 0 +OM Merged_GETS [0 ] 0 +OM Other_GETS_No_Mig [0 ] 0 +OM Invalidate [0 ] 0 +OM Ack [0 ] 0 +OM All_acks [0 ] 0 +OM All_acks_no_sharers [0 ] 0 -ISM Load 0 <-- -ISM Ifetch 0 <-- -ISM Store 0 <-- -ISM L2_Replacement 0 <-- -ISM L1_to_L2 0 <-- -ISM Ack 0 <-- -ISM All_acks_no_sharers 0 <-- +ISM Load [0 ] 0 +ISM Ifetch [0 ] 0 +ISM Store [0 ] 0 +ISM L2_Replacement [0 ] 0 +ISM L1_to_L2 [0 ] 0 +ISM Ack [0 ] 0 +ISM All_acks_no_sharers [0 ] 0 -M_W Load 0 <-- -M_W Ifetch 0 <-- -M_W Store 0 <-- -M_W L2_Replacement 0 <-- -M_W L1_to_L2 1192 -M_W Ack 0 <-- -M_W All_acks_no_sharers 83 +M_W Load [0 ] 0 +M_W Ifetch [0 ] 0 +M_W Store [0 ] 0 +M_W L2_Replacement [0 ] 0 +M_W L1_to_L2 [483 ] 483 +M_W Ack [0 ] 0 +M_W All_acks_no_sharers [89 ] 89 -MM_W Load 0 <-- -MM_W Ifetch 0 <-- -MM_W Store 4 -MM_W L2_Replacement 0 <-- -MM_W L1_to_L2 11046 -MM_W Ack 0 <-- -MM_W All_acks_no_sharers 776 +MM_W Load [0 ] 0 +MM_W Ifetch [0 ] 0 +MM_W Store [1 ] 1 +MM_W L2_Replacement [0 ] 0 +MM_W L1_to_L2 [10887 ] 10887 +MM_W Ack [0 ] 0 +MM_W All_acks_no_sharers [764 ] 764 -IS Load 0 <-- -IS Ifetch 0 <-- -IS Store 0 <-- -IS L2_Replacement 0 <-- -IS L1_to_L2 29047 -IS Other_GETX 0 <-- -IS Other_GETS 0 <-- -IS Ack 0 <-- -IS Shared_Ack 0 <-- -IS Data 0 <-- -IS Shared_Data 0 <-- -IS Exclusive_Data 84 +IS Load [0 ] 0 +IS Ifetch [0 ] 0 +IS Store [0 ] 0 +IS L2_Replacement [0 ] 0 +IS L1_to_L2 [14644 ] 14644 +IS Other_GETX [0 ] 0 +IS Other_GETS [0 ] 0 +IS Other_GETS_No_Mig [0 ] 0 +IS Invalidate [0 ] 0 +IS Ack [0 ] 0 +IS Shared_Ack [0 ] 0 +IS Data [0 ] 0 +IS Shared_Data [0 ] 0 +IS Exclusive_Data [90 ] 90 -SS Load 0 <-- -SS Ifetch 0 <-- -SS Store 0 <-- -SS L2_Replacement 0 <-- -SS L1_to_L2 0 <-- -SS Ack 0 <-- -SS Shared_Ack 0 <-- -SS All_acks 0 <-- -SS All_acks_no_sharers 0 <-- +SS Load [0 ] 0 +SS Ifetch [0 ] 0 +SS Store [0 ] 0 +SS L2_Replacement [0 ] 0 +SS L1_to_L2 [0 ] 0 +SS Ack [0 ] 0 +SS Shared_Ack [0 ] 0 +SS All_acks [0 ] 0 +SS All_acks_no_sharers [0 ] 0 -OI Load 0 <-- -OI Ifetch 0 <-- -OI Store 0 <-- -OI L2_Replacement 0 <-- -OI L1_to_L2 0 <-- -OI Other_GETX 0 <-- -OI Other_GETS 0 <-- -OI Writeback_Ack 0 <-- +OI Load [0 ] 0 +OI Ifetch [0 ] 0 +OI Store [0 ] 0 +OI L2_Replacement [0 ] 0 +OI L1_to_L2 [0 ] 0 +OI Other_GETX [0 ] 0 +OI Other_GETS [0 ] 0 +OI Merged_GETS [0 ] 0 +OI Other_GETS_No_Mig [0 ] 0 +OI Invalidate [0 ] 0 +OI Writeback_Ack [0 ] 0 -MI Load 0 <-- -MI Ifetch 0 <-- -MI Store 4 -MI L2_Replacement 0 <-- -MI L1_to_L2 0 <-- -MI Other_GETX 0 <-- -MI Other_GETS 0 <-- -MI Writeback_Ack 855 +MI Load [0 ] 0 +MI Ifetch [36 ] 36 +MI Store [5 ] 5 +MI L2_Replacement [0 ] 0 +MI L1_to_L2 [0 ] 0 +MI Other_GETX [0 ] 0 +MI Other_GETS [0 ] 0 +MI Merged_GETS [0 ] 0 +MI Other_GETS_No_Mig [0 ] 0 +MI Invalidate [0 ] 0 +MI Writeback_Ack [848 ] 848 -II Load 0 <-- -II Ifetch 0 <-- -II Store 0 <-- -II L2_Replacement 0 <-- -II L1_to_L2 0 <-- -II Other_GETX 0 <-- -II Other_GETS 0 <-- -II Writeback_Ack 0 <-- -II Writeback_Nack 0 <-- +II Load [0 ] 0 +II Ifetch [0 ] 0 +II Store [0 ] 0 +II L2_Replacement [0 ] 0 +II L1_to_L2 [0 ] 0 +II Other_GETX [0 ] 0 +II Other_GETS [0 ] 0 +II Other_GETS_No_Mig [0 ] 0 +II Invalidate [0 ] 0 +II Writeback_Ack [0 ] 0 +II Writeback_Nack [0 ] 0 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: - memory_total_requests: 1632 - memory_reads: 860 - memory_writes: 772 - memory_refreshes: 465 - memory_total_request_delays: 1106 - memory_delays_per_request: 0.677696 - memory_delays_in_input_queue: 152 - memory_delays_behind_head_of_bank_queue: 0 - memory_delays_stalled_at_head_of_bank_queue: 954 - memory_stalls_for_bank_busy: 245 +IT Load [0 ] 0 +IT Ifetch [0 ] 0 +IT Store [0 ] 0 +IT L2_Replacement [0 ] 0 +IT L1_to_L2 [0 ] 0 +IT Complete_L2_to_L1 [0 ] 0 +IT Other_GETX [0 ] 0 +IT Other_GETS [0 ] 0 +IT Merged_GETS [0 ] 0 +IT Other_GETS_No_Mig [0 ] 0 +IT Invalidate [0 ] 0 + +ST Load [0 ] 0 +ST Ifetch [0 ] 0 +ST Store [0 ] 0 +ST L2_Replacement [0 ] 0 +ST L1_to_L2 [0 ] 0 +ST Complete_L2_to_L1 [0 ] 0 +ST Other_GETX [0 ] 0 +ST Other_GETS [0 ] 0 +ST Merged_GETS [0 ] 0 +ST Other_GETS_No_Mig [0 ] 0 +ST Invalidate [0 ] 0 + +OT Load [0 ] 0 +OT Ifetch [0 ] 0 +OT Store [0 ] 0 +OT L2_Replacement [0 ] 0 +OT L1_to_L2 [0 ] 0 +OT Complete_L2_to_L1 [0 ] 0 +OT Other_GETX [0 ] 0 +OT Other_GETS [0 ] 0 +OT Merged_GETS [0 ] 0 +OT Other_GETS_No_Mig [0 ] 0 +OT Invalidate [0 ] 0 + +MT Load [0 ] 0 +MT Ifetch [0 ] 0 +MT Store [10 ] 10 +MT L2_Replacement [0 ] 0 +MT L1_to_L2 [154 ] 154 +MT Complete_L2_to_L1 [1 ] 1 +MT Other_GETX [0 ] 0 +MT Other_GETS [0 ] 0 +MT Merged_GETS [0 ] 0 +MT Other_GETS_No_Mig [0 ] 0 +MT Invalidate [0 ] 0 + +MMT Load [0 ] 0 +MMT Ifetch [11 ] 11 +MMT Store [41 ] 41 +MMT L2_Replacement [0 ] 0 +MMT L1_to_L2 [586 ] 586 +MMT Complete_L2_to_L1 [40 ] 40 +MMT Other_GETX [0 ] 0 +MMT Other_GETS [0 ] 0 +MMT Merged_GETS [0 ] 0 +MMT Other_GETS_No_Mig [0 ] 0 +MMT Invalidate [0 ] 0 + +Cache Stats: system.dir_cntrl0.probeFilter + system.dir_cntrl0.probeFilter_total_misses: 0 + system.dir_cntrl0.probeFilter_total_demand_misses: 0 + system.dir_cntrl0.probeFilter_total_prefetches: 0 + system.dir_cntrl0.probeFilter_total_sw_prefetches: 0 + system.dir_cntrl0.probeFilter_total_hw_prefetches: 0 + + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 1616 + memory_reads: 856 + memory_writes: 760 + memory_refreshes: 446 + memory_total_request_delays: 1108 + memory_delays_per_request: 0.685644 + memory_delays_in_input_queue: 161 + memory_delays_behind_head_of_bank_queue: 2 + memory_delays_stalled_at_head_of_bank_queue: 945 + memory_stalls_for_bank_busy: 192 memory_stalls_for_random_busy: 0 memory_stalls_for_anti_starvation: 0 - memory_stalls_for_arbitration: 77 - memory_stalls_for_bus: 374 + memory_stalls_for_arbitration: 83 + memory_stalls_for_bus: 395 memory_stalls_for_tfaw: 0 - memory_stalls_for_read_write_turnaround: 150 - memory_stalls_for_read_read_turnaround: 108 - accesses_per_bank: 35 39 45 95 73 66 68 49 65 50 44 55 48 35 48 57 45 44 54 56 48 27 42 58 48 39 39 44 54 55 48 59 + memory_stalls_for_read_write_turnaround: 154 + memory_stalls_for_read_read_turnaround: 121 + accesses_per_bank: 34 44 48 84 67 62 61 53 41 30 54 49 46 47 41 52 49 35 67 45 67 44 44 46 55 52 53 50 44 47 56 49 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 809 -GETS 84 -PUT 1454 -Unblock 858 -Writeback_Clean 0 -Writeback_Dirty 0 -Writeback_Exclusive_Clean 82 -Writeback_Exclusive_Dirty 772 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 860 -Memory_Ack 772 -Ack 0 -Shared_Ack 0 -Shared_Data 0 -Exclusive_Data 0 -All_acks_and_data 0 -All_acks_and_data_no_sharers 0 +GETX [770 ] 770 +GETS [91 ] 91 +PUT [909 ] 909 +Unblock [0 ] 0 +UnblockS [0 ] 0 +UnblockM [853 ] 853 +Writeback_Clean [0 ] 0 +Writeback_Dirty [0 ] 0 +Writeback_Exclusive_Clean [86 ] 86 +Writeback_Exclusive_Dirty [760 ] 760 +Pf_Replacement [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [854 ] 854 +Memory_Ack [760 ] 760 +Ack [0 ] 0 +Shared_Ack [0 ] 0 +Shared_Data [0 ] 0 +Data [0 ] 0 +Exclusive_Data [0 ] 0 +All_acks_and_shared_data [0 ] 0 +All_acks_and_owner_data [0 ] 0 +All_acks_and_data_no_sharers [0 ] 0 +All_Unblocks [0 ] 0 - Transitions - -NO GETX 0 <-- -NO GETS 0 <-- -NO PUT 855 -NO DMA_READ 0 <-- -NO DMA_WRITE 0 <-- +NX GETX [0 ] 0 +NX GETS [0 ] 0 +NX PUT [0 ] 0 +NX Pf_Replacement [0 ] 0 +NX DMA_READ [0 ] 0 +NX DMA_WRITE [0 ] 0 -O GETX 0 <-- -O GETS 0 <-- -O PUT 0 <-- -O DMA_READ 0 <-- -O DMA_WRITE 0 <-- +NO GETX [0 ] 0 +NO GETS [0 ] 0 +NO PUT [849 ] 849 +NO Pf_Replacement [0 ] 0 +NO DMA_READ [0 ] 0 +NO DMA_WRITE [0 ] 0 -E GETX 776 -E GETS 84 -E PUT 0 <-- -E DMA_READ 0 <-- -E DMA_WRITE 0 <-- +S GETX [0 ] 0 +S GETS [0 ] 0 +S PUT [0 ] 0 +S Pf_Replacement [0 ] 0 +S DMA_READ [0 ] 0 +S DMA_WRITE [0 ] 0 -NO_B GETX 0 <-- -NO_B GETS 0 <-- -NO_B PUT 599 -NO_B Unblock 858 -NO_B DMA_READ 0 <-- -NO_B DMA_WRITE 0 <-- +O GETX [0 ] 0 +O GETS [0 ] 0 +O PUT [0 ] 0 +O Pf_Replacement [0 ] 0 +O DMA_READ [0 ] 0 +O DMA_WRITE [0 ] 0 -O_B GETX 0 <-- -O_B GETS 0 <-- -O_B PUT 0 <-- -O_B Unblock 0 <-- -O_B DMA_READ 0 <-- -O_B DMA_WRITE 0 <-- +E GETX [766 ] 766 +E GETS [90 ] 90 +E PUT [0 ] 0 +E DMA_READ [0 ] 0 +E DMA_WRITE [0 ] 0 -NO_B_W GETX 0 <-- -NO_B_W GETS 0 <-- -NO_B_W PUT 0 <-- -NO_B_W Unblock 0 <-- -NO_B_W DMA_READ 0 <-- -NO_B_W DMA_WRITE 0 <-- -NO_B_W Memory_Data 860 +O_R GETX [0 ] 0 +O_R GETS [0 ] 0 +O_R PUT [0 ] 0 +O_R Pf_Replacement [0 ] 0 +O_R DMA_READ [0 ] 0 +O_R DMA_WRITE [0 ] 0 +O_R Ack [0 ] 0 +O_R All_acks_and_data_no_sharers [0 ] 0 -O_B_W GETX 0 <-- -O_B_W GETS 0 <-- -O_B_W PUT 0 <-- -O_B_W Unblock 0 <-- -O_B_W DMA_READ 0 <-- -O_B_W DMA_WRITE 0 <-- -O_B_W Memory_Data 0 <-- +S_R GETX [0 ] 0 +S_R GETS [0 ] 0 +S_R PUT [0 ] 0 +S_R Pf_Replacement [0 ] 0 +S_R DMA_READ [0 ] 0 +S_R DMA_WRITE [0 ] 0 +S_R Ack [0 ] 0 +S_R Data [0 ] 0 +S_R All_acks_and_data_no_sharers [0 ] 0 -NO_W GETX 0 <-- -NO_W GETS 0 <-- -NO_W PUT 0 <-- -NO_W DMA_READ 0 <-- -NO_W DMA_WRITE 0 <-- -NO_W Memory_Data 0 <-- +NO_R GETX [0 ] 0 +NO_R GETS [0 ] 0 +NO_R PUT [0 ] 0 +NO_R Pf_Replacement [0 ] 0 +NO_R DMA_READ [0 ] 0 +NO_R DMA_WRITE [0 ] 0 +NO_R Ack [0 ] 0 +NO_R Data [0 ] 0 +NO_R Exclusive_Data [0 ] 0 +NO_R All_acks_and_data_no_sharers [0 ] 0 -O_W GETX 0 <-- -O_W GETS 0 <-- -O_W PUT 0 <-- -O_W DMA_READ 0 <-- -O_W DMA_WRITE 0 <-- -O_W Memory_Data 0 <-- +NO_B GETX [0 ] 0 +NO_B GETS [0 ] 0 +NO_B PUT [60 ] 60 +NO_B UnblockS [0 ] 0 +NO_B UnblockM [853 ] 853 +NO_B Pf_Replacement [0 ] 0 +NO_B DMA_READ [0 ] 0 +NO_B DMA_WRITE [0 ] 0 -NO_DW_B_W GETX 0 <-- -NO_DW_B_W GETS 0 <-- -NO_DW_B_W PUT 0 <-- -NO_DW_B_W DMA_READ 0 <-- -NO_DW_B_W DMA_WRITE 0 <-- -NO_DW_B_W Ack 0 <-- -NO_DW_B_W Exclusive_Data 0 <-- -NO_DW_B_W All_acks_and_data_no_sharers 0 <-- +NO_B_X GETX [0 ] 0 +NO_B_X GETS [0 ] 0 +NO_B_X PUT [0 ] 0 +NO_B_X UnblockS [0 ] 0 +NO_B_X UnblockM [0 ] 0 +NO_B_X Pf_Replacement [0 ] 0 -NO_DR_B_W GETX 0 <-- -NO_DR_B_W GETS 0 <-- -NO_DR_B_W PUT 0 <-- -NO_DR_B_W DMA_READ 0 <-- -NO_DR_B_W DMA_WRITE 0 <-- -NO_DR_B_W Memory_Data 0 <-- -NO_DR_B_W Ack 0 <-- -NO_DR_B_W Shared_Ack 0 <-- -NO_DR_B_W Shared_Data 0 <-- -NO_DR_B_W Exclusive_Data 0 <-- +NO_B_S GETX [0 ] 0 +NO_B_S GETS [0 ] 0 +NO_B_S PUT [0 ] 0 +NO_B_S UnblockS [0 ] 0 +NO_B_S UnblockM [0 ] 0 +NO_B_S Pf_Replacement [0 ] 0 +NO_B_S DMA_READ [0 ] 0 +NO_B_S DMA_WRITE [0 ] 0 -NO_DR_B_D GETX 0 <-- -NO_DR_B_D GETS 0 <-- -NO_DR_B_D PUT 0 <-- -NO_DR_B_D DMA_READ 0 <-- -NO_DR_B_D DMA_WRITE 0 <-- -NO_DR_B_D Ack 0 <-- -NO_DR_B_D Shared_Ack 0 <-- -NO_DR_B_D Shared_Data 0 <-- -NO_DR_B_D Exclusive_Data 0 <-- -NO_DR_B_D All_acks_and_data 0 <-- -NO_DR_B_D All_acks_and_data_no_sharers 0 <-- +NO_B_S_W GETX [0 ] 0 +NO_B_S_W GETS [0 ] 0 +NO_B_S_W PUT [0 ] 0 +NO_B_S_W UnblockS [0 ] 0 +NO_B_S_W Pf_Replacement [0 ] 0 +NO_B_S_W DMA_READ [0 ] 0 +NO_B_S_W DMA_WRITE [0 ] 0 +NO_B_S_W All_Unblocks [0 ] 0 -NO_DR_B GETX 0 <-- -NO_DR_B GETS 0 <-- -NO_DR_B PUT 0 <-- -NO_DR_B DMA_READ 0 <-- -NO_DR_B DMA_WRITE 0 <-- -NO_DR_B Ack 0 <-- -NO_DR_B Shared_Ack 0 <-- -NO_DR_B Shared_Data 0 <-- -NO_DR_B Exclusive_Data 0 <-- -NO_DR_B All_acks_and_data 0 <-- -NO_DR_B All_acks_and_data_no_sharers 0 <-- +O_B GETX [0 ] 0 +O_B GETS [0 ] 0 +O_B PUT [0 ] 0 +O_B UnblockS [0 ] 0 +O_B Pf_Replacement [0 ] 0 +O_B DMA_READ [0 ] 0 +O_B DMA_WRITE [0 ] 0 -NO_DW_W GETX 0 <-- -NO_DW_W GETS 0 <-- -NO_DW_W PUT 0 <-- -NO_DW_W DMA_READ 0 <-- -NO_DW_W DMA_WRITE 0 <-- -NO_DW_W Memory_Ack 0 <-- +NO_B_W GETX [0 ] 0 +NO_B_W GETS [0 ] 0 +NO_B_W PUT [0 ] 0 +NO_B_W UnblockS [0 ] 0 +NO_B_W UnblockM [0 ] 0 +NO_B_W Pf_Replacement [0 ] 0 +NO_B_W DMA_READ [0 ] 0 +NO_B_W DMA_WRITE [0 ] 0 +NO_B_W Memory_Data [854 ] 854 -O_DR_B_W GETX 0 <-- -O_DR_B_W GETS 0 <-- -O_DR_B_W PUT 0 <-- -O_DR_B_W DMA_READ 0 <-- -O_DR_B_W DMA_WRITE 0 <-- -O_DR_B_W Memory_Data 0 <-- +O_B_W GETX [0 ] 0 +O_B_W GETS [0 ] 0 +O_B_W PUT [0 ] 0 +O_B_W UnblockS [0 ] 0 +O_B_W Pf_Replacement [0 ] 0 +O_B_W DMA_READ [0 ] 0 +O_B_W DMA_WRITE [0 ] 0 +O_B_W Memory_Data [0 ] 0 -O_DR_B GETX 0 <-- -O_DR_B GETS 0 <-- -O_DR_B PUT 0 <-- -O_DR_B DMA_READ 0 <-- -O_DR_B DMA_WRITE 0 <-- -O_DR_B Ack 0 <-- -O_DR_B All_acks_and_data_no_sharers 0 <-- +NO_W GETX [0 ] 0 +NO_W GETS [0 ] 0 +NO_W PUT [0 ] 0 +NO_W Pf_Replacement [0 ] 0 +NO_W DMA_READ [0 ] 0 +NO_W DMA_WRITE [0 ] 0 +NO_W Memory_Data [0 ] 0 -WB GETX 0 <-- -WB GETS 0 <-- -WB PUT 0 <-- -WB Unblock 0 <-- -WB Writeback_Clean 0 <-- -WB Writeback_Dirty 0 <-- -WB Writeback_Exclusive_Clean 82 -WB Writeback_Exclusive_Dirty 772 -WB DMA_READ 0 <-- -WB DMA_WRITE 0 <-- +O_W GETX [0 ] 0 +O_W GETS [0 ] 0 +O_W PUT [0 ] 0 +O_W Pf_Replacement [0 ] 0 +O_W DMA_READ [0 ] 0 +O_W DMA_WRITE [0 ] 0 +O_W Memory_Data [0 ] 0 -WB_O_W GETX 0 <-- -WB_O_W GETS 0 <-- -WB_O_W PUT 0 <-- -WB_O_W DMA_READ 0 <-- -WB_O_W DMA_WRITE 0 <-- -WB_O_W Memory_Ack 0 <-- +NO_DW_B_W GETX [0 ] 0 +NO_DW_B_W GETS [0 ] 0 +NO_DW_B_W PUT [0 ] 0 +NO_DW_B_W Pf_Replacement [0 ] 0 +NO_DW_B_W DMA_READ [0 ] 0 +NO_DW_B_W DMA_WRITE [0 ] 0 +NO_DW_B_W Ack [0 ] 0 +NO_DW_B_W Data [0 ] 0 +NO_DW_B_W Exclusive_Data [0 ] 0 +NO_DW_B_W All_acks_and_data_no_sharers [0 ] 0 -WB_E_W GETX 33 -WB_E_W GETS 0 <-- -WB_E_W PUT 0 <-- -WB_E_W DMA_READ 0 <-- -WB_E_W DMA_WRITE 0 <-- -WB_E_W Memory_Ack 772 +NO_DR_B_W GETX [0 ] 0 +NO_DR_B_W GETS [0 ] 0 +NO_DR_B_W PUT [0 ] 0 +NO_DR_B_W Pf_Replacement [0 ] 0 +NO_DR_B_W DMA_READ [0 ] 0 +NO_DR_B_W DMA_WRITE [0 ] 0 +NO_DR_B_W Memory_Data [0 ] 0 +NO_DR_B_W Ack [0 ] 0 +NO_DR_B_W Shared_Ack [0 ] 0 +NO_DR_B_W Shared_Data [0 ] 0 +NO_DR_B_W Data [0 ] 0 +NO_DR_B_W Exclusive_Data [0 ] 0 +NO_DR_B_D GETX [0 ] 0 +NO_DR_B_D GETS [0 ] 0 +NO_DR_B_D PUT [0 ] 0 +NO_DR_B_D Pf_Replacement [0 ] 0 +NO_DR_B_D DMA_READ [0 ] 0 +NO_DR_B_D DMA_WRITE [0 ] 0 +NO_DR_B_D Ack [0 ] 0 +NO_DR_B_D Shared_Ack [0 ] 0 +NO_DR_B_D Shared_Data [0 ] 0 +NO_DR_B_D Data [0 ] 0 +NO_DR_B_D Exclusive_Data [0 ] 0 +NO_DR_B_D All_acks_and_shared_data [0 ] 0 +NO_DR_B_D All_acks_and_owner_data [0 ] 0 +NO_DR_B_D All_acks_and_data_no_sharers [0 ] 0 + +NO_DR_B GETX [0 ] 0 +NO_DR_B GETS [0 ] 0 +NO_DR_B PUT [0 ] 0 +NO_DR_B Pf_Replacement [0 ] 0 +NO_DR_B DMA_READ [0 ] 0 +NO_DR_B DMA_WRITE [0 ] 0 +NO_DR_B Ack [0 ] 0 +NO_DR_B Shared_Ack [0 ] 0 +NO_DR_B Shared_Data [0 ] 0 +NO_DR_B Data [0 ] 0 +NO_DR_B Exclusive_Data [0 ] 0 +NO_DR_B All_acks_and_shared_data [0 ] 0 +NO_DR_B All_acks_and_owner_data [0 ] 0 +NO_DR_B All_acks_and_data_no_sharers [0 ] 0 + +NO_DW_W GETX [0 ] 0 +NO_DW_W GETS [0 ] 0 +NO_DW_W PUT [0 ] 0 +NO_DW_W Pf_Replacement [0 ] 0 +NO_DW_W DMA_READ [0 ] 0 +NO_DW_W DMA_WRITE [0 ] 0 +NO_DW_W Memory_Ack [0 ] 0 + +O_DR_B_W GETX [0 ] 0 +O_DR_B_W GETS [0 ] 0 +O_DR_B_W PUT [0 ] 0 +O_DR_B_W Pf_Replacement [0 ] 0 +O_DR_B_W DMA_READ [0 ] 0 +O_DR_B_W DMA_WRITE [0 ] 0 +O_DR_B_W Memory_Data [0 ] 0 +O_DR_B_W Ack [0 ] 0 +O_DR_B_W Shared_Ack [0 ] 0 + +O_DR_B GETX [0 ] 0 +O_DR_B GETS [0 ] 0 +O_DR_B PUT [0 ] 0 +O_DR_B Pf_Replacement [0 ] 0 +O_DR_B DMA_READ [0 ] 0 +O_DR_B DMA_WRITE [0 ] 0 +O_DR_B Ack [0 ] 0 +O_DR_B Shared_Ack [0 ] 0 +O_DR_B All_acks_and_owner_data [0 ] 0 +O_DR_B All_acks_and_data_no_sharers [0 ] 0 + +WB GETX [2 ] 2 +WB GETS [1 ] 1 +WB PUT [0 ] 0 +WB Unblock [0 ] 0 +WB Writeback_Clean [0 ] 0 +WB Writeback_Dirty [0 ] 0 +WB Writeback_Exclusive_Clean [86 ] 86 +WB Writeback_Exclusive_Dirty [760 ] 760 +WB Pf_Replacement [0 ] 0 +WB DMA_READ [0 ] 0 +WB DMA_WRITE [0 ] 0 + +WB_O_W GETX [0 ] 0 +WB_O_W GETS [0 ] 0 +WB_O_W PUT [0 ] 0 +WB_O_W Pf_Replacement [0 ] 0 +WB_O_W DMA_READ [0 ] 0 +WB_O_W DMA_WRITE [0 ] 0 +WB_O_W Memory_Ack [0 ] 0 + +WB_E_W GETX [2 ] 2 +WB_E_W GETS [0 ] 0 +WB_E_W PUT [0 ] 0 +WB_E_W Pf_Replacement [0 ] 0 +WB_E_W DMA_READ [0 ] 0 +WB_E_W DMA_WRITE [0 ] 0 +WB_E_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/simout Wed Aug 11 14:38:35 2010 -0700 @@ -5,11 +5,11 @@ All Rights Reserved -M5 compiled Mar 18 2010 14:59:19 -M5 revision 6a6bb24e484f+ 7041+ default qtip tip brad/regress_updates -M5 started Mar 18 2010 14:59:22 -M5 executing on cabr0210 +M5 compiled Aug 5 2010 14:43:33 +M5 revision c5f5b5533e96+ 7536+ default qtip tip brad/regress_updates +M5 started Aug 5 2010 14:46:32 +M5 executing on svvint09 command line: build/ALPHA_SE_MOESI_hammer/m5.fast -d build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer -re tests/run.py build/ALPHA_SE_MOESI_hammer/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby-MOESI_hammer Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... -Exiting @ tick 222961 because Ruby Tester completed +Exiting @ tick 213851 because Ruby Tester completed diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby-MOESI_hammer/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,10 +1,10 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208348 # Number of bytes of host memory used -host_seconds 0.53 # Real time elapsed on the host -host_tick_rate 420464 # Simulator tick rate (ticks/s) +host_mem_usage 209796 # Number of bytes of host memory used +host_seconds 0.44 # Real time elapsed on the host +host_tick_rate 485996 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks -sim_seconds 0.000223 # Number of seconds simulated -sim_ticks 222961 # Number of ticks simulated +sim_seconds 0.000214 # Number of seconds simulated +sim_ticks 213851 # Number of ticks simulated ---------- End Simulation Statistics ---------- diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/config.ini Wed Aug 11 14:38:35 2010 -0700 @@ -5,10 +5,85 @@ [system] type=System -children=physmem ruby +children=dir_cntrl0 l1_cntrl0 physmem ruby mem_mode=timing physmem=system.physmem +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.sequencer.icache +cache_response_latency=12 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +children=icache +dcache=system.l1_cntrl0.sequencer.icache +deadlock_threshold=500000 +icache=system.l1_cntrl0.sequencer.icache +max_outstanding_requests=16 +physmem=system.physmem +using_ruby_tester=true +version=0 +physMemPort=system.physmem.port[0] +port=root.cpuPort[0] + +[system.l1_cntrl0.sequencer.icache] +type=RubyCache +assoc=2 +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + [system.physmem] type=PhysicalMemory file= @@ -17,7 +92,7 @@ null=false range=0:134217727 zero=false -port=system.ruby.network.topology.ext_links0.ext_node.sequencer.physMemPort +port=system.l1_cntrl0.sequencer.physMemPort [system.ruby] type=RubySystem @@ -58,101 +133,26 @@ children=ext_links0 ext_links1 int_links0 int_links1 ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 +name=Crossbar num_int_nodes=3 print_config=false [system.ruby.network.topology.ext_links0] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links0.ext_node +ext_node=system.l1_cntrl0 int_node=0 latency=1 weight=1 -[system.ruby.network.topology.ext_links0.ext_node] -type=L1Cache_Controller -children=sequencer -buffer_size=0 -cacheMemory=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -cache_response_latency=12 -issue_latency=2 -number_of_TBEs=256 -recycle_latency=10 -sequencer=system.ruby.network.topology.ext_links0.ext_node.sequencer -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links0.ext_node.sequencer] -type=RubySequencer -children=icache -dcache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -deadlock_threshold=500000 -icache=system.ruby.network.topology.ext_links0.ext_node.sequencer.icache -max_outstanding_requests=16 -physmem=system.physmem -using_ruby_tester=true -version=0 -physMemPort=system.physmem.port[0] -port=root.cpuPort[0] - -[system.ruby.network.topology.ext_links0.ext_node.sequencer.icache] -type=RubyCache -assoc=2 -latency=3 -replacement_policy=PSEUDO_LRU -size=256 - [system.ruby.network.topology.ext_links1] type=ExtLink -children=ext_node bw_multiplier=64 -ext_node=system.ruby.network.topology.ext_links1.ext_node +ext_node=system.dir_cntrl0 int_node=1 latency=1 weight=1 -[system.ruby.network.topology.ext_links1.ext_node] -type=Directory_Controller -children=directory memBuffer -buffer_size=0 -directory=system.ruby.network.topology.ext_links1.ext_node.directory -directory_latency=12 -memBuffer=system.ruby.network.topology.ext_links1.ext_node.memBuffer -number_of_TBEs=256 -recycle_latency=10 -transitions_per_cycle=32 -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.directory] -type=RubyDirectoryMemory -map_levels=4 -numa_high_bit=0 -size=134217728 -use_map=false -version=0 - -[system.ruby.network.topology.ext_links1.ext_node.memBuffer] -type=RubyMemoryControl -bank_bit_0=8 -bank_busy_time=11 -bank_queue_size=12 -banks_per_rank=8 -basic_bus_busy_time=2 -dimm_bit_0=12 -dimms_per_channel=2 -mem_bus_cycle_multiplier=10 -mem_ctl_latency=12 -mem_fixed_delay=0 -mem_random_arbitrate=0 -rank_bit_0=11 -rank_rank_delay=1 -ranks_per_dimm=2 -read_write_delay=2 -refresh_period=1560 -tFaw=0 -version=0 - [system.ruby.network.topology.int_links0] type=IntLink bw_multiplier=16 diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/ruby.stats Wed Aug 11 14:38:35 2010 -0700 @@ -13,7 +13,7 @@ Network Configuration --------------------- network: SIMPLE_NETWORK -topology: +topology: Crossbar virtual_net_0: active, ordered virtual_net_1: active, ordered @@ -34,27 +34,27 @@ ================ End RubySystem Configuration Print ================ -Real time: Mar/18/2010 13:52:47 +Real time: Aug/05/2010 10:10:57 Profiler Stats -------------- -Elapsed_time_in_seconds: 1 -Elapsed_time_in_minutes: 0.0166667 -Elapsed_time_in_hours: 0.000277778 -Elapsed_time_in_days: 1.15741e-05 +Elapsed_time_in_seconds: 0 +Elapsed_time_in_minutes: 0 +Elapsed_time_in_hours: 0 +Elapsed_time_in_days: 0 -Virtual_time_in_seconds: 0.27 -Virtual_time_in_minutes: 0.0045 -Virtual_time_in_hours: 7.5e-05 -Virtual_time_in_days: 3.125e-06 +Virtual_time_in_seconds: 0.29 +Virtual_time_in_minutes: 0.00483333 +Virtual_time_in_hours: 8.05556e-05 +Virtual_time_in_days: 3.35648e-06 Ruby_current_time: 281031 Ruby_start_time: 0 Ruby_cycles: 281031 -mbytes_resident: 30.418 -mbytes_total: 203.402 -resident_ratio: 0.149584 +mbytes_resident: 30.9531 +mbytes_total: 203.703 +resident_ratio: 0.15199 ruby_cycles_executed: [ 281032 ] @@ -70,8 +70,27 @@ All Non-Zero Cycle Demand Cache Accesses ---------------------------------------- miss_latency: [binsize: 32 max: 6068 count: 999 average: 4453.7 | standard deviation: 529.325 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 5 6 4 7 8 11 10 20 9 19 17 13 22 23 30 23 21 22 25 31 27 31 39 35 22 20 39 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] -miss_latency_2: [binsize: 32 max: 5702 count: 100 average: 4601.67 | standard deviation: 400.66 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 2 0 3 1 1 3 4 5 2 3 1 2 2 1 1 5 2 0 2 2 2 5 2 2 3 1 3 3 1 5 4 4 2 3 3 1 1 3 3 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] -miss_latency_3: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 32 max: 5702 count: 52 average: 4674.27 | standard deviation: 454.241 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 2 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD: [binsize: 32 max: 5245 count: 48 average: 4523.02 | standard deviation: 319.516 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST: [binsize: 32 max: 6068 count: 899 average: 4437.24 | standard deviation: 539.424 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 1 0 0 0 0 1 1 1 0 1 0 1 1 2 5 0 4 1 2 6 3 6 4 6 4 7 7 11 9 18 9 16 16 12 19 19 25 21 18 21 23 29 26 30 34 33 22 18 37 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_L1Cache: [binsize: 32 max: 4572 count: 43 average: 3768.3 | standard deviation: 359.401 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 4 1 3 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ] +miss_latency_Directory: [binsize: 32 max: 6068 count: 956 average: 4484.53 | standard deviation: 514.797 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 4 3 3 5 7 10 10 16 8 16 17 11 22 23 29 23 21 22 25 31 27 31 37 35 22 20 37 25 30 27 25 23 23 19 22 10 24 20 22 19 19 12 21 14 12 11 5 8 6 0 3 2 0 2 0 2 0 1 0 0 0 0 2 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 0 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_dir_Times: 956 +miss_latency_IFETCH_L1Cache: [binsize: 32 max: 4022 count: 1 average: 4022 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_IFETCH_Directory: [binsize: 32 max: 5702 count: 51 average: 4687.06 | standard deviation: 449.206 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 1 3 4 0 0 0 0 1 0 1 1 1 0 0 1 0 1 0 2 2 0 3 2 0 3 0 3 1 3 3 1 1 3 2 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_L1Cache: [binsize: 32 max: 3964 count: 1 average: 3964 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_LD_Directory: [binsize: 32 max: 5245 count: 47 average: 4534.91 | standard deviation: 312.044 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 2 1 1 2 3 1 2 1 1 0 4 1 0 2 1 2 4 2 0 1 1 0 1 1 2 4 1 1 0 0 0 0 0 1 0 1 ] +miss_latency_ST_L1Cache: [binsize: 32 max: 4572 count: 41 average: 3757.34 | standard deviation: 364.607 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 0 1 0 1 0 2 2 0 3 1 0 2 2 1 1 3 1 2 1 1 0 3 1 2 0 2 0 0 1 0 0 0 0 0 0 0 2 0 0 0 2 ] +miss_latency_ST_Directory: [binsize: 32 max: 6068 count: 858 average: 4469.73 | standard deviation: 524.902 | 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 3 0 1 0 2 4 1 5 3 3 3 5 6 10 9 15 8 14 16 10 19 19 24 21 18 21 23 29 26 30 32 33 22 18 35 23 25 25 23 20 22 16 19 9 19 16 18 17 16 9 20 13 9 8 4 7 6 0 3 2 0 1 0 2 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 ] All Non-Zero Cycle SW Prefetch Requests ------------------------------------ @@ -103,7 +122,7 @@ page_size: 4096 user_time: 0 system_time: 0 -page_reclaims: 8779 +page_reclaims: 9003 page_faults: 0 swaps: 0 block_inputs: 0 @@ -112,6 +131,12 @@ Network Stats ------------- +total_msg_count_Control: 2871 22968 +total_msg_count_Data: 2862 206064 +total_msg_count_Response_Data: 2870 206640 +total_msg_count_Writeback_Control: 2861 22888 +total_msgs: 11464 total_bytes: 458560 + switch_0_inlinks: 2 switch_0_outlinks: 2 links_utilized_percent_switch_0: 0.106147 @@ -145,59 +170,59 @@ outgoing_messages_switch_2_link_1_Control: 957 7656 [ 0 0 957 0 0 0 0 0 0 0 ] base_latency: 1 outgoing_messages_switch_2_link_1_Data: 954 68688 [ 0 0 954 0 0 0 0 0 0 0 ] base_latency: 1 -Cache Stats: system.ruby.network.topology.ext_links0.ext_node.sequencer.icache - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_misses: 957 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_demand_misses: 957 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_sw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_total_hw_prefetches: 0 +Cache Stats: system.l1_cntrl0.sequencer.icache + system.l1_cntrl0.sequencer.icache_total_misses: 957 + system.l1_cntrl0.sequencer.icache_total_demand_misses: 957 + system.l1_cntrl0.sequencer.icache_total_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_sw_prefetches: 0 + system.l1_cntrl0.sequencer.icache_total_hw_prefetches: 0 - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_LD: 10.2403% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_type_ST: 89.7597% + system.l1_cntrl0.sequencer.icache_request_type_LD: 4.91118% + system.l1_cntrl0.sequencer.icache_request_type_ST: 89.7597% + system.l1_cntrl0.sequencer.icache_request_type_IFETCH: 5.32915% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_access_mode_type_SupervisorMode: 957 100% - system.ruby.network.topology.ext_links0.ext_node.sequencer.icache_request_size: [binsize: 1 max: 4 count: 957 average: 1.30721 | standard deviation: 0.910193 | 0 859 0 0 98 ] + system.l1_cntrl0.sequencer.icache_access_mode_type_SupervisorMode: 957 100% - --- L1Cache 0 --- + --- L1Cache --- - Event Counts - -Load 100 -Ifetch 0 -Store 900 -Data 956 -Fwd_GETX 0 -Inv 0 -Replacement 954 -Writeback_Ack 953 -Writeback_Nack 0 +Load [48 ] 48 +Ifetch [52 ] 52 +Store [900 ] 900 +Data [956 ] 956 +Fwd_GETX [0 ] 0 +Inv [0 ] 0 +Replacement [954 ] 954 +Writeback_Ack [953 ] 953 +Writeback_Nack [0 ] 0 - Transitions - -I Load 98 -I Ifetch 0 <-- -I Store 859 -I Inv 0 <-- -I Replacement 0 <-- +I Load [47 ] 47 +I Ifetch [51 ] 51 +I Store [859 ] 859 +I Inv [0 ] 0 +I Replacement [0 ] 0 -II Writeback_Nack 0 <-- +II Writeback_Nack [0 ] 0 -M Load 2 -M Ifetch 0 <-- -M Store 41 -M Fwd_GETX 0 <-- -M Inv 0 <-- -M Replacement 954 +M Load [1 ] 1 +M Ifetch [1 ] 1 +M Store [41 ] 41 +M Fwd_GETX [0 ] 0 +M Inv [0 ] 0 +M Replacement [954 ] 954 -MI Fwd_GETX 0 <-- -MI Inv 0 <-- -MI Writeback_Ack 953 -MI Writeback_Nack 0 <-- +MI Fwd_GETX [0 ] 0 +MI Inv [0 ] 0 +MI Writeback_Ack [953 ] 953 +MI Writeback_Nack [0 ] 0 -MII Fwd_GETX 0 <-- +MII Fwd_GETX [0 ] 0 -IS Data 98 +IS Data [98 ] 98 -IM Data 858 +IM Data [858 ] 858 -Memory controller: system.ruby.network.topology.ext_links1.ext_node.memBuffer: +Memory controller: system.dir_cntrl0.memBuffer: memory_total_requests: 1911 memory_reads: 957 memory_writes: 954 @@ -217,70 +242,69 @@ memory_stalls_for_read_read_turnaround: 112 accesses_per_bank: 52 59 44 109 131 76 66 52 64 66 66 44 56 54 54 52 52 48 76 50 48 60 56 48 50 62 66 48 36 64 48 54 - --- Directory 0 --- + --- Directory --- - Event Counts - -GETX 957 -GETS 0 -PUTX 954 -PUTX_NotOwner 0 -DMA_READ 0 -DMA_WRITE 0 -Memory_Data 957 -Memory_Ack 954 +GETX [957 ] 957 +GETS [0 ] 0 +PUTX [954 ] 954 +PUTX_NotOwner [0 ] 0 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [957 ] 957 +Memory_Ack [954 ] 954 - Transitions - -I GETX 957 -I PUTX_NotOwner 0 <-- -I DMA_READ 0 <-- -I DMA_WRITE 0 <-- +I GETX [957 ] 957 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 -M GETX 0 <-- -M PUTX 954 -M PUTX_NotOwner 0 <-- -M DMA_READ 0 <-- -M DMA_WRITE 0 <-- +M GETX [0 ] 0 +M PUTX [954 ] 954 +M PUTX_NotOwner [0 ] 0 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 -M_DRD GETX 0 <-- -M_DRD PUTX 0 <-- +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 -M_DWR GETX 0 <-- -M_DWR PUTX 0 <-- +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 -M_DWRI GETX 0 <-- -M_DWRI Memory_Ack 0 <-- +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 -M_DRDI GETX 0 <-- -M_DRDI Memory_Ack 0 <-- +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 -IM GETX 0 <-- -IM GETS 0 <-- -IM PUTX 0 <-- -IM PUTX_NotOwner 0 <-- -IM DMA_READ 0 <-- -IM DMA_WRITE 0 <-- -IM Memory_Data 957 +IM GETX [0 ] 0 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [957 ] 957 -MI GETX 0 <-- -MI GETS 0 <-- -MI PUTX 0 <-- -MI PUTX_NotOwner 0 <-- -MI DMA_READ 0 <-- -MI DMA_WRITE 0 <-- -MI Memory_Ack 954 +MI GETX [0 ] 0 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [954 ] 954 -ID GETX 0 <-- -ID GETS 0 <-- -ID PUTX 0 <-- -ID PUTX_NotOwner 0 <-- -ID DMA_READ 0 <-- -ID DMA_WRITE 0 <-- -ID Memory_Data 0 <-- +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 -ID_W GETX 0 <-- -ID_W GETS 0 <-- -ID_W PUTX 0 <-- -ID_W PUTX_NotOwner 0 <-- -ID_W DMA_READ 0 <-- -ID_W DMA_WRITE 0 <-- -ID_W Memory_Ack 0 <-- - +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack \ No newline at end of file diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/simout Wed Aug 11 14:38:35 2010 -0700 @@ -1,3 +1,5 @@ +Redirecting stdout to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simout +Redirecting stderr to build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby/simerr M5 Simulator System Copyright (c) 2001-2008 @@ -5,10 +7,10 @@ All Rights Reserved -M5 compiled Mar 18 2010 13:52:42 -M5 revision 6a6bb24e484f 7041 default qtip tip brad/regress_updates -M5 started Mar 18 2010 13:52:46 -M5 executing on cabr0210 +M5 compiled Aug 4 2010 17:29:21 +M5 revision 1cd2a169499f+ 7535+ default brad/hammer_merge_gets qtip tip +M5 started Aug 5 2010 10:10:57 +M5 executing on SC2B0617 command line: build/ALPHA_SE/m5.fast -d build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby -re tests/run.py build/ALPHA_SE/tests/fast/quick/60.rubytest/alpha/linux/rubytest-ruby Global frequency set at 1000000000 ticks per second info: Entering event queue @ 0. Starting simulation... diff -r 0bc82be9c82f -r 7a8f4a18013d tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt --- a/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt Wed Aug 11 14:38:31 2010 -0700 +++ b/tests/quick/60.rubytest/ref/alpha/linux/rubytest-ruby/stats.txt Wed Aug 11 14:38:35 2010 -0700 @@ -1,8 +1,8 @@ ---------- Begin Simulation Statistics ---------- -host_mem_usage 208288 # Number of bytes of host memory used -host_seconds 0.10 # Real time elapsed on the host -host_tick_rate 2919378 # Simulator tick rate (ticks/s) +host_mem_usage 208596 # Number of bytes of host memory used +host_seconds 0.09 # Real time elapsed on the host +host_tick_rate 3195386 # Simulator tick rate (ticks/s) sim_freq 1000000000 # Frequency of simulated ticks sim_seconds 0.000281 # Number of seconds simulated sim_ticks 281031 # Number of ticks simulated