diff -r f681719e2e99 build_opts/ARM_MESI_CMP_directory --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/build_opts/ARM_MESI_CMP_directory Sat May 12 19:24:11 2012 -0400 @@ -0,0 +1,3 @@ +TARGET_ISA = 'arm' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MESI_CMP_directory' diff -r f681719e2e99 build_opts/ARM_MOESI_CMP_directory --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/build_opts/ARM_MOESI_CMP_directory Sat May 12 19:24:11 2012 -0400 @@ -0,0 +1,3 @@ +TARGET_ISA = 'arm' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MOESI_CMP_directory' diff -r f681719e2e99 build_opts/ARM_MOESI_CMP_token --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/build_opts/ARM_MOESI_CMP_token Sat May 12 19:24:11 2012 -0400 @@ -0,0 +1,3 @@ +TARGET_ISA = 'arm' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MOESI_CMP_token' diff -r f681719e2e99 build_opts/ARM_MOESI_hammer --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/build_opts/ARM_MOESI_hammer Sat May 12 19:24:11 2012 -0400 @@ -0,0 +1,3 @@ +TARGET_ISA = 'arm' +CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' +PROTOCOL = 'MOESI_hammer' diff -r f681719e2e99 configs/common/Benchmarks.py --- a/configs/common/Benchmarks.py Thu May 10 18:04:29 2012 -0500 +++ b/configs/common/Benchmarks.py Sat May 12 19:24:11 2012 -0400 @@ -113,6 +113,10 @@ 'MutexTest': [SysConfig('mutex-test.rcS', '128MB')], 'ArmAndroid': [SysConfig('null.rcS', '256MB', 'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.clean.img')], + 'ArmUbuntu': [SysConfig('null.rcS', '256MB', + 'arm-ubuntu-natty-headless.img')], + 'ArmUbuntuRuby': [SysConfig('null.rcS', '172MB', + 'arm-ubuntu-natty-headless.img')], 'bbench': [SysConfig('bbench.rcS', '256MB', 'ARMv7a-Gingerbread-Android.SMP.mouse.nolock.img')] } diff -r f681719e2e99 configs/common/FSConfig.py --- a/configs/common/FSConfig.py Thu May 10 18:04:29 2012 -0500 +++ b/configs/common/FSConfig.py Sat May 12 19:24:11 2012 -0400 @@ -308,6 +308,91 @@ return self +def makeArmRubySystem(mem_mode, machine_type, mdesc = None, bare_metal=False): + assert machine_type + + if bare_metal: + self = ArmSystem() + else: + self = LinuxArmSystem() + + if not mdesc: + # generic system + mdesc = SysConfig() + + self.readfile = mdesc.script() + self.piobus = Bus(bus_id=0) + + self.mem_mode = mem_mode + + if machine_type == "RealView_PBX": + self.realview = RealViewPBX() + elif machine_type == "RealView_EB": + self.realview = RealViewEB() + elif machine_type == "VExpress_ELT": + self.realview = VExpress_ELT() + elif machine_type == "VExpress_EMM": + self.realview = VExpress_EMM() + self.load_addr_mask = 0xffffffff + else: + print "Unknown Machine Type" + sys.exit(1) + + self.cf0 = CowIdeDisk(driveID='master') + self.cf0.childImage(mdesc.disk()) + + # default to an IDE controller rather than a CF one + # assuming we've got one + try: + self.realview.ide.disks = [self.cf0] + except: + self.realview.cf_ctrl.disks = [self.cf0] + + if bare_metal: + # EOT character on UART will end the simulation + self.realview.uart.end_on_eot = True + self.physmem = SimpleMemory(range = AddrRange(Addr(mdesc.mem())), + zero = True) + else: + self.kernel = binary('vmlinux.arm.smp.fb.2.6.38.8') + self.machine_type = machine_type + + boot_flags = 'earlyprintk console=ttyAMA0 lpj=19988480 norandmaps ' + \ + 'rw loglevel=8 mem=%s root=/dev/sda1' % mdesc.mem() + + self.gic_cpu_addr = self.realview.gic.cpu_addr + self.flags_addr = self.realview.realview_io.pio_addr + 0x30 + + if mdesc.disk().lower().count('android'): + boot_flags += " init=/init " + self.boot_osflags = boot_flags + + self.physmem = SimpleMemory(range = + AddrRange(self.realview.mem_start_addr, + size = mdesc.mem()), + conf_table_reported = True) + self.realview.setupBootLoaderRuby(self.piobus, self, binary) + if convert.toMemorySize(mdesc.mem()) > int(self.realview.max_mem_size): + print "The currently selected ARM platforms doesn't support" + print " the amount of DRAM you've selected. Please try" + print " another platform" + sys.exit(1) + self.piobus.master = self.physmem.port + self.realview.attachOnChipIORuby(self.piobus) + + # + # Store the dma devices for later connection to dma ruby ports. + # Append an underscore to dma_devices to avoid the SimObjectVector check. + # + self._dma_ports = [self.realview.cf_ctrl.dma, self.realview.clcd.dma] + self.realview.attachIORuby(self.piobus, self._dma_ports) + + self.intrctrl = IntrControl() + self.terminal = Terminal() + self.vncserver = VncServer() + + return self + def makeLinuxMipsSystem(mem_mode, mdesc = None): class BaseMalta(Malta): diff -r f681719e2e99 configs/example/ruby_fs.py --- a/configs/example/ruby_fs.py Thu May 10 18:04:29 2012 -0500 +++ b/configs/example/ruby_fs.py Sat May 12 19:24:11 2012 -0400 @@ -74,7 +74,8 @@ bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] # Check for timing mode because ruby does not support atomic accesses -if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): +if not (options.cpu_type == "detailed" or options.cpu_type == "timing" or + (options.cpu_type == "arm_detailed" and buildEnv['TARGET_ISA'] == "arm")): print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" sys.exit(1) (CPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) @@ -86,6 +87,11 @@ elif buildEnv['TARGET_ISA'] == "x86": system = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], True) Simulation.setWorkCountOptions(system, options) +elif buildEnv['TARGET_ISA'] == "arm": + system = makeArmRubySystem(test_mem_mode, + options.machine_type, bm[0], + bare_metal=options.bare_metal) + Simulation.setWorkCountOptions(system, options) else: fatal("incapable of building non-alpha or non-x86 full system!") @@ -111,6 +117,9 @@ cpu.interrupts.pio = system.piobus.master cpu.interrupts.int_master = system.piobus.slave cpu.interrupts.int_slave = system.piobus.master + if buildEnv['TARGET_ISA'] == "arm": + cpu.itb.walker.port = system.ruby._cpu_ruby_ports[i].slave + cpu.dtb.walker.port = system.ruby._cpu_ruby_ports[i].slave root = Root(full_system = True, system = system) Simulation.run(options, root, system, FutureClass) diff -r f681719e2e99 src/dev/arm/RealView.py --- a/src/dev/arm/RealView.py Thu May 10 18:04:29 2012 -0500 +++ b/src/dev/arm/RealView.py Sat May 12 19:24:11 2012 -0400 @@ -145,6 +145,14 @@ mem_start_addr = Param.Addr(0, "Start address of main memory") max_mem_size = Param.Addr('256MB', "Maximum amount of RAM supported by platform") + def setupBootLoaderRuby(self, mem_bus, cur_sys, loc): + max_mem_size = Param.Addr('172MB', "Maximum amount of RAM supported by platform with Ruby") + self.nvmem = SimpleMemory(range = AddrRange(Addr('172MB'), + size = '64MB'), + zero = True) + self.nvmem.port = mem_bus.master + cur_sys.boot_loader = loc('boot_ruby.arm') + def setupBootLoader(self, mem_bus, cur_sys, loc): self.nvmem = SimpleMemory(range = AddrRange(Addr('2GB'), size = '64MB'), @@ -209,6 +217,48 @@ self.flash_fake.pio_addr + \ self.flash_fake.pio_size - 1)] + # Attach I/O devices that are on chip and also set the appropriate + # ranges for the bridge + def attachOnChipIORuby(self, bus): + self.gic.pio = bus.master + self.l2x0_fake.pio = bus.master + self.a9scu.pio = bus.master + self.local_cpu_timer.pio = bus.master + + # Attach I/O devices to specified bus object. Can't do this + # earlier, since the bus object itself is typically defined at the + # System level. + def attachIORuby(self, bus, dma_ports): + self.uart.pio = bus.master + self.realview_io.pio = bus.master + self.timer0.pio = bus.master + self.timer1.pio = bus.master + self.clcd.pio = bus.master + if dma_ports.count(self.clcd.dma) == 0: + self.clcd.dma = bus.slave + self.kmi0.pio = bus.master + self.kmi1.pio = bus.master + self.cf_ctrl.pio = bus.master + self.cf_ctrl.config = bus.master + if dma_ports.count(self.cf_ctrl.dma) == 0: + self.cf_ctrl.dma = bus.slave + self.dmac_fake.pio = bus.master + self.uart1_fake.pio = bus.master + self.uart2_fake.pio = bus.master + self.uart3_fake.pio = bus.master + self.smc_fake.pio = bus.master + self.sp810_fake.pio = bus.master + self.watchdog_fake.pio = bus.master + self.gpio0_fake.pio = bus.master + self.gpio1_fake.pio = bus.master + self.gpio2_fake.pio = bus.master + self.ssp_fake.pio = bus.master + self.sci_fake.pio = bus.master + self.aaci_fake.pio = bus.master + self.mmc_fake.pio = bus.master + self.rtc.pio = bus.master + self.flash_fake.pio = bus.master + # Attach I/O devices to specified bus object. Can't do this # earlier, since the bus object itself is typically defined at the # System level. diff -r f681719e2e99 system/arm/simple_bootloader/Makefile --- a/system/arm/simple_bootloader/Makefile Thu May 10 18:04:29 2012 -0500 +++ b/system/arm/simple_bootloader/Makefile Sat May 12 19:24:11 2012 -0400 @@ -53,11 +53,13 @@ boot.arm: boot.o $(LD) -o $@ -N -Ttext 0x80000000 $< -non_shared -static +boot_ruby.arm: boot.o + $(LD) -o $@ -N -Ttext 0x0C000000 $< -non_shared -static boot_emm.arm: boot.o $(LD) -o $@ -N -Ttext 0x00000010 $< -non_shared -static clean: - $(RM) -f *.o boot.arm boot_emm.arm + $(RM) -f *.o boot.arm boot_ruby.arm boot_emm.arm .PHONY: all clean