diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/config.ini @@ -0,0 +1,1887 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer workload +BTBEntries=4096 +BTBTagSize=16 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+opClass=SimdFloatAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu3.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu3.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu3.fuPool.FUList6.opList + +[system.cpu3.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 + +[system.cpu3.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu3.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu3.fuPool.FUList8.opList + +[system.cpu3.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/simout @@ -0,0 +1,16 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 15:43:33 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/o3-timing-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/o3-timing-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Init done +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +Exiting @ tick 518611500 because user interrupt received diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/skip b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/skip diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/o3-timing-mp/stats.txt @@ -0,0 +1,2119 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000519 # Number of seconds simulated +sim_ticks 518611500 # Number of ticks simulated +final_tick 518611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 85981 # Simulator instruction rate (inst/s) +host_op_rate 122404 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 11790614 # Simulator tick rate (ticks/s) +host_mem_usage 280580 # Number of bytes of host memory used +host_seconds 43.99 # Real time elapsed on the host +sim_insts 3781861 # Number of instructions simulated +sim_ops 5383942 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 40384 # Number of bytes read from this memory +system.physmem.bytes_inst_read 26432 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 631 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 77869465 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 50966861 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 77869465 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 26 # Number of system calls +system.cpu0.numCycles 1037224 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.BPredUnit.lookups 253797 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 253797 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 545 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 253287 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 251264 # Number of BTB hits +system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 9644 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 1268314 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 253797 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 251264 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 254828 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 2605 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 756753 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 19 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 96 # Number of stall cycles due to pending traps +system.cpu0.fetch.IcacheWaitRetryStallCycles 14 # Number of stall cycles due to full MSHR +system.cpu0.fetch.CacheLines 1772 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 305 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 1023378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.741121 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 3.027650 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 768646 75.11% 75.11% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 161 0.02% 75.12% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 158 0.02% 75.14% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 317 0.03% 75.17% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 141 0.01% 75.18% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 173 0.02% 75.20% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 186 0.02% 75.22% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 250916 24.52% 99.74% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 2680 0.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 1023378 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.244689 # Number of branch fetches per cycle +system.cpu0.fetch.rate 1.222797 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 260350 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 506442 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 3764 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 250798 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2024 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 1780701 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2024 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 260767 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 2998 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 1215 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 254107 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 502267 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 1779248 # Number of instructions processed by rename +system.cpu0.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full +system.cpu0.rename.IQFullEvents 250720 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 251426 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.RenamedOperands 1527293 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 4563494 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 4563494 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 1512748 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 14468 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 26 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 26 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 1005120 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 503757 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 252556 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 501730 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 250946 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 1776349 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 130 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 1771791 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 107 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 12227 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 16511 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 80 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 1023378 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 1.731316 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.489085 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 265765 25.97% 25.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 252332 24.66% 50.63% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 251730 24.60% 75.22% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 751 0.07% 75.30% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 251378 24.56% 99.86% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 627 0.06% 99.92% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 521 0.05% 99.97% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 219 0.02% 99.99% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 55 0.01% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 1023378 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 112 58.64% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 58.64% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 43 22.51% 81.15% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 36 18.85% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 165 0.01% 0.01% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 1016427 57.37% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.38% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 503156 28.40% 85.77% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 252043 14.23% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 1771791 # Type of FU issued +system.cpu0.iq.rate 1.708205 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 191 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.000108 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 4567256 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 1788724 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 1770398 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 1771817 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 250725 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 1520 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 21 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 988 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 5 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 2024 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 2138 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 52 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 1776479 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 54 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 503757 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 252556 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 25 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 16 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 21 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 56 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 641 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 697 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 1770801 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 502992 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 988 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 0 # number of nop insts executed +system.cpu0.iew.exec_refs 754939 # number of memory reference insts executed +system.cpu0.iew.exec_branches 252120 # Number of branches executed +system.cpu0.iew.exec_stores 251947 # Number of stores executed +system.cpu0.iew.exec_rate 1.707250 # Inst execution rate +system.cpu0.iew.wb_sent 1770575 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 1770398 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 1263709 # num instructions producing a value +system.cpu0.iew.wb_consumers 1518568 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 1.706862 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.832171 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitCommittedInsts 1258161 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 1763667 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 12728 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 50 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 560 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 1021354 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 1.726793 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.310117 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 265791 26.02% 26.02% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 252204 24.69% 50.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 679 0.07% 50.78% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 501850 49.14% 99.92% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 325 0.03% 99.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 166 0.02% 99.97% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 117 0.01% 99.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 53 0.01% 99.98% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 169 0.02% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 1021354 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 1258161 # Number of instructions committed +system.cpu0.commit.committedOps 1763667 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 753768 # Number of memory references committed +system.cpu0.commit.loads 502212 # Number of loads committed +system.cpu0.commit.membars 34 # Number of memory barriers committed +system.cpu0.commit.branches 251717 # Number of branches committed +system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 1763606 # Number of committed integer instructions. +system.cpu0.commit.function_calls 0 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 169 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 2797580 # The number of ROB reads +system.cpu0.rob.rob_writes 3554927 # The number of ROB writes +system.cpu0.timesIdled 172 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 13846 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 1258161 # Number of Instructions Simulated +system.cpu0.committedOps 1763667 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 1258161 # Number of Instructions Simulated +system.cpu0.cpi 0.824397 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.824397 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.213008 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.213008 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 3281218 # number of integer regfile reads +system.cpu0.int_regfile_writes 1518949 # number of integer regfile writes +system.cpu0.misc_regfile_reads 1260361 # number of misc regfile reads +system.cpu0.icache.replacements 83 # number of replacements +system.cpu0.icache.tagsinuse 250.272513 # Cycle average of tags in use +system.cpu0.icache.total_refs 1337 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 337 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 3.967359 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 250.272513 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.488814 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.488814 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 1337 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 1337 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 1337 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 1337 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 1337 # number of overall hits +system.cpu0.icache.overall_hits::total 1337 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 435 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 435 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 435 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 435 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 435 # number of overall misses +system.cpu0.icache.overall_misses::total 435 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 21648500 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 21648500 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 21648500 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 21648500 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 21648500 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 21648500 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 1772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 1772 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 1772 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 1772 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 1772 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 1772 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.245485 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.245485 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.245485 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 49766.666667 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 49766.666667 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 49766.666667 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 52500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 5 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 10500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 98 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 98 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 98 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 98 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 98 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 98 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 337 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 337 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 337 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 337 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 337 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 337 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 16894000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 16894000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 16894000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 16894000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 16894000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 16894000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.190181 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.190181 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.190181 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 50130.563798 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 50130.563798 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 50130.563798 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 1 # number of replacements +system.cpu0.dcache.tagsinuse 130.668680 # Cycle average of tags in use +system.cpu0.dcache.total_refs 497592 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 133 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 3741.293233 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 130.668680 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.255212 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.255212 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 252076 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 252076 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 251475 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 251475 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 503551 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 503551 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 503551 # number of overall hits +system.cpu0.dcache.overall_hits::total 503551 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 142 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 142 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 80 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 80 # number of WriteReq misses +system.cpu0.dcache.demand_misses::cpu0.data 222 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 222 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 222 # number of overall misses +system.cpu0.dcache.overall_misses::total 222 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 7226000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 7226000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 4420000 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 4420000 # number of WriteReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 11646000 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 11646000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 11646000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 11646000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 252218 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 252218 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 251555 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 251555 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 503773 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 503773 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 503773 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 503773 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.000563 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.000318 # miss rate for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.000441 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.000441 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 50887.323944 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 55250 # average WriteReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 52459.459459 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 52459.459459 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 27000 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 27000 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 54 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 54 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 1 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 55 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 55 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 55 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 55 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 88 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 88 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 79 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 79 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 167 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 167 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 167 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 167 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4337000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4337000 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4126000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4126000 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 8463000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 8463000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 8463000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 8463000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.000349 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.000314 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.000331 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.000331 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 49284.090909 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 52227.848101 # average WriteReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 50676.646707 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 50676.646707 # average overall mshr miss latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 1005154 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.BPredUnit.lookups 250515 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 250515 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 442 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 249600 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 248070 # Number of BTB hits +system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 4760 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 1250885 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 250515 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 248070 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 251262 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 2262 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 743397 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 17 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.PendingTrapStallCycles 94 # Number of stall cycles due to pending traps +system.cpu1.fetch.IcacheWaitRetryStallCycles 11 # Number of stall cycles due to full MSHR +system.cpu1.fetch.CacheLines 1556 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 187 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 1001340 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.755330 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 3.035733 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 750104 74.91% 74.91% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 126 0.01% 74.92% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 128 0.01% 74.94% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 146 0.01% 74.95% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 255 0.03% 74.98% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 302 0.03% 75.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 194 0.02% 75.02% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 247512 24.72% 99.74% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 2573 0.26% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 1001340 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.249230 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.244471 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 252503 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 495981 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 3579 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 247478 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 1799 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 1756456 # Number of instructions handled by decode +system.cpu1.decode.SquashedInsts 1 # Number of squashed instructions handled by decode +system.cpu1.rename.SquashCycles 1799 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 252903 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 341 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 362 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 250652 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 495283 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 1755048 # Number of instructions processed by rename +system.cpu1.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu1.rename.IQFullEvents 247654 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 247536 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 1507438 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 4504231 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 4504167 # Number of integer rename lookups +system.cpu1.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu1.rename.CommittedMaps 1493496 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 13864 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 9 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 991422 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 497554 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 248839 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 495084 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 247586 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 1752275 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 133 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 1747837 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 110 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 11095 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 16390 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 1001340 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.745498 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.487154 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 254465 25.41% 25.41% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 248192 24.79% 50.20% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 248371 24.80% 75.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 708 0.07% 75.07% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 248182 24.78% 99.86% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 725 0.07% 99.93% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 495 0.05% 99.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 160 0.02% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 42 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 1001340 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 53 38.69% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.69% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 63 45.99% 84.67% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 21 15.33% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 107 0.01% 0.01% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 1002562 57.36% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 57.37% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 496832 28.43% 85.79% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 248336 14.21% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 1747837 # Type of FU issued +system.cpu1.iq.rate 1.738875 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 137 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.000078 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 4497234 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 1763480 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 1746617 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 26 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 1747857 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 10 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 247419 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 1769 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 1 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 11 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 835 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 1799 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 202 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 21 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 1752408 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 48 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 497554 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 248839 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 8 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 11 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 63 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 498 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 561 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 1747090 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 496704 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 746 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 0 # number of nop insts executed +system.cpu1.iew.exec_refs 744946 # number of memory reference insts executed +system.cpu1.iew.exec_branches 248889 # Number of branches executed +system.cpu1.iew.exec_stores 248242 # Number of stores executed +system.cpu1.iew.exec_rate 1.738132 # Inst execution rate +system.cpu1.iew.wb_sent 1746847 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 1746621 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 1247869 # num instructions producing a value +system.cpu1.iew.wb_consumers 1500897 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 1.737665 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.831415 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitCommittedInsts 1241597 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 1740834 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 11492 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 30 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 456 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 999541 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 1.741633 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.308570 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 254538 25.47% 25.47% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 248319 24.84% 50.31% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 313 0.03% 50.34% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 495280 49.55% 99.89% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 425 0.04% 99.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 236 0.02% 99.96% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 108 0.01% 99.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 55 0.01% 99.97% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 267 0.03% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 999541 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 1241597 # Number of instructions committed +system.cpu1.commit.committedOps 1740834 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 743755 # Number of memory references committed +system.cpu1.commit.loads 495762 # Number of loads committed +system.cpu1.commit.membars 26 # Number of memory barriers committed +system.cpu1.commit.branches 248519 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 1740797 # Number of committed integer instructions. +system.cpu1.commit.function_calls 0 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 267 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 2751600 # The number of ROB reads +system.cpu1.rob.rob_writes 3506555 # The number of ROB writes +system.cpu1.timesIdled 67 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 3814 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 32068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 1241597 # Number of Instructions Simulated +system.cpu1.committedOps 1740834 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 1241597 # Number of Instructions Simulated +system.cpu1.cpi 0.809565 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.809565 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.235231 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.235231 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 3239121 # number of integer regfile reads +system.cpu1.int_regfile_writes 1499099 # number of integer regfile writes +system.cpu1.fp_regfile_reads 4 # number of floating regfile reads +system.cpu1.misc_regfile_reads 1243410 # number of misc regfile reads +system.cpu1.icache.replacements 24 # number of replacements +system.cpu1.icache.tagsinuse 134.917866 # Cycle average of tags in use +system.cpu1.icache.total_refs 1360 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 164 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 8.292683 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 134.917866 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.263511 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.263511 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 1360 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 1360 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 1360 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 1360 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 1360 # number of overall hits +system.cpu1.icache.overall_hits::total 1360 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 196 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 196 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 196 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 196 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 196 # number of overall misses +system.cpu1.icache.overall_misses::total 196 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 7380499 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 7380499 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 7380499 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 7380499 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 7380499 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 7380499 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 1556 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 1556 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 1556 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 1556 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 1556 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 1556 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.125964 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.125964 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.125964 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 37655.607143 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 37655.607143 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 37655.607143 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 24500 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 3 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs 8166.666667 # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 32 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 32 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 32 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 32 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 164 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 164 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 164 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 164 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 164 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 164 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 5903500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 5903500 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 5903500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 5903500 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 5903500 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 5903500 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.105398 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.105398 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.105398 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 35996.951220 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 35996.951220 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 35996.951220 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 39.642273 # Cycle average of tags in use +system.cpu1.dcache.total_refs 494421 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 41 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 12059.048780 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 39.642273 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.077426 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.077426 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 249155 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 249155 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 247955 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 247955 # number of WriteReq hits +system.cpu1.dcache.demand_hits::cpu1.data 497110 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 497110 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 497110 # number of overall hits +system.cpu1.dcache.overall_hits::total 497110 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 68 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 68 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 37 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 37 # number of WriteReq misses +system.cpu1.dcache.demand_misses::cpu1.data 105 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 105 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 105 # number of overall misses +system.cpu1.dcache.overall_misses::total 105 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 1972500 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 1972500 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1345000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1345000 # number of WriteReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 3317500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 3317500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 3317500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 3317500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 249223 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 249223 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 247992 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 247992 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 497215 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 497215 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 497215 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 497215 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.000273 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.000149 # miss rate for WriteReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.000211 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.000211 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 29007.352941 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 36351.351351 # average WriteReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 31595.238095 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 31595.238095 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 21 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 21 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 1 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 1 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 22 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 22 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 47 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 47 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 36 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 36 # number of WriteReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 83 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 83 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 83 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 83 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1121500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1121500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1182500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1182500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2304000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2304000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2304000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2304000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.000189 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.000145 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.000167 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.000167 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 23861.702128 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 32847.222222 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 27759.036145 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 27759.036145 # average overall mshr miss latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.numCycles 20619 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.BPredUnit.lookups 14129 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 14129 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 237 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 13853 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 12897 # Number of BTB hits +system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 2984 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 32097 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 14129 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12897 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 14508 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 1263 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 1089 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 34 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.PendingTrapStallCycles 207 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 706 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 111 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 19809 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 4.472563 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.786414 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 5311 26.81% 26.81% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 66 0.33% 27.14% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 54 0.27% 27.42% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 68 0.34% 27.76% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 86 0.43% 28.19% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 117 0.59% 28.78% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 12747 64.35% 93.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 72 0.36% 93.50% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 1288 6.50% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 19809 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.685242 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.556671 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 3154 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 1232 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 14336 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 100 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 987 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 88014 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 987 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 3367 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 593 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 239 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 14218 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 405 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 87347 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 88 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 250 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 86731 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 201908 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 201844 # Number of integer rename lookups +system.cpu2.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu2.rename.CommittedMaps 79898 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 6833 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 10 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 1325 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 14095 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 826 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 308 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 209 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 85928 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 143 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 83545 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 62 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 5908 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 8676 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 121 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 19809 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 4.217527 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 2.611272 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 4732 23.89% 23.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 579 2.92% 26.81% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 497 2.51% 29.32% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 355 1.79% 31.11% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 393 1.98% 33.10% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 296 1.49% 34.59% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 12868 64.96% 99.55% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 65 0.33% 99.88% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 24 0.12% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 19809 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 37 42.53% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 42.53% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 32 36.78% 79.31% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 18 20.69% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 120 0.14% 0.14% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 69232 82.87% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 83.01% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 13673 16.37% 99.38% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 520 0.62% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 83545 # Type of FU issued +system.cpu2.iq.rate 4.051845 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 87 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.001041 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 187022 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 91955 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 82921 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 26 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 83502 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 10 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 98 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 956 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 500 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 987 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 434 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 22 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 86071 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 50 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 14095 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 826 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 9 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 15 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 26 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 284 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 310 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 83189 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 13612 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 356 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 0 # number of nop insts executed +system.cpu2.iew.exec_refs 14078 # number of memory reference insts executed +system.cpu2.iew.exec_branches 13302 # Number of branches executed +system.cpu2.iew.exec_stores 466 # Number of stores executed +system.cpu2.iew.exec_rate 4.034580 # Inst execution rate +system.cpu2.iew.wb_sent 83066 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 82925 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 68179 # num instructions producing a value +system.cpu2.iew.wb_consumers 108630 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 4.021776 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.627626 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitCommittedInsts 27422 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 79964 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 6106 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 22 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 270 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 18822 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 4.248433 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 2.667604 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 4828 25.65% 25.65% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 466 2.48% 28.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 156 0.83% 28.96% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 278 1.48% 30.43% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 172 0.91% 31.35% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 99 0.53% 31.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 12694 67.44% 99.31% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 27 0.14% 99.46% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 102 0.54% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 18822 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 27422 # Number of instructions committed +system.cpu2.commit.committedOps 79964 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 13465 # Number of memory references committed +system.cpu2.commit.loads 13139 # Number of loads committed +system.cpu2.commit.membars 18 # Number of memory barriers committed +system.cpu2.commit.branches 13141 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 79942 # Number of committed integer instructions. +system.cpu2.commit.function_calls 0 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 102 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 104790 # The number of ROB reads +system.cpu2.rob.rob_writes 173132 # The number of ROB writes +system.cpu2.timesIdled 43 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 810 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 32416 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 27422 # Number of Instructions Simulated +system.cpu2.committedOps 79964 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 27422 # Number of Instructions Simulated +system.cpu2.cpi 0.751915 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.751915 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.329938 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.329938 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 149895 # number of integer regfile reads +system.cpu2.int_regfile_writes 82673 # number of integer regfile writes +system.cpu2.fp_regfile_reads 4 # number of floating regfile reads +system.cpu2.misc_regfile_reads 41019 # number of misc regfile reads +system.cpu2.icache.replacements 9 # number of replacements +system.cpu2.icache.tagsinuse 130.851251 # Cycle average of tags in use +system.cpu2.icache.total_refs 543 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 146 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 3.719178 # Average number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.occ_blocks::cpu2.inst 130.851251 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.255569 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.255569 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 543 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 543 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 543 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 543 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 543 # number of overall hits +system.cpu2.icache.overall_hits::total 543 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 163 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 163 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 163 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 163 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 163 # number of overall misses +system.cpu2.icache.overall_misses::total 163 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 2702000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 2702000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 2702000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 2702000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 2702000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 2702000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 706 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 706 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 706 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 706 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 706 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 706 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.230878 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.230878 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.230878 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 16576.687117 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 16576.687117 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 16576.687117 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 17 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 17 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 17 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 17 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 17 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 17 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 146 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 146 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 146 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 146 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 146 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 146 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 2108500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 2108500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 2108500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 2108500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 2108500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 2108500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.206799 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.206799 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.206799 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 14441.780822 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 14441.780822 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 14441.780822 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.replacements 5 # number of replacements +system.cpu2.dcache.tagsinuse 36.372725 # Cycle average of tags in use +system.cpu2.dcache.total_refs 927 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 43 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 21.558140 # Average number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.occ_blocks::cpu2.data 36.372725 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.071040 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.071040 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 13390 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 13390 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 265 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 265 # number of WriteReq hits +system.cpu2.dcache.demand_hits::cpu2.data 13655 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 13655 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 13655 # number of overall hits +system.cpu2.dcache.overall_hits::total 13655 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 85 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 85 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 61 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 61 # number of WriteReq misses +system.cpu2.dcache.demand_misses::cpu2.data 146 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 146 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 146 # number of overall misses +system.cpu2.dcache.overall_misses::total 146 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 1953000 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 1953000 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1436500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1436500 # number of WriteReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 3389500 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 3389500 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 3389500 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 3389500 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 13475 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 13475 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 326 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 326 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 13801 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 13801 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 13801 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 13801 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.006308 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.187117 # miss rate for WriteReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.010579 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.010579 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 22976.470588 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 23549.180328 # average WriteReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 23215.753425 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 23215.753425 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.writebacks::writebacks 2 # number of writebacks +system.cpu2.dcache.writebacks::total 2 # number of writebacks +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 32 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 32 # number of ReadReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 32 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 32 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 32 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 32 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 53 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 53 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 61 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 61 # number of WriteReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 114 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 114 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 114 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 114 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 968500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 968500 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1253500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1253500 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2222000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 2222000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2222000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 2222000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003933 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.187117 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.008260 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.008260 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 18273.584906 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 20549.180328 # average WriteReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 19491.228070 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 19491.228070 # average overall mshr miss latency +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.numCycles 1004502 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.BPredUnit.lookups 260622 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 260622 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 427 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 259754 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 258234 # Number of BTB hits +system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.BPredUnit.usedRAS 0 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.RASInCorrect 0 # Number of incorrect RAS predictions. +system.cpu3.fetch.icacheStallCycles 4095 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 1263704 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 260622 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 258234 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 261385 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 2256 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 736526 # Number of cycles fetch has spent blocked +system.cpu3.fetch.MiscStallCycles 20 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.PendingTrapStallCycles 124 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 1467 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 134 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 1003952 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.808828 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 3.053567 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 742590 73.97% 73.97% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 142 0.01% 73.98% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 122 0.01% 73.99% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 127 0.01% 74.01% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 255 0.03% 74.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 282 0.03% 74.06% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 12809 1.28% 75.33% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 245075 24.41% 99.75% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 2550 0.25% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 1003952 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.259454 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.258040 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 249285 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 491664 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 16111 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 245090 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 1802 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 1814776 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 1802 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 249711 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 807 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 278 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 260764 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 490590 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 1813506 # Number of instructions processed by rename +system.cpu3.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full +system.cpu3.rename.IQFullEvents 245230 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 245239 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 1568191 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 4636415 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 4636351 # Number of integer rename lookups +system.cpu3.rename.fp_rename_lookups 64 # Number of floating rename lookups +system.cpu3.rename.CommittedMaps 1554574 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 13539 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 12 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 982134 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 505228 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 246408 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 490212 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 245162 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 1810793 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 170 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 1806331 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 133 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 10995 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 16240 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 144 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 1003952 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.799220 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.551550 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 251731 25.07% 25.07% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 245796 24.48% 49.56% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 245946 24.50% 74.05% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 732 0.07% 74.13% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 245792 24.48% 98.61% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 683 0.07% 98.68% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 13082 1.30% 99.98% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 148 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 42 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 1003952 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 65 40.12% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.12% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 69 42.59% 82.72% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 28 17.28% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 130 0.01% 0.01% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 1055733 58.45% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.45% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 504532 27.93% 86.38% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 245936 13.62% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 1806331 # Type of FU issued +system.cpu3.iq.rate 1.798235 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 162 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.000090 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 4616882 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 1821938 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 1805149 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 26 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 32 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 4 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 1806353 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 10 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 245037 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 1687 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 15 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 832 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 2 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 1802 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 603 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 27 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 1810963 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 53 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 505228 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 246408 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 20 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 15 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 64 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 471 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 535 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 1805600 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 504397 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 730 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 0 # number of nop insts executed +system.cpu3.iew.exec_refs 750233 # number of memory reference insts executed +system.cpu3.iew.exec_branches 259016 # Number of branches executed +system.cpu3.iew.exec_stores 245836 # Number of stores executed +system.cpu3.iew.exec_rate 1.797508 # Inst execution rate +system.cpu3.iew.wb_sent 1805376 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 1805153 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 1298608 # num instructions producing a value +system.cpu3.iew.wb_consumers 1586992 # num instructions consuming a value +system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu3.iew.wb_rate 1.797063 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.818283 # average fanout of values written-back +system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu3.commit.commitCommittedInsts 1254681 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 1799477 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 11404 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 26 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 444 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 1002150 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 1.795616 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.384123 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 251828 25.13% 25.13% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 245871 24.53% 49.66% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 324 0.03% 49.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 490445 48.94% 98.63% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 406 0.04% 98.68% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 247 0.02% 98.70% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 12703 1.27% 99.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 62 0.01% 99.97% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 264 0.03% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 1002150 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 1254681 # Number of instructions committed +system.cpu3.commit.committedOps 1799477 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 749083 # Number of memory references committed +system.cpu3.commit.loads 503518 # Number of loads committed +system.cpu3.commit.membars 22 # Number of memory barriers committed +system.cpu3.commit.branches 258697 # Number of branches committed +system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 1799444 # Number of committed integer instructions. +system.cpu3.commit.function_calls 0 # Number of function calls committed. +system.cpu3.commit.bw_lim_events 264 # number cycles where commit BW limit reached +system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu3.rob.rob_reads 2812767 # The number of ROB reads +system.cpu3.rob.rob_writes 3623673 # The number of ROB writes +system.cpu3.timesIdled 43 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 550 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 32720 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 1254681 # Number of Instructions Simulated +system.cpu3.committedOps 1799477 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 1254681 # Number of Instructions Simulated +system.cpu3.cpi 0.800604 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.800604 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.249058 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.249058 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 3346045 # number of integer regfile reads +system.cpu3.int_regfile_writes 1559998 # number of integer regfile writes +system.cpu3.fp_regfile_reads 4 # number of floating regfile reads +system.cpu3.misc_regfile_reads 1268948 # number of misc regfile reads +system.cpu3.icache.replacements 18 # number of replacements +system.cpu3.icache.tagsinuse 136.521984 # Cycle average of tags in use +system.cpu3.icache.total_refs 1290 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 161 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 8.012422 # Average number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.occ_blocks::cpu3.inst 136.521984 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.266645 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.266645 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 1290 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 1290 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 1290 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 1290 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 1290 # number of overall hits +system.cpu3.icache.overall_hits::total 1290 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 177 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 177 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 177 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 177 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 177 # number of overall misses +system.cpu3.icache.overall_misses::total 177 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 2623000 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 2623000 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 2623000 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 2623000 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 2623000 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 2623000 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 1467 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 1467 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 1467 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 1467 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 1467 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 1467 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.120654 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.120654 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.120654 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14819.209040 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14819.209040 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14819.209040 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 16 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 16 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 16 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 16 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 16 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 161 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 161 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 161 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 161 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 161 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 161 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 1990000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 1990000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 1990000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 1990000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 1990000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 1990000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.109748 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.109748 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.109748 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12360.248447 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12360.248447 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12360.248447 # average overall mshr miss latency +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.replacements 7 # number of replacements +system.cpu3.dcache.tagsinuse 43.963190 # Cycle average of tags in use +system.cpu3.dcache.total_refs 499595 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 53 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 9426.320755 # Average number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.occ_blocks::cpu3.data 43.963190 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.085866 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.085866 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 259185 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 259185 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 245491 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 245491 # number of WriteReq hits +system.cpu3.dcache.demand_hits::cpu3.data 504676 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 504676 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 504676 # number of overall hits +system.cpu3.dcache.overall_hits::total 504676 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 101 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 101 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 73 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 73 # number of WriteReq misses +system.cpu3.dcache.demand_misses::cpu3.data 174 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 174 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 174 # number of overall misses +system.cpu3.dcache.overall_misses::total 174 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 2483500 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 2483500 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1845500 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1845500 # number of WriteReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 4329000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 4329000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 4329000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 4329000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 259286 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 259286 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 245564 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 245564 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 504850 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 504850 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 504850 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 504850 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.000390 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.000297 # miss rate for WriteReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.000345 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.000345 # miss rate for overall accesses +system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 24589.108911 # average ReadReq miss latency +system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 25280.821918 # average WriteReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 24879.310345 # average overall miss latency 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40026.041667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40214.285714 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40142.857143 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40239.130435 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/config.ini @@ -0,0 +1,579 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[7] + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[3] +pio=system.membus.master[2] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[6] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[9] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[11] + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[8] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[3] +int_slave=system.membus.master[5] +pio=system.membus.master[4] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[10] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[13] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[15] + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/simout @@ -0,0 +1,82 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 15:43:33 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-atomic-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-atomic-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Init done +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +Iteration 1 completed +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +Iteration 3 completed +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=1, now next=2 +Iteration 4 completed +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +Iteration 5 completed +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 6 completed +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +Iteration 7 completed +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 8 completed +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 9 completed +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 10 completed +PASSED :-) +Exiting @ tick 183751000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-atomic-mp/stats.txt @@ -0,0 +1,636 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000184 # Number of seconds simulated +sim_ticks 183751000 # Number of ticks simulated +final_tick 183751000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 750901 # Simulator instruction rate (inst/s) +host_op_rate 1299483 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 194001250 # Simulator tick rate (ticks/s) +host_mem_usage 1193544 # Number of bytes of host memory used +host_seconds 0.95 # Real time elapsed on the host +sim_insts 711190 # Number of instructions simulated +sim_ops 1230795 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 36992 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22784 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 578 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 201315911 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 123993883 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 201315911 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 95 # Number of system calls +system.cpu0.numCycles 367687 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 222464 # Number of instructions committed +system.cpu0.committedOps 320608 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 320353 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 44122 # number of instructions that are conditional controls +system.cpu0.num_int_insts 320353 # number of integer instructions +system.cpu0.num_fp_insts 40 # number of float instructions +system.cpu0.num_int_register_reads 809949 # number of times the integer registers were read +system.cpu0.num_int_register_writes 279252 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 60 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu0.num_mem_refs 129330 # number of memory refs +system.cpu0.num_load_insts 85625 # Number of load instructions +system.cpu0.num_store_insts 43705 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 367687 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.icache.replacements 194 # number of replacements +system.cpu0.icache.tagsinuse 224.430909 # Cycle average of tags in use +system.cpu0.icache.total_refs 269092 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 451 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 596.656319 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 224.430909 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.438342 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.438342 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 269092 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 269092 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 269092 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 269092 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 269092 # number of overall hits +system.cpu0.icache.overall_hits::total 269092 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 451 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 451 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 451 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 451 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 451 # number of overall misses +system.cpu0.icache.overall_misses::total 451 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 269543 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 269543 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 269543 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 269543 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 269543 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 269543 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.001673 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.001673 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.001673 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 3 # number of replacements +system.cpu0.dcache.tagsinuse 137.440330 # Cycle average of tags in use +system.cpu0.dcache.total_refs 87517 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 157 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 557.433121 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 137.440330 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.268438 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.268438 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 85394 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 85394 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 43513 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 43513 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 128907 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 128907 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 128907 # number of overall hits +system.cpu0.dcache.overall_hits::total 128907 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 231 # number of ReadReq misses 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# number of times a function call or return occured +system.cpu2.num_conditional_control_insts 41958 # number of instructions that are conditional controls +system.cpu2.num_int_insts 303225 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 724548 # number of times the integer registers were read +system.cpu2.num_int_register_writes 285591 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 85246 # number of memory refs +system.cpu2.num_load_insts 60807 # Number of load instructions +system.cpu2.num_store_insts 24439 # Number of store instructions +system.cpu2.num_idle_cycles 14864.948534 # Number of idle cycles +system.cpu2.num_busy_cycles 348070.051466 # Number of busy cycles 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number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 215455 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 215455 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 215455 # number of overall hits +system.cpu2.icache.overall_hits::total 215455 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 265 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 265 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 265 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 265 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 265 # number of overall misses +system.cpu2.icache.overall_misses::total 265 # number of overall misses +system.cpu2.icache.ReadReq_accesses::cpu2.inst 215720 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 215720 # number of ReadReq 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of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 186 # number of WriteReq misses +system.cpu2.dcache.demand_misses::cpu2.data 436 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 436 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 436 # number of overall misses +system.cpu2.dcache.overall_misses::total 436 # number of overall misses +system.cpu2.dcache.ReadReq_accesses::cpu2.data 60807 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 60807 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 24439 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 24439 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 85246 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 85246 # number of demand (read+write) accesses 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# number of times a function call or return occured +system.cpu3.num_conditional_control_insts 42324 # number of instructions that are conditional controls +system.cpu3.num_int_insts 302722 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 718827 # number of times the integer registers were read +system.cpu3.num_int_register_writes 287800 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 80176 # number of memory refs +system.cpu3.num_load_insts 58453 # Number of load instructions +system.cpu3.num_store_insts 21723 # Number of store instructions +system.cpu3.num_idle_cycles 14996.378362 # Number of idle cycles +system.cpu3.num_busy_cycles 347940.621638 # Number of busy cycles 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+system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/config.ini @@ -0,0 +1,690 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.cpu0] +type=TimingSimpleCPU +children=dtb interrupts itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl0.sequencer.slave[1] +icache_port=system.l1_cntrl0.sequencer.slave[0] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl0.sequencer.slave[4] +int_slave=system.l1_cntrl0.sequencer.master[1] +pio=system.l1_cntrl0.sequencer.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl1.sequencer.slave[1] +icache_port=system.l1_cntrl1.sequencer.slave[0] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl1.sequencer.slave[3] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl1.sequencer.slave[4] +int_slave=system.l1_cntrl1.sequencer.master[1] +pio=system.l1_cntrl1.sequencer.master[0] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl1.sequencer.slave[2] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl2.sequencer.slave[1] +icache_port=system.l1_cntrl2.sequencer.slave[0] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl2.sequencer.slave[3] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl2.sequencer.slave[4] +int_slave=system.l1_cntrl2.sequencer.master[1] +pio=system.l1_cntrl2.sequencer.master[0] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl2.sequencer.slave[2] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl3.sequencer.slave[1] +icache_port=system.l1_cntrl3.sequencer.slave[0] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl3.sequencer.slave[3] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl3.sequencer.slave[4] +int_slave=system.l1_cntrl3.sequencer.master[1] +pio=system.l1_cntrl3.sequencer.master[0] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl3.sequencer.slave[2] + +[system.cpu3.tracer] +type=ExeTracer + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=4 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.cacheMemory +cache_response_latency=12 +cntrl_id=0 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.l1_cntrl1] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl1.cacheMemory +cache_response_latency=12 +cntrl_id=1 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl1.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 +master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave +slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master + +[system.l1_cntrl2] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl2.cacheMemory +cache_response_latency=12 +cntrl_id=2 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl2.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +master=system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave +slave=system.cpu2.icache_port system.cpu2.dcache_port system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu2.interrupts.int_master + +[system.l1_cntrl3] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl3.cacheMemory +cache_response_latency=12 +cntrl_id=3 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl3.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 +master=system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave +slave=system.cpu3.icache_port system.cpu3.dcache_port system.cpu3.itb.walker.port system.cpu3.dtb.walker.port system.cpu3.interrupts.int_master + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl1 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl2 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.ext_links3] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl3 +int_node=system.ruby.network.topology.routers3 +latency=1 +link_id=3 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers4 +latency=1 +link_id=4 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=6 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=7 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=8 +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=9 +node_a=system.ruby.network.topology.routers4 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers5] +type=BasicRouter +router_id=5 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=4 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +slave=system.system_port + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/ruby.stats --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/ruby.stats @@ -0,0 +1,409 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, ordered +virtual_net_3: active, ordered +virtual_net_4: active, ordered +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: May/16/2012 19:38:35 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 27 +Elapsed_time_in_minutes: 0.45 +Elapsed_time_in_hours: 0.0075 +Elapsed_time_in_days: 0.0003125 + +Virtual_time_in_seconds: 27.4 +Virtual_time_in_minutes: 0.456667 +Virtual_time_in_hours: 0.00761111 +Virtual_time_in_days: 0.00031713 + +Ruby_current_time: 7862696 +Ruby_start_time: 0 +Ruby_cycles: 7862696 + +mbytes_resident: 55.2305 +mbytes_total: 271.43 +resident_ratio: 0.203552 + +ruby_cycles_executed: [ 7862697 7862697 7862697 7862697 ] + +Busy Controller Counts: +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 2097073 average: 1 | standard deviation: 0 | 0 2097073 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 4 max: 453 count: 2097072 average: 13.5017 | standard deviation: 28.8973 | 1730442 0 0 0 0 0 0 0 0 0 0 190908 47734 80003 9046 792 342 403 16 0 2 0 2 1 2 0 5 1 0 2 2 5 6 1 12 2 7 82 77 145 216 229 14059 11322 4807 199 166 553 377 141 10 24 20 21 20 14 23 13 8 14 12 24 13 19 2214 951 1015 190 38 109 50 65 7 1 4 2 4 10 0 4 2 3 0 2 3 1 1 2 0 7 3 4 24 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 453 count: 460188 average: 18.6488 | standard deviation: 36.607 | 347023 0 0 0 0 0 0 0 0 0 0 78965 12204 6702 44 9 7 3 0 0 0 0 0 0 0 0 3 0 0 0 0 1 1 0 3 1 2 17 19 27 61 99 6118 4548 1472 94 55 235 127 49 3 8 11 8 7 7 16 5 3 6 4 8 4 6 672 540 747 62 24 58 16 42 4 1 4 1 3 5 0 4 1 2 0 0 1 0 0 1 0 6 0 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 2 max: 377 count: 139767 average: 12.1535 | standard deviation: 39.2731 | 0 132362 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 7 22 8 5 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 7 3 3 9 44 46 29 15 19 1550 2372 729 718 952 8 30 19 10 12 49 126 26 23 13 3 0 1 1 2 0 2 6 1 1 0 1 3 1 0 3 2 0 4 3 1 6 0 0 3 1 3 0 1 1 145 14 2 2 170 4 1 0 1 22 9 5 2 4 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 1 0 0 3 0 ] +miss_latency_IFETCH: [binsize: 2 max: 379 count: 1495775 average: 11.9962 | standard deviation: 24.3801 | 0 1250256 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111768 31968 3518 72751 537 8630 363 717 66 137 197 12 388 4 11 0 0 1 1 0 0 0 2 0 1 1 1 0 0 2 0 0 1 0 0 2 0 0 2 0 4 2 3 0 1 7 2 1 0 0 5 21 31 17 35 22 39 38 41 52 33 2168 1837 1634 3539 2153 43 35 20 60 27 63 78 75 125 59 11 3 3 7 6 2 5 4 2 4 8 1 2 6 0 1 2 0 1 0 4 1 1 13 0 5 0 2 10 4 1392 165 172 78 17 112 11 9 3 4 16 6 21 11 4 1 1 0 0 0 0 0 1 1 0 5 0 0 0 0 0 0 0 0 1 0 0 2 0 0 0 1 0 0 1 1 0 0 0 0 1 2 0 0 1 14 3 1 0 1 1 0 0 0 0 ] +miss_latency_RMW_Read: [binsize: 2 max: 373 count: 430 average: 158.444 | standard deviation: 77.6656 | 0 74 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 3 1 1 0 1 10 4 2 63 20 174 0 0 1 2 0 1 1 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Locked_RMW_Read: [binsize: 1 max: 177 count: 456 average: 44.6228 | standard deviation: 64.5245 | 0 0 0 271 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 3 8 1 3 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 71 0 5 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 456 average: 3 | standard deviation: 0 | 0 0 0 456 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 1730442 average: 3 | standard deviation: 0 | 0 0 0 1730442 ] +miss_latency_Directory: [binsize: 4 max: 453 count: 37242 average: 185.122 | standard deviation: 31.2103 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 73 76 137 211 218 14055 11319 4799 191 160 552 377 138 9 24 18 21 17 13 21 11 8 12 11 23 13 17 2214 951 1015 190 38 106 50 65 5 1 4 1 4 10 0 4 2 2 0 2 3 1 1 2 0 6 3 3 24 5 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 2 max: 377 count: 329388 average: 49.2682 | standard deviation: 4.18922 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 190908 35378 12356 73096 6907 8677 369 722 70 142 200 15 388 4 12 0 0 1 1 0 0 0 2 0 1 1 1 0 0 2 3 0 1 0 0 2 0 0 2 1 4 3 3 0 1 10 2 2 0 0 7 0 9 0 1 6 2 3 2 2 9 3 1 2 1 7 1 1 7 1 5 0 1 0 0 1 2 1 0 0 0 0 2 0 0 3 0 1 0 2 0 0 2 0 0 2 0 1 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 1 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 329388 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 37241 +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 347023 average: 3 | standard deviation: 0 | 0 0 0 347023 ] +miss_latency_LD_Directory: [binsize: 4 max: 453 count: 15182 average: 186.732 | standard deviation: 33.1643 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 18 26 59 98 6117 4547 1469 88 52 235 127 49 2 8 11 8 5 7 16 4 3 4 4 7 4 4 672 540 747 62 24 57 16 42 3 1 4 0 3 5 0 4 1 2 0 0 1 0 0 1 0 5 0 1 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 2 max: 357 count: 97983 average: 48.0277 | standard deviation: 3.92756 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 78965 3392 8812 337 6365 38 6 5 4 4 3 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 0 0 0 0 0 0 0 1 0 1 0 0 0 3 0 1 0 0 2 0 6 0 1 1 0 2 0 1 0 1 0 1 0 3 0 1 5 0 3 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 2 0 0 0 0 1 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 132362 average: 3 | standard deviation: 0 | 0 0 0 132362 ] +miss_latency_ST_Directory: [binsize: 2 max: 377 count: 7263 average: 178.253 | standard deviation: 23.2097 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 7 3 3 9 44 46 29 15 19 1550 2372 729 718 952 8 30 19 10 12 49 126 26 23 13 3 0 1 1 2 0 2 6 1 1 0 1 3 1 0 3 2 0 4 3 1 6 0 0 3 1 3 0 1 1 145 14 2 2 170 4 1 0 1 22 9 5 2 4 4 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 1 0 0 2 3 1 0 0 3 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 1 max: 57 count: 142 average: 48.7324 | standard deviation: 2.80577 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 94 0 7 0 22 2 6 2 3 0 6 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 1250256 average: 3 | standard deviation: 0 | 0 0 0 1250256 ] +miss_latency_IFETCH_Directory: [binsize: 2 max: 379 count: 14357 average: 186.815 | standard deviation: 32.1026 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 21 28 17 35 17 37 37 39 51 24 2166 1836 1633 3538 2149 42 35 18 59 25 63 77 75 125 58 9 3 3 7 6 2 3 4 2 3 8 0 2 4 0 1 1 0 1 0 4 0 1 13 0 5 0 2 10 4 1392 165 172 78 17 112 11 9 3 2 16 6 21 11 4 1 0 0 0 0 0 0 1 1 0 5 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 1 0 0 1 1 0 0 0 0 1 2 0 0 0 14 3 1 0 0 1 0 0 0 0 ] +miss_latency_IFETCH_L1Cache_wCC: [binsize: 2 max: 377 count: 231162 average: 49.7949 | standard deviation: 4.18653 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 111768 31968 3518 72751 537 8630 363 717 66 137 197 12 388 4 11 0 0 1 1 0 0 0 2 0 1 1 1 0 0 2 0 0 1 0 0 2 0 0 2 0 4 2 3 0 1 7 2 1 0 0 5 0 3 0 0 5 2 1 2 1 9 2 1 1 1 4 1 0 2 1 2 0 1 0 0 1 2 0 0 0 0 0 2 0 0 1 0 1 0 2 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 ] +miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 74 average: 3 | standard deviation: 0 | 0 0 0 74 ] +miss_latency_RMW_Read_Directory: [binsize: 2 max: 373 count: 356 average: 190.756 | standard deviation: 34.7212 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 3 1 1 0 1 10 4 2 63 20 174 0 0 1 2 0 1 1 1 0 6 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 58 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Locked_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 271 average: 3 | standard deviation: 0 | 0 0 0 271 ] +miss_latency_Locked_RMW_Read_Directory: [binsize: 1 max: 177 count: 84 average: 174.738 | standard deviation: 1.31259 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 71 0 5 ] +miss_latency_Locked_RMW_Read_L1Cache_wCC: [binsize: 1 max: 75 count: 101 average: 48.0891 | standard deviation: 3.71618 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 81 3 8 1 3 0 0 0 0 0 3 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_Locked_RMW_Write_L1Cache: [binsize: 1 max: 3 count: 456 average: 3 | standard deviation: 0 | 0 0 0 456 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 36 count: 733296 average: 0.93582 | standard deviation: 2.28151 | 600058 1246 31483 1041 16814 359 71345 81 367 100 8437 69 302 41 686 13 74 14 144 3 192 2 11 2 382 0 3 0 14 1 5 1 4 0 0 0 2 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 36 count: 733296 average: 0.93582 | standard deviation: 2.28151 | 600058 1246 31483 1041 16814 359 71345 81 367 100 8437 69 302 41 686 13 74 14 144 3 192 2 11 2 382 0 3 0 14 1 5 1 4 0 0 0 2 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 366630 average: 0.000559147 | standard deviation: 0.0464488 | 366575 2 2 5 46 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 36 count: 366666 average: 1.87099 | standard deviation: 2.94257 | 233483 1244 31481 1036 16768 359 71345 81 367 100 8437 69 302 41 686 13 74 14 144 3 192 2 11 2 382 0 3 0 14 1 5 1 4 0 0 0 2 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 27 +system_time: 0 +page_reclaims: 15257 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +total_msg_count_Control: 1099890 8799120 +total_msg_count_Data: 111834 8052048 +total_msg_count_Response_Data: 1099890 79192080 +total_msg_count_Writeback_Control: 1099998 8799984 +total_msgs: 3411612 total_bytes: 104843232 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 5.59709 + links_utilized_percent_switch_0_link_0: 5.59712 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 5.59707 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 88017 6337224 [ 0 0 0 0 88017 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 88016 704128 [ 0 0 0 88016 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 88017 704136 [ 0 0 88017 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 4208 302976 [ 0 0 4208 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 83808 6034176 [ 0 0 0 0 83808 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 5.91995 + links_utilized_percent_switch_1_link_0: 5.91967 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 5.92023 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 93088 6702336 [ 0 0 0 0 93088 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 93099 744792 [ 0 0 0 93099 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 93088 744704 [ 0 0 93088 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 11027 793944 [ 0 0 11027 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 82072 5909184 [ 0 0 0 0 82072 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 5.48482 + links_utilized_percent_switch_2_link_0: 5.48457 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 5.48508 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 86246 6209712 [ 0 0 0 0 86246 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 86256 690048 [ 0 0 0 86256 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 86246 689968 [ 0 0 86246 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 11022 793584 [ 0 0 11022 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 75234 5416848 [ 0 0 0 0 75234 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 2 +switch_3_outlinks: 2 +links_utilized_percent_switch_3: 6.3138 + links_utilized_percent_switch_3_link_0: 6.31339 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 6.31421 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 99279 7148088 [ 0 0 0 0 99279 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 99295 794360 [ 0 0 0 99295 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 99279 794232 [ 0 0 99279 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 11021 793512 [ 0 0 11021 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 88274 6355728 [ 0 0 0 0 88274 0 0 0 0 0 ] base_latency: 1 + +switch_4_inlinks: 2 +switch_4_outlinks: 2 +links_utilized_percent_switch_4: 4.46404 + links_utilized_percent_switch_4_link_0: 4.46496 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 4.46313 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Control: 366630 2933040 [ 0 0 366630 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Data: 37278 2684016 [ 0 0 37278 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 37242 2681424 [ 0 0 0 0 37242 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 366666 2933328 [ 0 0 0 366666 0 0 0 0 0 0 ] base_latency: 1 + +switch_5_inlinks: 5 +switch_5_outlinks: 5 +links_utilized_percent_switch_5: 5.55594 + links_utilized_percent_switch_5_link_0: 5.59712 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 5.91967 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 5.48457 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 6.31339 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_4: 4.46496 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 88017 6337224 [ 0 0 0 0 88017 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 88016 704128 [ 0 0 0 88016 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 93088 6702336 [ 0 0 0 0 93088 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 93099 744792 [ 0 0 0 93099 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 86246 6209712 [ 0 0 0 0 86246 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 86256 690048 [ 0 0 0 86256 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 99279 7148088 [ 0 0 0 0 99279 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Writeback_Control: 99295 794360 [ 0 0 0 99295 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_4_Control: 366630 2933040 [ 0 0 366630 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_4_Data: 37278 2684016 [ 0 0 37278 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 88017 + system.l1_cntrl0.cacheMemory_total_demand_misses: 88017 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.cacheMemory_request_type_LD: 26.5631% + system.l1_cntrl0.cacheMemory_request_type_ST: 0.919141% + system.l1_cntrl0.cacheMemory_request_type_IFETCH: 72.5178% + + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 88017 100% + + --- L1Cache --- + - Event Counts - +Load [175745 92936 115659 75848 ] 460188 +Ifetch [540269 312852 381046 261608 ] 1495775 +Store [88948 21736 14319 16106 ] 141109 +Data [88017 93088 86246 99279 ] 366630 +Fwd_GETX [83808 82072 75234 88274 ] 329388 +Inv [0 0 0 0 ] 0 +Replacement [4239 11106 11106 11109 ] 37560 +Writeback_Ack [4205 11013 11010 11004 ] 37232 +Writeback_Nack [3 14 12 17 ] 46 + + - Transitions - +I Load [23380 28469 29785 31531 ] 113165 +I Ifetch [63828 62247 54073 65371 ] 245519 +I Store [809 2372 2388 2377 ] 7946 +I Inv [0 0 0 0 ] 0 +I Replacement [31 79 84 88 ] 282 + +II Writeback_Nack [3 14 12 17 ] 46 + +M Load [152365 64467 85874 44317 ] 347023 +M Ifetch [476441 250605 326973 196237 ] 1250256 +M Store [88139 19364 11931 13729 ] 133163 +M Fwd_GETX [83805 82058 75222 88257 ] 329342 +M Inv [0 0 0 0 ] 0 +M Replacement [4208 11027 11022 11021 ] 37278 + +MI Fwd_GETX [3 14 12 17 ] 46 +MI Inv [0 0 0 0 ] 0 +MI Writeback_Ack [4205 11013 11010 11004 ] 37232 +MI Writeback_Nack [0 0 0 0 ] 0 + +MII Fwd_GETX [0 0 0 0 ] 0 + +IS Data [87208 90716 83858 96902 ] 358684 + +IM Data [809 2372 2388 2377 ] 7946 + +Cache Stats: system.l1_cntrl1.cacheMemory + system.l1_cntrl1.cacheMemory_total_misses: 93088 + system.l1_cntrl1.cacheMemory_total_demand_misses: 93088 + system.l1_cntrl1.cacheMemory_total_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl1.cacheMemory_request_type_LD: 30.5829% + system.l1_cntrl1.cacheMemory_request_type_ST: 2.54813% + system.l1_cntrl1.cacheMemory_request_type_IFETCH: 66.869% + + system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 93088 100% + +Cache Stats: system.l1_cntrl2.cacheMemory + system.l1_cntrl2.cacheMemory_total_misses: 86246 + system.l1_cntrl2.cacheMemory_total_demand_misses: 86246 + system.l1_cntrl2.cacheMemory_total_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl2.cacheMemory_request_type_LD: 34.5349% + system.l1_cntrl2.cacheMemory_request_type_ST: 2.76882% + system.l1_cntrl2.cacheMemory_request_type_IFETCH: 62.6962% + + system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 86246 100% + +Cache Stats: system.l1_cntrl3.cacheMemory + system.l1_cntrl3.cacheMemory_total_misses: 99279 + system.l1_cntrl3.cacheMemory_total_demand_misses: 99279 + system.l1_cntrl3.cacheMemory_total_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl3.cacheMemory_request_type_LD: 31.76% + system.l1_cntrl3.cacheMemory_request_type_ST: 2.39426% + system.l1_cntrl3.cacheMemory_request_type_IFETCH: 65.8457% + + system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 99279 100% + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 74474 + memory_reads: 37242 + memory_writes: 37232 + memory_refreshes: 16381 + memory_total_request_delays: 109346 + memory_delays_per_request: 1.46824 + memory_delays_in_input_queue: 18786 + memory_delays_behind_head_of_bank_queue: 814 + memory_delays_stalled_at_head_of_bank_queue: 89746 + memory_stalls_for_bank_busy: 51246 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 0 + memory_stalls_for_arbitration: 2518 + memory_stalls_for_bus: 34610 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 1331 + memory_stalls_for_read_read_turnaround: 41 + accesses_per_bank: 3658 1082 2048 758 174 562 180 596 126 478 462 496 112 708 980 5770 17740 9556 1292 2832 1820 5802 5428 2217 1534 334 523 769 657 1014 2702 2064 + + --- Directory --- + - Event Counts - +GETX [368528 ] 368528 +GETS [0 ] 0 +PUTX [37232 ] 37232 +PUTX_NotOwner [46 ] 46 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [37242 ] 37242 +Memory_Ack [37232 ] 37232 + + - Transitions - +I GETX [37242 ] 37242 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [329388 ] 329388 +M PUTX [37232 ] 37232 +M PUTX_NotOwner [46 ] 46 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [1480 ] 1480 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [37242 ] 37242 + +MI GETX [418 ] 418 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [37232 ] 37232 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack [0 ] 0 + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simout b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/simout @@ -0,0 +1,82 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 19:38:08 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp-ruby -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp-ruby +Global frequency set at 1000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Init done +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 1 completed +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +Iteration 2 completed +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=1, now next=2 +Iteration 3 completed +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 4 completed +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 5 completed +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=3, now next=1 +Iteration 6 completed +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 7 completed +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 8 completed +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 9 completed +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 10 completed +PASSED :-) +Exiting @ tick 7862696 because target called exit() diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp-ruby/stats.txt @@ -0,0 +1,114 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.007863 # Number of seconds simulated +sim_ticks 7862696 # Number of ticks simulated +final_tick 7862696 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 42091 # Simulator instruction rate (inst/s) +host_op_rate 84572 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 292484 # Simulator tick rate (ticks/s) +host_mem_usage 277948 # Number of bytes of host memory used +host_seconds 26.88 # Real time elapsed on the host +sim_insts 1131504 # Number of instructions simulated +sim_ops 2273505 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 13260382 # Number of bytes read from this memory +system.physmem.bytes_inst_read 11966200 # Number of instructions bytes read from this memory +system.physmem.bytes_written 594038 # Number of bytes written to this memory +system.physmem.num_reads 1956849 # Number of read requests responded to by this memory +system.physmem.num_writes 140223 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 1686493030 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1521895289 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 75551439 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 1762044469 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 95 # Number of system calls +system.cpu0.numCycles 7862696 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 448069 # Number of instructions committed +system.cpu0.committedOps 636455 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 636200 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 40 # Number of float alu accesses +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 89243 # number of instructions that are conditional controls +system.cpu0.num_int_insts 636200 # number of integer instructions +system.cpu0.num_fp_insts 40 # number of float instructions +system.cpu0.num_int_register_reads 1622127 # number of times the integer registers were read +system.cpu0.num_int_register_writes 549978 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 60 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 20 # number of times the floating registers were written +system.cpu0.num_mem_refs 264693 # number of memory refs +system.cpu0.num_load_insts 175867 # Number of load instructions +system.cpu0.num_store_insts 88826 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 7862696 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu1.numCycles 7754666 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 228400 # Number of instructions committed +system.cpu1.committedOps 512651 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 512293 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 77295 # number of instructions that are conditional controls +system.cpu1.num_int_insts 512293 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 1207439 # number of times the integer registers were read +system.cpu1.num_int_register_writes 497615 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 114672 # number of memory refs +system.cpu1.num_load_insts 93190 # Number of load instructions +system.cpu1.num_store_insts 21482 # Number of store instructions +system.cpu1.num_idle_cycles 338187.674882 # Number of idle cycles +system.cpu1.num_busy_cycles 7416478.325118 # Number of busy cycles +system.cpu1.not_idle_fraction 0.956389 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.043611 # Percentage of idle cycles +system.cpu2.numCycles 7754692 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 266440 # Number of instructions committed +system.cpu2.committedOps 686190 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 685822 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 0 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 107452 # number of instructions that are conditional controls +system.cpu2.num_int_insts 685822 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 1599960 # number of times the integer registers were read +system.cpu2.num_int_register_writes 678564 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 129978 # number of memory refs +system.cpu2.num_load_insts 115918 # Number of load instructions +system.cpu2.num_store_insts 14060 # Number of store instructions +system.cpu2.num_idle_cycles 341723.577576 # Number of idle cycles +system.cpu2.num_busy_cycles 7412968.422424 # Number of busy cycles +system.cpu2.not_idle_fraction 0.955933 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.044067 # Percentage of idle cycles +system.cpu3.numCycles 7754618 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 188595 # Number of instructions committed +system.cpu3.committedOps 438209 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 437857 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 0 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 65828 # number of instructions that are conditional controls +system.cpu3.num_int_insts 437857 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 1024372 # number of times the integer registers were read +system.cpu3.num_int_register_writes 428806 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 91954 # number of memory refs +system.cpu3.num_load_insts 76099 # Number of load instructions +system.cpu3.num_store_insts 15855 # Number of store instructions +system.cpu3.num_idle_cycles 345521.340358 # Number of idle cycles +system.cpu3.num_busy_cycles 7409096.659642 # Number of busy cycles +system.cpu3.not_idle_fraction 0.955443 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.044557 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/config.ini @@ -0,0 +1,563 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[7] + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[3] +pio=system.membus.master[2] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[6] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[9] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[11] + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[8] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[3] +int_slave=system.membus.master[5] +pio=system.membus.master[4] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[10] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[13] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[15] + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/simout @@ -0,0 +1,25 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 15:43:33 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp +Global frequency set at 1000000000000 ticks per second +info: Entering event queue @ 0. Starting simulation... +Init done +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=3, now next=1 +Iteration 1 completed +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 2 completed +Exiting @ tick 10541207000 because user interrupt received diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/skip b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/skip diff --git a/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test-atomic/ref/x86/linux/simple-timing-mp/stats.txt @@ -0,0 +1,1074 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.010541 # Number of seconds simulated +sim_ticks 10541207000 # Number of ticks simulated +final_tick 10541207000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 527995 # Simulator instruction rate (inst/s) +host_op_rate 740736 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 238317780 # Simulator tick rate (ticks/s) +host_mem_usage 275896 # Number of bytes of host memory used +host_seconds 44.23 # Real time elapsed on the host +sim_insts 23354124 # Number of instructions simulated +sim_ops 32764006 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 33088 # Number of bytes read from this memory +system.physmem.bytes_inst_read 19392 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 517 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 3138919 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1839638 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 3138919 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 34 # Number of system calls +system.cpu0.numCycles 21082414 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 5843539 # Number of instructions committed +system.cpu0.committedOps 8184459 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 8184364 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 8 # Number of float alu accesses +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 1168494 # number of instructions that are conditional controls +system.cpu0.num_int_insts 8184364 # number of integer instructions +system.cpu0.num_fp_insts 8 # number of float instructions +system.cpu0.num_int_register_reads 21039815 # number of times the integer registers were read +system.cpu0.num_int_register_writes 7016932 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 12 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 4 # number of times the floating registers were written +system.cpu0.num_mem_refs 3504430 # number of memory refs +system.cpu0.num_load_insts 2335933 # Number of load instructions +system.cpu0.num_store_insts 1168497 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 21082414 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.icache.replacements 84 # number of replacements +system.cpu0.icache.tagsinuse 230.527976 # Cycle average of tags in use +system.cpu0.icache.total_refs 7012815 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 315 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 22262.904762 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 230.527976 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.450250 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.450250 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 7012815 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 7012815 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 7012815 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 7012815 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 7012815 # number of overall hits +system.cpu0.icache.overall_hits::total 7012815 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 315 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 315 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 315 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 315 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 315 # number of overall misses +system.cpu0.icache.overall_misses::total 315 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 14288000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 14288000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 14288000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 14288000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 14288000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 14288000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 7013130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 7013130 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 7013130 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 7013130 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 7013130 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 7013130 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.000045 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.000045 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.000045 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 45358.730159 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 45358.730159 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 45358.730159 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 315 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 315 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 315 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 315 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 315 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 315 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 13343000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 13343000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 13343000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 13343000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 13343000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 13343000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.000045 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.000045 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.000045 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 42358.730159 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 42358.730159 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 42358.730159 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 2 # number of replacements +system.cpu0.dcache.tagsinuse 145.757090 # Cycle average of tags in use +system.cpu0.dcache.total_refs 3499803 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 148 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 23647.317568 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 145.757090 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.284682 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.284682 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 2335828 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 2335828 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 1168388 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 1168388 # number of WriteReq hits +system.cpu0.dcache.demand_hits::cpu0.data 3504216 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 3504216 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 3504216 # number of overall hits +system.cpu0.dcache.overall_hits::total 3504216 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 105 # number of ReadReq misses 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(read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 9889000 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 9889000 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 9889000 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 2335933 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 2335933 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 1168497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 1168497 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 3504430 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 3504430 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 3504430 # number of overall (read+write) accesses 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number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 105 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 105 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 109 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 109 # number of WriteReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 214 # number of demand (read+write) MSHR misses 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misses that were no-allocate +system.cpu1.numCycles 21082414 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 5836404 # Number of instructions committed +system.cpu1.committedOps 8208285 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 8208209 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 1173356 # number of instructions that are conditional controls +system.cpu1.num_int_insts 8208209 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 21085384 # number of times the integer registers were read +system.cpu1.num_int_register_writes 7046969 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 3497440 # number of memory refs +system.cpu1.num_load_insts 2334832 # Number of load instructions +system.cpu1.num_store_insts 1162608 # Number of store instructions +system.cpu1.num_idle_cycles 55667.999995 # Number of idle cycles +system.cpu1.num_busy_cycles 21026746.000005 # Number of busy cycles +system.cpu1.not_idle_fraction 0.997360 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.002640 # Percentage of idle cycles +system.cpu1.icache.replacements 28 # number of replacements +system.cpu1.icache.tagsinuse 91.553372 # Cycle average of tags in use +system.cpu1.icache.total_refs 7011086 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 120 # Sample count of references to valid blocks. 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15804.166667 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 15804.166667 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 120 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 120 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 120 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 120 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 120 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 120 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1536000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1536000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1536000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1536000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1536000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1536000 # number of overall MSHR miss cycles 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3497440 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 3497440 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 3497440 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.000029 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.000047 # miss rate for WriteReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.000035 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.000035 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 20373.134328 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 31054.545455 # average WriteReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 25188.524590 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 25188.524590 # average overall miss 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55 # number of WriteReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 122 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 122 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 122 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 122 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1164000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1164000 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1543000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1543000 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 2707000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 2707000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 2707000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 2707000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.000029 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.000047 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.000035 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.000035 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 17373.134328 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 28054.545455 # average WriteReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 22188.524590 # average overall mshr miss latency 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float instructions +system.cpu2.num_int_register_reads 21031926 # number of times the integer registers were read +system.cpu2.num_int_register_writes 7018577 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 3499102 # number of memory refs +system.cpu2.num_load_insts 2333298 # Number of load instructions +system.cpu2.num_store_insts 1165804 # Number of store instructions +system.cpu2.num_idle_cycles 56131.999995 # Number of idle cycles +system.cpu2.num_busy_cycles 21026282.000005 # Number of busy cycles +system.cpu2.not_idle_fraction 0.997337 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.002663 # Percentage of idle cycles +system.cpu2.icache.replacements 28 # number of replacements +system.cpu2.icache.tagsinuse 91.708849 # Cycle average of tags in use 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# number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 4242500 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 7006593 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 7006593 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 7006593 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 7006593 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 7006593 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 7006593 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.000017 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.000017 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.000017 # miss rate for overall accesses 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average of tags in use +system.cpu2.dcache.total_refs 3492666 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 36 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 97018.500000 # Average number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.occ_blocks::cpu2.data 34.913337 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.068190 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.068190 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 2333227 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 2333227 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 1165747 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 1165747 # number of WriteReq hits +system.cpu2.dcache.demand_hits::cpu2.data 3498974 # number of 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WriteReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 3068000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 3068000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 3068000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 3068000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.000030 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.000049 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.000037 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.000037 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 20070.422535 # average ReadReq mshr miss latency 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number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu0.data 6041000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.inst 200000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu1.data 800000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.inst 2360000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu2.data 960000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.inst 160000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::cpu3.data 760000 # number of overall MSHR miss cycles +system.l2c.overall_mshr_miss_latency::total 20683000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.746032 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.953846 # mshr miss rate for ReadReq accesses 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ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.746032 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.980519 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.041667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.666667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.491667 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.033058 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.655172 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.746032 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.980519 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.041667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.666667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.491667 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.800000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.033058 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.655172 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40008.510638 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadReq mshr miss latency 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Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/config.ini @@ -0,0 +1,1803 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.cpu0] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu0.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu0.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + 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+[system.cpu2.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu2.fuPool.FUList3.opList0 system.cpu2.fuPool.FUList3.opList1 system.cpu2.fuPool.FUList3.opList2 + +[system.cpu2.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu2.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu2.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu2.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu2.fuPool.FUList4.opList + +[system.cpu2.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu2.fuPool.FUList5.opList00 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+[system.cpu2.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu2.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu2.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu2.fuPool.FUList8.opList + +[system.cpu2.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu2.interrupts] +type=SparcInterrupts + +[system.cpu2.itb] +type=SparcTLB +size=64 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=3 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu3.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu3.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu3.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=false +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu3.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[7] + +[system.cpu3.dtb] +type=SparcTLB +size=64 + +[system.cpu3.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 + +[system.cpu3.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu3.fuPool.FUList0.opList + +[system.cpu3.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu3.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 + +[system.cpu3.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu3.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu3.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 + +[system.cpu3.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu3.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu3.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu3.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 + +[system.cpu3.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu3.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu3.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu3.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu3.fuPool.FUList4.opList + +[system.cpu3.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu3.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 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+opLat=1 + +[system.cpu3.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu3.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu3.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu3.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu3.fuPool.FUList6.opList + +[system.cpu3.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 + +[system.cpu3.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu3.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu3.fuPool.FUList8.opList + +[system.cpu3.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[6] + +[system.cpu3.interrupts] +type=SparcInterrupts + +[system.cpu3.itb] +type=SparcTLB +size=64 + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.physmem.port[0] +slave=system.l2c.mem_side system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[0] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/simout @@ -0,0 +1,89 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 16:06:31 +gem5 started May 16 2012 20:20:05 +gem5 executing on SC2B0617 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/o3-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/o3-timing-mp +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0: Constructing CPU with id 0 + 0: system.cpu1: Constructing CPU with id 1 + 0: system.cpu2: Constructing CPU with id 2 + 0: system.cpu3: Constructing CPU with id 3 +info: Entering event queue @ 0. Starting simulation... +1285500: system.cpu0: syscall uname called w/arguments 1048640,0,2750464,8796093021226 +1285500: system.cpu0: syscall uname returns 0 +1905500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +1905500: system.cpu0: syscall mmap returns 18446735277616529408 +6854000: system.cpu0: syscall brk called w/arguments 0,0,1385948,0 +6854000: system.cpu0: syscall brk returns 2752512 +6902500: system.cpu0: syscall brk called w/arguments 0,0,1385948,2891776 +6902500: global: Break Point changed to: 0X2C2000 +6902500: system.cpu0: syscall brk returns 2891776 +14955000: system.cpu0: syscall fstat called w/arguments 132620,8796093018288,8796093017992,1 +14955000: global: fstat(1, ...) +14955000: system.cpu0: syscall fstat returns 0 +15433500: system.cpu0: syscall mmap called w/arguments 34,3,8192,0 +15433500: system.cpu0: syscall mmap returns 18446735277616660480 +18188000: system.cpu0: syscall write called w/arguments 0,22,18446735277616660480,1 +Starting 4 threads... +18188000: system.cpu0: syscall write returns 22 +19258500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +19258500: system.cpu0: syscall mmap returns 18446735277616668672 +19360000: system.cpu0: syscall clone called w/arguments 0,12,18446735277616795649,69376 +19360000: global: In sys_clone: +19360000: global: Flags=10f00 +19360000: global: Child stack=fffff80000041001 +19360000: global: Found unallocated thread context +19360000: system.cpu0: syscall clone returns 1 +19439500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +19439500: system.cpu0: syscall mmap returns 18446735277616799744 +19534500: system.cpu0: syscall clone called w/arguments 0,12,18446735277616926721,69376 +19534500: global: In sys_clone: +19534500: global: Flags=10f00 +19534500: global: Child stack=fffff80000061001 +19534500: global: Found unallocated thread context +19534500: system.cpu0: syscall clone returns 1 +19600500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +19600500: system.cpu0: syscall mmap returns 18446735277616930816 +19698500: system.cpu0: syscall clone called w/arguments 0,12,18446735277617057793,69376 +19698500: global: In sys_clone: +19698500: global: Flags=10f00 +19698500: global: Child stack=fffff80000081001 +19698500: global: Found unallocated thread context +19698500: system.cpu0: syscall clone returns 1 +21835000: system.cpu0: syscall write called w/arguments 0,29,18446735277616660480,1 +&local[0]=0xfffff80000000000 +21835000: system.cpu0: syscall write returns 29 +23831000: system.cpu3: syscall write called w/arguments 18446735277616930816,29,18446735277616660480,1 +&local[3]=0xfffff80000062038 +23831000: system.cpu3: syscall write returns 29 +25880000: system.cpu2: syscall write called w/arguments 18446735277616799744,29,18446735277616660480,1 +&local[2]=0xfffff80000042038 +25880000: system.cpu2: syscall write returns 29 +27928000: system.cpu1: syscall write called w/arguments 18446735277616668672,29,18446735277616660480,1 +&local[1]=0xfffff80000022038 +27928000: system.cpu1: syscall write returns 29 +39880000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[0] = 1031 +39880000: system.cpu0: syscall write returns 16 +41276500: system.cpu3: syscall exit called w/arguments 3,132620,0,0 +41276500: system.cpu3: syscall exit returns 1 +43312500: system.cpu2: syscall exit called w/arguments 3,132620,0,0 +43312500: system.cpu2: syscall exit returns 1 +45393500: system.cpu1: syscall exit called w/arguments 3,132620,0,0 +45393500: system.cpu1: syscall exit returns 1 +46163000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[1] = 1032 +46163000: system.cpu0: syscall write returns 16 +47130000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[2] = 1033 +47130000: system.cpu0: syscall write returns 16 +48075000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[3] = 1034 +48075000: system.cpu0: syscall write returns 16 +50525500: system.cpu0: syscall munmap called w/arguments 0,0,8192,18446735277616660480 +50525500: system.cpu0: syscall munmap returns 0 +50648000: system.cpu0: syscall exit_group called w/arguments 1504373,0,0,0 +50648000: system.cpu0: syscall exit_group returns 1 +Exiting @ tick 50648000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/o3-timing-mp/stats.txt @@ -0,0 +1,2162 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000051 # Number of seconds simulated +sim_ticks 50648000 # Number of ticks simulated +final_tick 50648000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 139883 # Simulator instruction rate (inst/s) +host_op_rate 139882 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 15471997 # Simulator tick rate (ticks/s) +host_mem_usage 278520 # Number of bytes of host memory used +host_seconds 3.27 # Real time elapsed on the host +sim_insts 457906 # Number of instructions simulated +sim_ops 457906 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 41088 # Number of bytes read from this memory +system.physmem.bytes_inst_read 27328 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 642 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 811246249 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 539567209 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 811246249 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 26 # Number of system calls +system.cpu0.numCycles 101297 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.BPredUnit.lookups 19137 # Number of BP lookups +system.cpu0.BPredUnit.condPredicted 17185 # Number of conditional branches predicted +system.cpu0.BPredUnit.condIncorrect 1146 # Number of conditional branches incorrect +system.cpu0.BPredUnit.BTBLookups 17258 # Number of BTB lookups +system.cpu0.BPredUnit.BTBHits 14739 # Number of BTB hits +system.cpu0.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu0.BPredUnit.usedRAS 499 # Number of times the RAS was used to get a target. +system.cpu0.BPredUnit.RASInCorrect 117 # Number of incorrect RAS predictions. +system.cpu0.fetch.icacheStallCycles 19466 # Number of cycles fetch is stalled on an Icache miss +system.cpu0.fetch.Insts 150474 # Number of instructions fetch has processed +system.cpu0.fetch.Branches 19137 # Number of branches that fetch encountered +system.cpu0.fetch.predictedBranches 15238 # Number of branches that fetch has predicted taken +system.cpu0.fetch.Cycles 46217 # Number of cycles fetch has run and was not squashing or blocked +system.cpu0.fetch.SquashCycles 3303 # Number of cycles fetch has spent squashing +system.cpu0.fetch.BlockedCycles 11320 # Number of cycles fetch has spent blocked +system.cpu0.fetch.MiscStallCycles 5 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu0.fetch.PendingTrapStallCycles 1389 # Number of stall cycles due to pending traps +system.cpu0.fetch.CacheLines 9472 # Number of cache lines fetched +system.cpu0.fetch.IcacheSquashes 473 # Number of outstanding Icache misses that were squashed +system.cpu0.fetch.rateDist::samples 80445 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::mean 1.870520 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::stdev 2.830271 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::0 34228 42.55% 42.55% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::1 28415 35.32% 77.87% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::2 586 0.73% 78.60% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::3 633 0.79% 79.39% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::4 2396 2.98% 82.36% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::5 291 0.36% 82.73% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::6 1365 1.70% 84.42% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::7 489 0.61% 85.03% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::8 12042 14.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.rateDist::total 80445 # Number of instructions fetched each cycle (Total) +system.cpu0.fetch.branchRate 0.188920 # Number of branch fetches per cycle +system.cpu0.fetch.rate 1.485473 # Number of inst fetches per cycle +system.cpu0.decode.IdleCycles 20603 # Number of cycles decode is idle +system.cpu0.decode.BlockedCycles 12176 # Number of cycles decode is blocked +system.cpu0.decode.RunCycles 44815 # Number of cycles decode is running +system.cpu0.decode.UnblockCycles 803 # Number of cycles decode is unblocking +system.cpu0.decode.SquashCycles 2048 # Number of cycles decode is squashing +system.cpu0.decode.DecodedInsts 147795 # Number of instructions handled by decode +system.cpu0.rename.SquashCycles 2048 # Number of cycles rename is squashing +system.cpu0.rename.IdleCycles 21476 # Number of cycles rename is idle +system.cpu0.rename.BlockCycles 324 # Number of cycles rename is blocking +system.cpu0.rename.serializeStallCycles 10025 # count of cycles rename stalled for serializing inst +system.cpu0.rename.RunCycles 44782 # Number of cycles rename is running +system.cpu0.rename.UnblockCycles 1790 # Number of cycles rename is unblocking +system.cpu0.rename.RenamedInsts 145290 # Number of instructions processed by rename +system.cpu0.rename.IQFullEvents 1312 # Number of times rename has blocked due to IQ full +system.cpu0.rename.LSQFullEvents 134 # Number of times rename has blocked due to LSQ full +system.cpu0.rename.FullRegisterEvents 20 # Number of times there has been no free registers +system.cpu0.rename.RenamedOperands 137065 # Number of destination operands rename has renamed +system.cpu0.rename.RenameLookups 262243 # Number of register rename lookups that rename has made +system.cpu0.rename.int_rename_lookups 262243 # Number of integer rename lookups +system.cpu0.rename.CommittedMaps 126169 # Number of HB maps that are committed +system.cpu0.rename.UndoneMaps 10896 # Number of HB maps that are undone due to squashing +system.cpu0.rename.serializingInsts 745 # count of serializing insts renamed +system.cpu0.rename.tempSerializingInsts 781 # count of temporary serializing insts renamed +system.cpu0.rename.skidInsts 4831 # count of insts added to the skid buffer +system.cpu0.memDep0.insertedLoads 18517 # Number of loads inserted to the mem dependence unit. +system.cpu0.memDep0.insertedStores 5483 # Number of stores inserted to the mem dependence unit. +system.cpu0.memDep0.conflictingLoads 3103 # Number of conflicting loads. +system.cpu0.memDep0.conflictingStores 1062 # Number of conflicting stores. +system.cpu0.iq.iqInstsAdded 138730 # Number of instructions added to the IQ (excludes non-spec) +system.cpu0.iq.iqNonSpecInstsAdded 716 # Number of non-speculative instructions added to the IQ +system.cpu0.iq.iqInstsIssued 136978 # Number of instructions issued +system.cpu0.iq.iqSquashedInstsIssued 142 # Number of squashed instructions issued +system.cpu0.iq.iqSquashedInstsExamined 8615 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu0.iq.iqSquashedOperandsExamined 6781 # Number of squashed operands that are examined and possibly removed from graph +system.cpu0.iq.iqSquashedNonSpecRemoved 293 # Number of squashed non-spec instructions that were removed +system.cpu0.iq.issued_per_cycle::samples 80445 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::mean 1.702753 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::stdev 1.706602 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::0 27137 33.73% 33.73% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::1 16073 19.98% 53.71% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::2 14003 17.41% 71.12% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::3 11400 14.17% 85.29% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::4 928 1.15% 86.45% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::5 10552 13.12% 99.56% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::6 253 0.31% 99.88% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::7 83 0.10% 99.98% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::8 16 0.02% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu0.iq.issued_per_cycle::total 80445 # Number of insts issued each cycle +system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntAlu 53 26.11% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntMult 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::IntDiv 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatAdd 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCmp 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatCvt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatMult 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatDiv 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAdd 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdAlu 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCmp 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdCvt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMisc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMult 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShift 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 26.11% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemRead 29 14.29% 40.39% # attempts to use FU when none available +system.cpu0.iq.fu_full::MemWrite 121 59.61% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IntAlu 113486 82.85% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::IntMult 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 82.85% # Type of FU issued +system.cpu0.iq.FU_type_0::MemRead 18292 13.35% 96.20% # Type of FU issued +system.cpu0.iq.FU_type_0::MemWrite 5200 3.80% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu0.iq.FU_type_0::total 136978 # Type of FU issued +system.cpu0.iq.rate 1.352241 # Inst issue rate +system.cpu0.iq.fu_busy_cnt 203 # FU busy when requested +system.cpu0.iq.fu_busy_rate 0.001482 # FU busy rate (busy events/executed inst) +system.cpu0.iq.int_inst_queue_reads 354746 # Number of integer instruction queue reads +system.cpu0.iq.int_inst_queue_writes 148070 # Number of integer instruction queue writes +system.cpu0.iq.int_inst_queue_wakeup_accesses 135255 # Number of integer instruction queue wakeup accesses +system.cpu0.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu0.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu0.iq.int_alu_accesses 137181 # Number of integer alu accesses +system.cpu0.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu0.iew.lsq.thread0.forwLoads 3160 # Number of loads that had data forwarded from stores +system.cpu0.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu0.iew.lsq.thread0.squashedLoads 1535 # Number of loads squashed +system.cpu0.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed +system.cpu0.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations +system.cpu0.iew.lsq.thread0.squashedStores 1040 # Number of stores squashed +system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu0.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu0.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu0.iew.lsq.thread0.cacheBlocked 17 # Number of times an access to memory failed due to the cache being blocked +system.cpu0.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu0.iew.iewSquashCycles 2048 # Number of cycles IEW is squashing +system.cpu0.iew.iewBlockCycles 125 # Number of cycles IEW is blocking +system.cpu0.iew.iewUnblockCycles 5 # Number of cycles IEW is unblocking +system.cpu0.iew.iewDispatchedInsts 143222 # Number of instructions dispatched to IQ +system.cpu0.iew.iewDispSquashedInsts 308 # Number of squashed instructions skipped by dispatch +system.cpu0.iew.iewDispLoadInsts 18517 # Number of dispatched load instructions +system.cpu0.iew.iewDispStoreInsts 5483 # Number of dispatched store instructions +system.cpu0.iew.iewDispNonSpecInsts 678 # Number of dispatched non-speculative instructions +system.cpu0.iew.iewIQFullEvents 5 # Number of times the IQ has become full, causing a stall +system.cpu0.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu0.iew.memOrderViolationEvents 9 # Number of memory order violations +system.cpu0.iew.predictedTakenIncorrect 300 # Number of branches that were predicted taken incorrectly +system.cpu0.iew.predictedNotTakenIncorrect 1000 # Number of branches that were predicted not taken incorrectly +system.cpu0.iew.branchMispredicts 1300 # Number of branch mispredicts detected at execute +system.cpu0.iew.iewExecutedInsts 135921 # Number of executed instructions +system.cpu0.iew.iewExecLoadInsts 18062 # Number of load instructions executed +system.cpu0.iew.iewExecSquashedInsts 1057 # Number of squashed instructions skipped in execute +system.cpu0.iew.exec_swp 0 # number of swp insts executed +system.cpu0.iew.exec_nop 3776 # number of nop insts executed +system.cpu0.iew.exec_refs 23141 # number of memory reference insts executed +system.cpu0.iew.exec_branches 16532 # Number of branches executed +system.cpu0.iew.exec_stores 5079 # Number of stores executed +system.cpu0.iew.exec_rate 1.341807 # Inst execution rate +system.cpu0.iew.wb_sent 135523 # cumulative count of insts sent to commit +system.cpu0.iew.wb_count 135255 # cumulative count of insts written-back +system.cpu0.iew.wb_producers 109048 # num instructions producing a value +system.cpu0.iew.wb_consumers 121308 # num instructions consuming a value +system.cpu0.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu0.iew.wb_rate 1.335232 # insts written-back per cycle +system.cpu0.iew.wb_fanout 0.898935 # average fanout of values written-back +system.cpu0.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu0.commit.commitCommittedInsts 133390 # The number of committed instructions +system.cpu0.commit.commitCommittedOps 133390 # The number of committed instructions +system.cpu0.commit.commitSquashedInsts 9799 # The number of squashed insts skipped by commit +system.cpu0.commit.commitNonSpecStalls 423 # The number of times commit has been forced to stall to communicate backwards +system.cpu0.commit.branchMispredicts 1146 # The number of times a branch was mispredicted +system.cpu0.commit.committed_per_cycle::samples 78416 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::mean 1.701056 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::stdev 1.799474 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::0 30545 38.95% 38.95% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::1 11621 14.82% 53.77% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::2 11617 14.81% 68.59% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::3 12575 16.04% 84.62% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::4 437 0.56% 85.18% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::5 11200 14.28% 99.46% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::6 105 0.13% 99.60% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::7 96 0.12% 99.72% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::8 220 0.28% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu0.commit.committed_per_cycle::total 78416 # Number of insts commited each cycle +system.cpu0.commit.committedInsts 133390 # Number of instructions committed +system.cpu0.commit.committedOps 133390 # Number of ops (including micro ops) committed +system.cpu0.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu0.commit.refs 21425 # Number of memory references committed +system.cpu0.commit.loads 16982 # Number of loads committed +system.cpu0.commit.membars 32 # Number of memory barriers committed +system.cpu0.commit.branches 15745 # Number of branches committed +system.cpu0.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu0.commit.int_insts 115126 # Number of committed integer instructions. +system.cpu0.commit.function_calls 164 # Number of function calls committed. +system.cpu0.commit.bw_lim_events 220 # number cycles where commit BW limit reached +system.cpu0.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu0.rob.rob_reads 220274 # The number of ROB reads +system.cpu0.rob.rob_writes 288444 # The number of ROB writes +system.cpu0.timesIdled 309 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu0.idleCycles 20852 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu0.committedInsts 129947 # Number of Instructions Simulated +system.cpu0.committedOps 129947 # Number of Ops (including micro ops) Simulated +system.cpu0.committedInsts_total 129947 # Number of Instructions Simulated +system.cpu0.cpi 0.779525 # CPI: Cycles Per Instruction +system.cpu0.cpi_total 0.779525 # CPI: Total CPI of All Threads +system.cpu0.ipc 1.282832 # IPC: Instructions Per Cycle +system.cpu0.ipc_total 1.282832 # IPC: Total IPC of All Threads +system.cpu0.int_regfile_reads 226314 # number of integer regfile reads +system.cpu0.int_regfile_writes 130548 # number of integer regfile writes +system.cpu0.fp_regfile_reads 192 # number of floating regfile reads +system.cpu0.misc_regfile_reads 24717 # number of misc regfile reads +system.cpu0.misc_regfile_writes 526 # number of misc regfile writes +system.cpu0.icache.replacements 239 # number of replacements +system.cpu0.icache.tagsinuse 220.686031 # Cycle average of tags in use +system.cpu0.icache.total_refs 8780 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 536 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 16.380597 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 220.686031 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.431027 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.431027 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 8780 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 8780 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 8780 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 8780 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 8780 # number of overall hits +system.cpu0.icache.overall_hits::total 8780 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 692 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 692 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 692 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 692 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 692 # number of overall misses +system.cpu0.icache.overall_misses::total 692 # number of overall misses +system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 30888000 # number of ReadReq miss cycles +system.cpu0.icache.ReadReq_miss_latency::total 30888000 # number of ReadReq miss cycles +system.cpu0.icache.demand_miss_latency::cpu0.inst 30888000 # number of demand (read+write) miss cycles +system.cpu0.icache.demand_miss_latency::total 30888000 # number of demand (read+write) miss cycles +system.cpu0.icache.overall_miss_latency::cpu0.inst 30888000 # number of overall miss cycles +system.cpu0.icache.overall_miss_latency::total 30888000 # number of overall miss cycles +system.cpu0.icache.ReadReq_accesses::cpu0.inst 9472 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 9472 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 9472 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 9472 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 9472 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 9472 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.073057 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.073057 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.073057 # miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 44635.838150 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 44635.838150 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 44635.838150 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 15500 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 1 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs 15500 # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 155 # number of ReadReq MSHR hits +system.cpu0.icache.ReadReq_mshr_hits::total 155 # number of ReadReq MSHR hits +system.cpu0.icache.demand_mshr_hits::cpu0.inst 155 # number of demand (read+write) MSHR hits +system.cpu0.icache.demand_mshr_hits::total 155 # number of demand (read+write) MSHR hits +system.cpu0.icache.overall_mshr_hits::cpu0.inst 155 # number of overall MSHR hits +system.cpu0.icache.overall_mshr_hits::total 155 # number of overall MSHR hits +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 537 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 537 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 537 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 537 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 537 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 537 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 23537000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 23537000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 23537000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 23537000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 23537000 # number of overall MSHR miss cycles +system.cpu0.icache.overall_mshr_miss_latency::total 23537000 # number of overall MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.056693 # mshr miss rate for ReadReq accesses +system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.056693 # mshr miss rate for demand accesses +system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.056693 # mshr miss rate for overall accesses +system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 43830.540037 # average ReadReq mshr miss latency +system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 43830.540037 # average overall mshr miss latency +system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 43830.540037 # average overall mshr miss latency +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 5 # number of replacements +system.cpu0.dcache.tagsinuse 134.997937 # Cycle average of tags in use +system.cpu0.dcache.total_refs 18393 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 178 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 103.331461 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 134.997937 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.263668 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.263668 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 14653 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 14653 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 3985 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 3985 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 10 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 18638 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 18638 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 18638 # number of overall hits +system.cpu0.dcache.overall_hits::total 18638 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 182 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 182 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 442 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 442 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 6 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 6 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 624 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 624 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 624 # number of overall misses +system.cpu0.dcache.overall_misses::total 624 # number of overall misses +system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 8362000 # number of ReadReq miss cycles +system.cpu0.dcache.ReadReq_miss_latency::total 8362000 # number of ReadReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 22297984 # number of WriteReq miss cycles +system.cpu0.dcache.WriteReq_miss_latency::total 22297984 # number of WriteReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 285500 # number of SwapReq miss cycles +system.cpu0.dcache.SwapReq_miss_latency::total 285500 # number of SwapReq miss cycles +system.cpu0.dcache.demand_miss_latency::cpu0.data 30659984 # number of demand (read+write) miss cycles +system.cpu0.dcache.demand_miss_latency::total 30659984 # number of demand (read+write) miss cycles +system.cpu0.dcache.overall_miss_latency::cpu0.data 30659984 # number of overall miss cycles +system.cpu0.dcache.overall_miss_latency::total 30659984 # number of overall miss cycles +system.cpu0.dcache.ReadReq_accesses::cpu0.data 14835 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 14835 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 4427 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 4427 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 16 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 16 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 19262 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 19262 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 19262 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 19262 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.012268 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.099842 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.375000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.032395 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.032395 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 45945.054945 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 50447.927602 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 47583.333333 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 49134.589744 # average overall miss latency +system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 49134.589744 # average overall miss latency +system.cpu0.dcache.blocked_cycles::no_mshrs 156500 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 19 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs 8236.842105 # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3 # number of writebacks +system.cpu0.dcache.writebacks::total 3 # number of writebacks +system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 87 # number of ReadReq MSHR hits +system.cpu0.dcache.ReadReq_mshr_hits::total 87 # number of ReadReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 348 # number of WriteReq MSHR hits +system.cpu0.dcache.WriteReq_mshr_hits::total 348 # number of WriteReq MSHR hits +system.cpu0.dcache.demand_mshr_hits::cpu0.data 435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.demand_mshr_hits::total 435 # number of demand (read+write) MSHR hits +system.cpu0.dcache.overall_mshr_hits::cpu0.data 435 # number of overall MSHR hits +system.cpu0.dcache.overall_mshr_hits::total 435 # number of overall MSHR hits +system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 95 # number of ReadReq MSHR misses +system.cpu0.dcache.ReadReq_mshr_misses::total 95 # number of ReadReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 94 # number of WriteReq MSHR misses +system.cpu0.dcache.WriteReq_mshr_misses::total 94 # number of WriteReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 6 # number of SwapReq MSHR misses +system.cpu0.dcache.SwapReq_mshr_misses::total 6 # number of SwapReq MSHR misses +system.cpu0.dcache.demand_mshr_misses::cpu0.data 189 # number of demand (read+write) MSHR misses +system.cpu0.dcache.demand_mshr_misses::total 189 # number of demand (read+write) MSHR misses +system.cpu0.dcache.overall_mshr_misses::cpu0.data 189 # number of overall MSHR misses +system.cpu0.dcache.overall_mshr_misses::total 189 # number of overall MSHR misses +system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 4749500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_latency::total 4749500 # number of ReadReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 4724500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.WriteReq_mshr_miss_latency::total 4724500 # number of WriteReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 267500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.SwapReq_mshr_miss_latency::total 267500 # number of SwapReq MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 9474000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.demand_mshr_miss_latency::total 9474000 # number of demand (read+write) MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 9474000 # number of overall MSHR miss cycles +system.cpu0.dcache.overall_mshr_miss_latency::total 9474000 # number of overall MSHR miss cycles +system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.006404 # mshr miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.021233 # mshr miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.375000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.009812 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.009812 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 49994.736842 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 50260.638298 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 44583.333333 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 50126.984127 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 50126.984127 # average overall mshr miss latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 62576 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.BPredUnit.lookups 13371 # Number of BP lookups +system.cpu1.BPredUnit.condPredicted 12954 # Number of conditional branches predicted +system.cpu1.BPredUnit.condIncorrect 240 # Number of conditional branches incorrect +system.cpu1.BPredUnit.BTBLookups 13126 # Number of BTB lookups +system.cpu1.BPredUnit.BTBHits 12462 # Number of BTB hits +system.cpu1.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu1.BPredUnit.usedRAS 84 # Number of times the RAS was used to get a target. +system.cpu1.BPredUnit.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu1.fetch.icacheStallCycles 5268 # Number of cycles fetch is stalled on an Icache miss +system.cpu1.fetch.Insts 117363 # Number of instructions fetch has processed +system.cpu1.fetch.Branches 13371 # Number of branches that fetch encountered +system.cpu1.fetch.predictedBranches 12546 # Number of branches that fetch has predicted taken +system.cpu1.fetch.Cycles 37060 # Number of cycles fetch has run and was not squashing or blocked +system.cpu1.fetch.SquashCycles 724 # Number of cycles fetch has spent squashing +system.cpu1.fetch.BlockedCycles 7460 # Number of cycles fetch has spent blocked +system.cpu1.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu1.fetch.NoActiveThreadStallCycles 10508 # Number of stall cycles due to no active thread to fetch from +system.cpu1.fetch.PendingTrapStallCycles 878 # Number of stall cycles due to pending traps +system.cpu1.fetch.CacheLines 3406 # Number of cache lines fetched +system.cpu1.fetch.IcacheSquashes 96 # Number of outstanding Icache misses that were squashed +system.cpu1.fetch.rateDist::samples 61631 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::mean 1.904285 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::stdev 2.891724 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::0 24571 39.87% 39.87% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::1 24007 38.95% 78.82% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::2 1372 2.23% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::3 85 0.14% 81.18% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::4 22 0.04% 81.22% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::5 36 0.06% 81.28% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::6 1064 1.73% 83.01% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::7 87 0.14% 83.15% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::8 10387 16.85% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.rateDist::total 61631 # Number of instructions fetched each cycle (Total) +system.cpu1.fetch.branchRate 0.213676 # Number of branch fetches per cycle +system.cpu1.fetch.rate 1.875527 # Number of inst fetches per cycle +system.cpu1.decode.IdleCycles 7749 # Number of cycles decode is idle +system.cpu1.decode.BlockedCycles 5955 # Number of cycles decode is blocked +system.cpu1.decode.RunCycles 35736 # Number of cycles decode is running +system.cpu1.decode.UnblockCycles 1230 # Number of cycles decode is unblocking +system.cpu1.decode.SquashCycles 453 # Number of cycles decode is squashing +system.cpu1.decode.DecodedInsts 116821 # Number of instructions handled by decode +system.cpu1.rename.SquashCycles 453 # Number of cycles rename is squashing +system.cpu1.rename.IdleCycles 8169 # Number of cycles rename is idle +system.cpu1.rename.BlockCycles 2283 # Number of cycles rename is blocking +system.cpu1.rename.serializeStallCycles 1162 # count of cycles rename stalled for serializing inst +system.cpu1.rename.RunCycles 35443 # Number of cycles rename is running +system.cpu1.rename.UnblockCycles 3613 # Number of cycles rename is unblocking +system.cpu1.rename.RenamedInsts 116423 # Number of instructions processed by rename +system.cpu1.rename.IQFullEvents 2430 # Number of times rename has blocked due to IQ full +system.cpu1.rename.LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu1.rename.RenamedOperands 110052 # Number of destination operands rename has renamed +system.cpu1.rename.RenameLookups 205243 # Number of register rename lookups that rename has made +system.cpu1.rename.int_rename_lookups 205243 # Number of integer rename lookups +system.cpu1.rename.CommittedMaps 107907 # Number of HB maps that are committed +system.cpu1.rename.UndoneMaps 2145 # Number of HB maps that are undone due to squashing +system.cpu1.rename.serializingInsts 121 # count of serializing insts renamed +system.cpu1.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu1.rename.skidInsts 4632 # count of insts added to the skid buffer +system.cpu1.memDep0.insertedLoads 12867 # Number of loads inserted to the mem dependence unit. +system.cpu1.memDep0.insertedStores 1432 # Number of stores inserted to the mem dependence unit. +system.cpu1.memDep0.conflictingLoads 2279 # Number of conflicting loads. +system.cpu1.memDep0.conflictingStores 1022 # Number of conflicting stores. +system.cpu1.iq.iqInstsAdded 112122 # Number of instructions added to the IQ (excludes non-spec) +system.cpu1.iq.iqNonSpecInstsAdded 1382 # Number of non-speculative instructions added to the IQ +system.cpu1.iq.iqInstsIssued 112903 # Number of instructions issued +system.cpu1.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu1.iq.iqSquashedInstsExamined 1788 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu1.iq.iqSquashedOperandsExamined 1495 # Number of squashed operands that are examined and possibly removed from graph +system.cpu1.iq.iqSquashedNonSpecRemoved 124 # Number of squashed non-spec instructions that were removed +system.cpu1.iq.issued_per_cycle::samples 61631 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::mean 1.831919 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::stdev 1.792007 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::0 22648 36.75% 36.75% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::1 6169 10.01% 46.76% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::2 12281 19.93% 66.68% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::3 10189 16.53% 83.22% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::4 192 0.31% 83.53% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::5 10087 16.37% 99.89% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::6 55 0.09% 99.98% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::7 8 0.01% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::8 2 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu1.iq.issued_per_cycle::total 61631 # Number of insts issued each cycle +system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntAlu 5 21.74% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemRead 1 4.35% 26.09% # attempts to use FU when none available +system.cpu1.iq.fu_full::MemWrite 17 73.91% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IntAlu 97573 86.42% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntMult 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 86.42% # Type of FU issued +system.cpu1.iq.FU_type_0::MemRead 13982 12.38% 98.81% # Type of FU issued +system.cpu1.iq.FU_type_0::MemWrite 1348 1.19% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu1.iq.FU_type_0::total 112903 # Type of FU issued +system.cpu1.iq.rate 1.804254 # Inst issue rate +system.cpu1.iq.fu_busy_cnt 23 # FU busy when requested +system.cpu1.iq.fu_busy_rate 0.000204 # FU busy rate (busy events/executed inst) +system.cpu1.iq.int_inst_queue_reads 287467 # Number of integer instruction queue reads +system.cpu1.iq.int_inst_queue_writes 115298 # Number of integer instruction queue writes +system.cpu1.iq.int_inst_queue_wakeup_accesses 112567 # Number of integer instruction queue wakeup accesses +system.cpu1.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu1.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu1.iq.int_alu_accesses 112926 # Number of integer alu accesses +system.cpu1.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu1.iew.lsq.thread0.forwLoads 1040 # Number of loads that had data forwarded from stores +system.cpu1.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu1.iew.lsq.thread0.squashedLoads 375 # Number of loads squashed +system.cpu1.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu1.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu1.iew.lsq.thread0.squashedStores 245 # Number of stores squashed +system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu1.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu1.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu1.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu1.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu1.iew.iewSquashCycles 453 # Number of cycles IEW is squashing +system.cpu1.iew.iewBlockCycles 33 # Number of cycles IEW is blocking +system.cpu1.iew.iewUnblockCycles 3 # Number of cycles IEW is unblocking +system.cpu1.iew.iewDispatchedInsts 115941 # Number of instructions dispatched to IQ +system.cpu1.iew.iewDispSquashedInsts 81 # Number of squashed instructions skipped by dispatch +system.cpu1.iew.iewDispLoadInsts 12867 # Number of dispatched load instructions +system.cpu1.iew.iewDispStoreInsts 1432 # Number of dispatched store instructions +system.cpu1.iew.iewDispNonSpecInsts 94 # Number of dispatched non-speculative instructions +system.cpu1.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu1.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu1.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu1.iew.predictedTakenIncorrect 39 # Number of branches that were predicted taken incorrectly +system.cpu1.iew.predictedNotTakenIncorrect 237 # Number of branches that were predicted not taken incorrectly +system.cpu1.iew.branchMispredicts 276 # Number of branch mispredicts detected at execute +system.cpu1.iew.iewExecutedInsts 112704 # Number of executed instructions +system.cpu1.iew.iewExecLoadInsts 12737 # Number of load instructions executed +system.cpu1.iew.iewExecSquashedInsts 199 # Number of squashed instructions skipped in execute +system.cpu1.iew.exec_swp 0 # number of swp insts executed +system.cpu1.iew.exec_nop 2437 # number of nop insts executed +system.cpu1.iew.exec_refs 14055 # number of memory reference insts executed +system.cpu1.iew.exec_branches 12804 # Number of branches executed +system.cpu1.iew.exec_stores 1318 # Number of stores executed +system.cpu1.iew.exec_rate 1.801074 # Inst execution rate +system.cpu1.iew.wb_sent 112611 # cumulative count of insts sent to commit +system.cpu1.iew.wb_count 112567 # cumulative count of insts written-back +system.cpu1.iew.wb_producers 96530 # num instructions producing a value +system.cpu1.iew.wb_consumers 106817 # num instructions consuming a value +system.cpu1.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu1.iew.wb_rate 1.798885 # insts written-back per cycle +system.cpu1.iew.wb_fanout 0.903695 # average fanout of values written-back +system.cpu1.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu1.commit.commitCommittedInsts 113743 # The number of committed instructions +system.cpu1.commit.commitCommittedOps 113743 # The number of committed instructions +system.cpu1.commit.commitSquashedInsts 2177 # The number of squashed insts skipped by commit +system.cpu1.commit.commitNonSpecStalls 1258 # The number of times commit has been forced to stall to communicate backwards +system.cpu1.commit.branchMispredicts 240 # The number of times a branch was mispredicted +system.cpu1.commit.committed_per_cycle::samples 50671 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::mean 2.244736 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::stdev 1.835520 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::0 14377 28.37% 28.37% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::1 3653 7.21% 35.58% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::2 10226 20.18% 55.76% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::3 11257 22.22% 77.98% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::4 69 0.14% 78.12% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::5 11025 21.76% 99.87% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::6 16 0.03% 99.91% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::7 14 0.03% 99.93% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::8 34 0.07% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu1.commit.committed_per_cycle::total 50671 # Number of insts commited each cycle +system.cpu1.commit.committedInsts 113743 # Number of instructions committed +system.cpu1.commit.committedOps 113743 # Number of ops (including micro ops) committed +system.cpu1.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu1.commit.refs 13679 # Number of memory references committed +system.cpu1.commit.loads 12492 # Number of loads committed +system.cpu1.commit.membars 1215 # Number of memory barriers committed +system.cpu1.commit.branches 12591 # Number of branches committed +system.cpu1.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu1.commit.int_insts 98985 # Number of committed integer instructions. +system.cpu1.commit.function_calls 15 # Number of function calls committed. +system.cpu1.commit.bw_lim_events 34 # number cycles where commit BW limit reached +system.cpu1.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu1.rob.rob_reads 166230 # The number of ROB reads +system.cpu1.rob.rob_writes 232296 # The number of ROB writes +system.cpu1.timesIdled 58 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu1.idleCycles 945 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu1.quiesceCycles 38719 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu1.committedInsts 110252 # Number of Instructions Simulated +system.cpu1.committedOps 110252 # Number of Ops (including micro ops) Simulated +system.cpu1.committedInsts_total 110252 # Number of Instructions Simulated +system.cpu1.cpi 0.567572 # CPI: Cycles Per Instruction +system.cpu1.cpi_total 0.567572 # CPI: Total CPI of All Threads +system.cpu1.ipc 1.761890 # IPC: Instructions Per Cycle +system.cpu1.ipc_total 1.761890 # IPC: Total IPC of All Threads +system.cpu1.int_regfile_reads 188437 # number of integer regfile reads +system.cpu1.int_regfile_writes 109018 # number of integer regfile writes +system.cpu1.fp_regfile_writes 64 # number of floating regfile writes +system.cpu1.misc_regfile_reads 14213 # number of misc regfile reads +system.cpu1.misc_regfile_writes 58 # number of misc regfile writes +system.cpu1.icache.replacements 20 # number of replacements +system.cpu1.icache.tagsinuse 53.472833 # Cycle average of tags in use +system.cpu1.icache.total_refs 3257 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 125 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 26.056000 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 53.472833 # Average occupied blocks per requestor +system.cpu1.icache.occ_percent::cpu1.inst 0.104439 # Average percentage of cache occupancy +system.cpu1.icache.occ_percent::total 0.104439 # Average percentage of cache occupancy +system.cpu1.icache.ReadReq_hits::cpu1.inst 3257 # number of ReadReq hits +system.cpu1.icache.ReadReq_hits::total 3257 # number of ReadReq hits +system.cpu1.icache.demand_hits::cpu1.inst 3257 # number of demand (read+write) hits +system.cpu1.icache.demand_hits::total 3257 # number of demand (read+write) hits +system.cpu1.icache.overall_hits::cpu1.inst 3257 # number of overall hits +system.cpu1.icache.overall_hits::total 3257 # number of overall hits +system.cpu1.icache.ReadReq_misses::cpu1.inst 149 # number of ReadReq misses +system.cpu1.icache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu1.icache.demand_misses::cpu1.inst 149 # number of demand (read+write) misses +system.cpu1.icache.demand_misses::total 149 # number of demand (read+write) misses +system.cpu1.icache.overall_misses::cpu1.inst 149 # number of overall misses +system.cpu1.icache.overall_misses::total 149 # number of overall misses +system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 2453500 # number of ReadReq miss cycles +system.cpu1.icache.ReadReq_miss_latency::total 2453500 # number of ReadReq miss cycles +system.cpu1.icache.demand_miss_latency::cpu1.inst 2453500 # number of demand (read+write) miss cycles +system.cpu1.icache.demand_miss_latency::total 2453500 # number of demand (read+write) miss cycles +system.cpu1.icache.overall_miss_latency::cpu1.inst 2453500 # number of overall miss cycles +system.cpu1.icache.overall_miss_latency::total 2453500 # number of overall miss cycles +system.cpu1.icache.ReadReq_accesses::cpu1.inst 3406 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.ReadReq_accesses::total 3406 # number of ReadReq accesses(hits+misses) +system.cpu1.icache.demand_accesses::cpu1.inst 3406 # number of demand (read+write) accesses +system.cpu1.icache.demand_accesses::total 3406 # number of demand (read+write) accesses +system.cpu1.icache.overall_accesses::cpu1.inst 3406 # number of overall (read+write) accesses +system.cpu1.icache.overall_accesses::total 3406 # number of overall (read+write) accesses +system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.043746 # miss rate for ReadReq accesses +system.cpu1.icache.demand_miss_rate::cpu1.inst 0.043746 # miss rate for demand accesses +system.cpu1.icache.overall_miss_rate::cpu1.inst 0.043746 # miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 16466.442953 # average ReadReq miss latency +system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 16466.442953 # average overall miss latency +system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 16466.442953 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 24 # number of ReadReq MSHR hits +system.cpu1.icache.ReadReq_mshr_hits::total 24 # number of ReadReq MSHR hits +system.cpu1.icache.demand_mshr_hits::cpu1.inst 24 # number of demand (read+write) MSHR hits +system.cpu1.icache.demand_mshr_hits::total 24 # number of demand (read+write) MSHR hits +system.cpu1.icache.overall_mshr_hits::cpu1.inst 24 # number of overall MSHR hits +system.cpu1.icache.overall_mshr_hits::total 24 # number of overall MSHR hits +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 125 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 125 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 125 # number of demand (read+write) MSHR misses +system.cpu1.icache.demand_mshr_misses::total 125 # number of demand (read+write) MSHR misses +system.cpu1.icache.overall_mshr_misses::cpu1.inst 125 # number of overall MSHR misses +system.cpu1.icache.overall_mshr_misses::total 125 # number of overall MSHR misses +system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 1775000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_latency::total 1775000 # number of ReadReq MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 1775000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.demand_mshr_miss_latency::total 1775000 # number of demand (read+write) MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 1775000 # number of overall MSHR miss cycles +system.cpu1.icache.overall_mshr_miss_latency::total 1775000 # number of overall MSHR miss cycles +system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.036700 # mshr miss rate for ReadReq accesses +system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.036700 # mshr miss rate for demand accesses +system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.036700 # mshr miss rate for overall accesses +system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 14200 # average ReadReq mshr miss latency +system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 14200 # average overall mshr miss latency +system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 14200 # average overall mshr miss latency +system.cpu1.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.dcache.replacements 0 # number of replacements +system.cpu1.dcache.tagsinuse 18.658279 # Cycle average of tags in use +system.cpu1.dcache.total_refs 11442 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 369.096774 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 18.658279 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.036442 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.036442 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 11636 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11636 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1142 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1142 # number of WriteReq hits +system.cpu1.dcache.demand_hits::cpu1.data 12778 # number of demand (read+write) hits +system.cpu1.dcache.demand_hits::total 12778 # number of demand (read+write) hits +system.cpu1.dcache.overall_hits::cpu1.data 12778 # number of overall hits +system.cpu1.dcache.overall_hits::total 12778 # number of overall hits +system.cpu1.dcache.ReadReq_misses::cpu1.data 44 # number of ReadReq misses +system.cpu1.dcache.ReadReq_misses::total 44 # number of ReadReq misses +system.cpu1.dcache.WriteReq_misses::cpu1.data 41 # number of WriteReq misses +system.cpu1.dcache.WriteReq_misses::total 41 # number of WriteReq misses +system.cpu1.dcache.SwapReq_misses::cpu1.data 4 # number of SwapReq misses +system.cpu1.dcache.SwapReq_misses::total 4 # number of SwapReq misses +system.cpu1.dcache.demand_misses::cpu1.data 85 # number of demand (read+write) misses +system.cpu1.dcache.demand_misses::total 85 # number of demand (read+write) misses +system.cpu1.dcache.overall_misses::cpu1.data 85 # number of overall misses +system.cpu1.dcache.overall_misses::total 85 # number of overall misses +system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 604000 # number of ReadReq miss cycles +system.cpu1.dcache.ReadReq_miss_latency::total 604000 # number of ReadReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 1968500 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 1968500 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 23000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 23000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 2572500 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 2572500 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 2572500 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 2572500 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 11680 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 11680 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::total 1183 # number of WriteReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::cpu1.data 4 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.SwapReq_accesses::total 4 # number of SwapReq accesses(hits+misses) +system.cpu1.dcache.demand_accesses::cpu1.data 12863 # number of demand (read+write) accesses +system.cpu1.dcache.demand_accesses::total 12863 # number of demand (read+write) accesses +system.cpu1.dcache.overall_accesses::cpu1.data 12863 # number of overall (read+write) accesses +system.cpu1.dcache.overall_accesses::total 12863 # number of overall (read+write) accesses +system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.003767 # miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.034658 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 1 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.006608 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.006608 # miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 13727.272727 # average ReadReq miss latency +system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 48012.195122 # average WriteReq miss latency +system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 5750 # average SwapReq miss latency +system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 30264.705882 # average overall miss latency +system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 30264.705882 # average overall miss latency +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed +system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 13 # number of ReadReq MSHR hits +system.cpu1.dcache.ReadReq_mshr_hits::total 13 # number of ReadReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 25 # number of WriteReq MSHR hits +system.cpu1.dcache.WriteReq_mshr_hits::total 25 # number of WriteReq MSHR hits +system.cpu1.dcache.demand_mshr_hits::cpu1.data 38 # number of demand (read+write) MSHR hits +system.cpu1.dcache.demand_mshr_hits::total 38 # number of demand (read+write) MSHR hits +system.cpu1.dcache.overall_mshr_hits::cpu1.data 38 # number of overall MSHR hits +system.cpu1.dcache.overall_mshr_hits::total 38 # number of overall MSHR hits +system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 31 # number of ReadReq MSHR misses +system.cpu1.dcache.ReadReq_mshr_misses::total 31 # number of ReadReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 16 # number of WriteReq MSHR misses +system.cpu1.dcache.WriteReq_mshr_misses::total 16 # number of WriteReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 4 # number of SwapReq MSHR misses +system.cpu1.dcache.SwapReq_mshr_misses::total 4 # number of SwapReq MSHR misses +system.cpu1.dcache.demand_mshr_misses::cpu1.data 47 # number of demand (read+write) MSHR misses +system.cpu1.dcache.demand_mshr_misses::total 47 # number of demand (read+write) MSHR misses +system.cpu1.dcache.overall_mshr_misses::cpu1.data 47 # number of overall MSHR misses +system.cpu1.dcache.overall_mshr_misses::total 47 # number of overall MSHR misses +system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 348500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_latency::total 348500 # number of ReadReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.WriteReq_mshr_miss_latency::total 665500 # number of WriteReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 11000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.SwapReq_mshr_miss_latency::total 11000 # number of SwapReq MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 1014000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.demand_mshr_miss_latency::total 1014000 # number of demand (read+write) MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 1014000 # number of overall MSHR miss cycles +system.cpu1.dcache.overall_mshr_miss_latency::total 1014000 # number of overall MSHR miss cycles +system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.002654 # mshr miss rate for ReadReq accesses +system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.013525 # mshr miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for SwapReq accesses +system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003654 # mshr miss rate for demand accesses +system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003654 # mshr miss rate for overall accesses +system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 11241.935484 # average ReadReq mshr miss latency +system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 41593.750000 # average WriteReq mshr miss latency +system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 2750 # average SwapReq mshr miss latency +system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 21574.468085 # average overall mshr miss latency +system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 21574.468085 # average overall mshr miss latency +system.cpu1.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.numCycles 62227 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.BPredUnit.lookups 12896 # Number of BP lookups +system.cpu2.BPredUnit.condPredicted 12478 # Number of conditional branches predicted +system.cpu2.BPredUnit.condIncorrect 239 # Number of conditional branches incorrect +system.cpu2.BPredUnit.BTBLookups 12653 # Number of BTB lookups +system.cpu2.BPredUnit.BTBHits 11986 # Number of BTB hits +system.cpu2.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu2.BPredUnit.usedRAS 84 # Number of times the RAS was used to get a target. +system.cpu2.BPredUnit.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu2.fetch.icacheStallCycles 4173 # Number of cycles fetch is stalled on an Icache miss +system.cpu2.fetch.Insts 115486 # Number of instructions fetch has processed +system.cpu2.fetch.Branches 12896 # Number of branches that fetch encountered +system.cpu2.fetch.predictedBranches 12070 # Number of branches that fetch has predicted taken +system.cpu2.fetch.Cycles 35636 # Number of cycles fetch has run and was not squashing or blocked +system.cpu2.fetch.SquashCycles 714 # Number of cycles fetch has spent squashing +system.cpu2.fetch.BlockedCycles 5741 # Number of cycles fetch has spent blocked +system.cpu2.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu2.fetch.NoActiveThreadStallCycles 14670 # Number of stall cycles due to no active thread to fetch from +system.cpu2.fetch.PendingTrapStallCycles 914 # Number of stall cycles due to pending traps +system.cpu2.fetch.CacheLines 2455 # Number of cache lines fetched +system.cpu2.fetch.IcacheSquashes 95 # Number of outstanding Icache misses that were squashed +system.cpu2.fetch.rateDist::samples 61582 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::mean 1.875321 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::stdev 2.904886 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::0 25946 42.13% 42.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::1 23057 37.44% 79.57% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::2 895 1.45% 81.03% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::3 84 0.14% 81.16% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::4 23 0.04% 81.20% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::5 36 0.06% 81.26% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::6 1063 1.73% 82.99% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::7 87 0.14% 83.13% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::8 10391 16.87% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.rateDist::total 61582 # Number of instructions fetched each cycle (Total) +system.cpu2.fetch.branchRate 0.207241 # Number of branch fetches per cycle +system.cpu2.fetch.rate 1.855882 # Number of inst fetches per cycle +system.cpu2.decode.IdleCycles 6335 # Number of cycles decode is idle +system.cpu2.decode.BlockedCycles 4590 # Number of cycles decode is blocked +system.cpu2.decode.RunCycles 34525 # Number of cycles decode is running +system.cpu2.decode.UnblockCycles 1018 # Number of cycles decode is unblocking +system.cpu2.decode.SquashCycles 444 # Number of cycles decode is squashing +system.cpu2.decode.DecodedInsts 114954 # Number of instructions handled by decode +system.cpu2.rename.SquashCycles 444 # Number of cycles rename is squashing +system.cpu2.rename.IdleCycles 6754 # Number of cycles rename is idle +system.cpu2.rename.BlockCycles 1429 # Number of cycles rename is blocking +system.cpu2.rename.serializeStallCycles 1077 # count of cycles rename stalled for serializing inst +system.cpu2.rename.RunCycles 34442 # Number of cycles rename is running +system.cpu2.rename.UnblockCycles 2766 # Number of cycles rename is unblocking +system.cpu2.rename.RenamedInsts 114539 # Number of instructions processed by rename +system.cpu2.rename.IQFullEvents 2006 # Number of times rename has blocked due to IQ full +system.cpu2.rename.LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu2.rename.RenamedOperands 109602 # Number of destination operands rename has renamed +system.cpu2.rename.RenameLookups 203385 # Number of register rename lookups that rename has made +system.cpu2.rename.int_rename_lookups 203385 # Number of integer rename lookups +system.cpu2.rename.CommittedMaps 107451 # Number of HB maps that are committed +system.cpu2.rename.UndoneMaps 2151 # Number of HB maps that are undone due to squashing +system.cpu2.rename.serializingInsts 121 # count of serializing insts renamed +system.cpu2.rename.tempSerializingInsts 133 # count of temporary serializing insts renamed +system.cpu2.rename.skidInsts 3785 # count of insts added to the skid buffer +system.cpu2.memDep0.insertedLoads 12395 # Number of loads inserted to the mem dependence unit. +system.cpu2.memDep0.insertedStores 1432 # Number of stores inserted to the mem dependence unit. +system.cpu2.memDep0.conflictingLoads 1804 # Number of conflicting loads. +system.cpu2.memDep0.conflictingStores 1022 # Number of conflicting stores. +system.cpu2.iq.iqInstsAdded 111191 # Number of instructions added to the IQ (excludes non-spec) +system.cpu2.iq.iqNonSpecInstsAdded 904 # Number of non-speculative instructions added to the IQ +system.cpu2.iq.iqInstsIssued 111542 # Number of instructions issued +system.cpu2.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu2.iq.iqSquashedInstsExamined 1748 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu2.iq.iqSquashedOperandsExamined 1448 # Number of squashed operands that are examined and possibly removed from graph +system.cpu2.iq.iqSquashedNonSpecRemoved 103 # Number of squashed non-spec instructions that were removed +system.cpu2.iq.issued_per_cycle::samples 61582 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::mean 1.811276 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::stdev 1.808201 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::0 23963 38.91% 38.91% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::1 4802 7.80% 46.71% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::2 12283 19.95% 66.66% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::3 10190 16.55% 83.20% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::4 192 0.31% 83.51% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::5 10087 16.38% 99.89% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::6 56 0.09% 99.99% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::7 7 0.01% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::8 2 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu2.iq.issued_per_cycle::total 61582 # Number of insts issued each cycle +system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntAlu 5 21.74% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::IntDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShift 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 21.74% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemRead 1 4.35% 26.09% # attempts to use FU when none available +system.cpu2.iq.fu_full::MemWrite 17 73.91% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IntAlu 97120 87.07% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntMult 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 87.07% # Type of FU issued +system.cpu2.iq.FU_type_0::MemRead 13075 11.72% 98.79% # Type of FU issued +system.cpu2.iq.FU_type_0::MemWrite 1347 1.21% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu2.iq.FU_type_0::total 111542 # Type of FU issued +system.cpu2.iq.rate 1.792502 # Inst issue rate +system.cpu2.iq.fu_busy_cnt 23 # FU busy when requested +system.cpu2.iq.fu_busy_rate 0.000206 # FU busy rate (busy events/executed inst) +system.cpu2.iq.int_inst_queue_reads 284696 # Number of integer instruction queue reads +system.cpu2.iq.int_inst_queue_writes 113849 # Number of integer instruction queue writes +system.cpu2.iq.int_inst_queue_wakeup_accesses 111203 # Number of integer instruction queue wakeup accesses +system.cpu2.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu2.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu2.iq.int_alu_accesses 111565 # Number of integer alu accesses +system.cpu2.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu2.iew.lsq.thread0.forwLoads 1040 # Number of loads that had data forwarded from stores +system.cpu2.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu2.iew.lsq.thread0.squashedLoads 358 # Number of loads squashed +system.cpu2.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu2.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu2.iew.lsq.thread0.squashedStores 246 # Number of stores squashed +system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu2.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu2.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu2.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu2.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu2.iew.iewSquashCycles 444 # Number of cycles IEW is squashing +system.cpu2.iew.iewBlockCycles 25 # Number of cycles IEW is blocking +system.cpu2.iew.iewUnblockCycles 2 # Number of cycles IEW is unblocking +system.cpu2.iew.iewDispatchedInsts 114057 # Number of instructions dispatched to IQ +system.cpu2.iew.iewDispSquashedInsts 87 # Number of squashed instructions skipped by dispatch +system.cpu2.iew.iewDispLoadInsts 12395 # Number of dispatched load instructions +system.cpu2.iew.iewDispStoreInsts 1432 # Number of dispatched store instructions +system.cpu2.iew.iewDispNonSpecInsts 93 # Number of dispatched non-speculative instructions +system.cpu2.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu2.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu2.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu2.iew.predictedTakenIncorrect 38 # Number of branches that were predicted taken incorrectly +system.cpu2.iew.predictedNotTakenIncorrect 237 # Number of branches that were predicted not taken incorrectly +system.cpu2.iew.branchMispredicts 275 # Number of branch mispredicts detected at execute +system.cpu2.iew.iewExecutedInsts 111342 # Number of executed instructions +system.cpu2.iew.iewExecLoadInsts 12286 # Number of load instructions executed +system.cpu2.iew.iewExecSquashedInsts 200 # Number of squashed instructions skipped in execute +system.cpu2.iew.exec_swp 0 # number of swp insts executed +system.cpu2.iew.exec_nop 1962 # number of nop insts executed +system.cpu2.iew.exec_refs 13603 # number of memory reference insts executed +system.cpu2.iew.exec_branches 12349 # Number of branches executed +system.cpu2.iew.exec_stores 1317 # Number of stores executed +system.cpu2.iew.exec_rate 1.789288 # Inst execution rate +system.cpu2.iew.wb_sent 111251 # cumulative count of insts sent to commit +system.cpu2.iew.wb_count 111203 # cumulative count of insts written-back +system.cpu2.iew.wb_producers 96076 # num instructions producing a value +system.cpu2.iew.wb_consumers 106364 # num instructions consuming a value +system.cpu2.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu2.iew.wb_rate 1.787054 # insts written-back per cycle +system.cpu2.iew.wb_fanout 0.903276 # average fanout of values written-back +system.cpu2.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu2.commit.commitCommittedInsts 111918 # The number of committed instructions +system.cpu2.commit.commitCommittedOps 111918 # The number of committed instructions +system.cpu2.commit.commitSquashedInsts 2110 # The number of squashed insts skipped by commit +system.cpu2.commit.commitNonSpecStalls 801 # The number of times commit has been forced to stall to communicate backwards +system.cpu2.commit.branchMispredicts 239 # The number of times a branch was mispredicted +system.cpu2.commit.committed_per_cycle::samples 46469 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::mean 2.408444 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::stdev 1.808429 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::0 11090 23.87% 23.87% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::1 3196 6.88% 30.74% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::2 10225 22.00% 52.75% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::3 10799 23.24% 75.99% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::4 69 0.15% 76.13% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::5 11025 23.73% 99.86% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::6 16 0.03% 99.89% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::7 14 0.03% 99.92% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::8 35 0.08% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu2.commit.committed_per_cycle::total 46469 # Number of insts commited each cycle +system.cpu2.commit.committedInsts 111918 # Number of instructions committed +system.cpu2.commit.committedOps 111918 # Number of ops (including micro ops) committed +system.cpu2.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu2.commit.refs 13223 # Number of memory references committed +system.cpu2.commit.loads 12037 # Number of loads committed +system.cpu2.commit.membars 759 # Number of memory barriers committed +system.cpu2.commit.branches 12134 # Number of branches committed +system.cpu2.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu2.commit.int_insts 98073 # Number of committed integer instructions. +system.cpu2.commit.function_calls 15 # Number of function calls committed. +system.cpu2.commit.bw_lim_events 35 # number cycles where commit BW limit reached +system.cpu2.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu2.rob.rob_reads 160135 # The number of ROB reads +system.cpu2.rob.rob_writes 228503 # The number of ROB writes +system.cpu2.timesIdled 55 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu2.idleCycles 645 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu2.quiesceCycles 39068 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu2.committedInsts 109339 # Number of Instructions Simulated +system.cpu2.committedOps 109339 # Number of Ops (including micro ops) Simulated +system.cpu2.committedInsts_total 109339 # Number of Instructions Simulated +system.cpu2.cpi 0.569120 # CPI: Cycles Per Instruction +system.cpu2.cpi_total 0.569120 # CPI: Total CPI of All Threads +system.cpu2.ipc 1.757099 # IPC: Instructions Per Cycle +system.cpu2.ipc_total 1.757099 # IPC: Total IPC of All Threads +system.cpu2.int_regfile_reads 187073 # number of integer regfile reads +system.cpu2.int_regfile_writes 108568 # number of integer regfile writes +system.cpu2.fp_regfile_writes 64 # number of floating regfile writes +system.cpu2.misc_regfile_reads 13763 # number of misc regfile reads +system.cpu2.misc_regfile_writes 58 # number of misc regfile writes +system.cpu2.icache.replacements 21 # number of replacements +system.cpu2.icache.tagsinuse 56.418714 # Cycle average of tags in use +system.cpu2.icache.total_refs 2307 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 126 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 18.309524 # Average number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.occ_blocks::cpu2.inst 56.418714 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.110193 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.110193 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 2307 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 2307 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 2307 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 2307 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 2307 # number of overall hits +system.cpu2.icache.overall_hits::total 2307 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 148 # number of ReadReq misses +system.cpu2.icache.ReadReq_misses::total 148 # number of ReadReq misses +system.cpu2.icache.demand_misses::cpu2.inst 148 # number of demand (read+write) misses +system.cpu2.icache.demand_misses::total 148 # number of demand (read+write) misses +system.cpu2.icache.overall_misses::cpu2.inst 148 # number of overall misses +system.cpu2.icache.overall_misses::total 148 # number of overall misses +system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 2107000 # number of ReadReq miss cycles +system.cpu2.icache.ReadReq_miss_latency::total 2107000 # number of ReadReq miss cycles +system.cpu2.icache.demand_miss_latency::cpu2.inst 2107000 # number of demand (read+write) miss cycles +system.cpu2.icache.demand_miss_latency::total 2107000 # number of demand (read+write) miss cycles +system.cpu2.icache.overall_miss_latency::cpu2.inst 2107000 # number of overall miss cycles +system.cpu2.icache.overall_miss_latency::total 2107000 # number of overall miss cycles +system.cpu2.icache.ReadReq_accesses::cpu2.inst 2455 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.ReadReq_accesses::total 2455 # number of ReadReq accesses(hits+misses) +system.cpu2.icache.demand_accesses::cpu2.inst 2455 # number of demand (read+write) accesses +system.cpu2.icache.demand_accesses::total 2455 # number of demand (read+write) accesses +system.cpu2.icache.overall_accesses::cpu2.inst 2455 # number of overall (read+write) accesses +system.cpu2.icache.overall_accesses::total 2455 # number of overall (read+write) accesses +system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.060285 # miss rate for ReadReq accesses +system.cpu2.icache.demand_miss_rate::cpu2.inst 0.060285 # miss rate for demand accesses +system.cpu2.icache.overall_miss_rate::cpu2.inst 0.060285 # miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 14236.486486 # average ReadReq miss latency +system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 14236.486486 # average overall miss latency +system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 14236.486486 # average overall miss latency +system.cpu2.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.icache.fast_writes 0 # number of fast writes performed +system.cpu2.icache.cache_copies 0 # number of cache copies performed +system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 22 # number of ReadReq MSHR hits +system.cpu2.icache.ReadReq_mshr_hits::total 22 # number of ReadReq MSHR hits +system.cpu2.icache.demand_mshr_hits::cpu2.inst 22 # number of demand (read+write) MSHR hits +system.cpu2.icache.demand_mshr_hits::total 22 # number of demand (read+write) MSHR hits +system.cpu2.icache.overall_mshr_hits::cpu2.inst 22 # number of overall MSHR hits +system.cpu2.icache.overall_mshr_hits::total 22 # number of overall MSHR hits +system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 126 # number of ReadReq MSHR misses +system.cpu2.icache.ReadReq_mshr_misses::total 126 # number of ReadReq MSHR misses +system.cpu2.icache.demand_mshr_misses::cpu2.inst 126 # number of demand (read+write) MSHR misses +system.cpu2.icache.demand_mshr_misses::total 126 # number of demand (read+write) MSHR misses +system.cpu2.icache.overall_mshr_misses::cpu2.inst 126 # number of overall MSHR misses +system.cpu2.icache.overall_mshr_misses::total 126 # number of overall MSHR misses +system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 1504500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_latency::total 1504500 # number of ReadReq MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 1504500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.demand_mshr_miss_latency::total 1504500 # number of demand (read+write) MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 1504500 # number of overall MSHR miss cycles +system.cpu2.icache.overall_mshr_miss_latency::total 1504500 # number of overall MSHR miss cycles +system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.051324 # mshr miss rate for ReadReq accesses +system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.051324 # mshr miss rate for demand accesses +system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.051324 # mshr miss rate for overall accesses +system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 11940.476190 # average ReadReq mshr miss latency +system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 11940.476190 # average overall mshr miss latency +system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 11940.476190 # average overall mshr miss latency +system.cpu2.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 18.537475 # Cycle average of tags in use +system.cpu2.dcache.total_refs 11438 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 368.967742 # Average number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.occ_blocks::cpu2.data 18.537475 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.036206 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.036206 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 11178 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 11178 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 1143 # number of WriteReq hits +system.cpu2.dcache.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu2.dcache.demand_hits::cpu2.data 12321 # number of demand (read+write) hits +system.cpu2.dcache.demand_hits::total 12321 # number of demand (read+write) hits +system.cpu2.dcache.overall_hits::cpu2.data 12321 # number of overall hits +system.cpu2.dcache.overall_hits::total 12321 # number of overall hits +system.cpu2.dcache.ReadReq_misses::cpu2.data 48 # number of ReadReq misses +system.cpu2.dcache.ReadReq_misses::total 48 # number of ReadReq misses +system.cpu2.dcache.WriteReq_misses::cpu2.data 40 # number of WriteReq misses +system.cpu2.dcache.WriteReq_misses::total 40 # number of WriteReq misses +system.cpu2.dcache.SwapReq_misses::cpu2.data 3 # number of SwapReq misses +system.cpu2.dcache.SwapReq_misses::total 3 # number of SwapReq misses +system.cpu2.dcache.demand_misses::cpu2.data 88 # number of demand (read+write) misses +system.cpu2.dcache.demand_misses::total 88 # number of demand (read+write) misses +system.cpu2.dcache.overall_misses::cpu2.data 88 # number of overall misses +system.cpu2.dcache.overall_misses::total 88 # number of overall misses +system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 640500 # number of ReadReq miss cycles +system.cpu2.dcache.ReadReq_miss_latency::total 640500 # number of ReadReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 1853500 # number of WriteReq miss cycles +system.cpu2.dcache.WriteReq_miss_latency::total 1853500 # number of WriteReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 17500 # number of SwapReq miss cycles +system.cpu2.dcache.SwapReq_miss_latency::total 17500 # number of SwapReq miss cycles +system.cpu2.dcache.demand_miss_latency::cpu2.data 2494000 # number of demand (read+write) miss cycles +system.cpu2.dcache.demand_miss_latency::total 2494000 # number of demand (read+write) miss cycles +system.cpu2.dcache.overall_miss_latency::cpu2.data 2494000 # number of overall miss cycles +system.cpu2.dcache.overall_miss_latency::total 2494000 # number of overall miss cycles +system.cpu2.dcache.ReadReq_accesses::cpu2.data 11226 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.ReadReq_accesses::total 11226 # number of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 1183 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 1183 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::cpu2.data 3 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.SwapReq_accesses::total 3 # number of SwapReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 12409 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 12409 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 12409 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 12409 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.004276 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.033812 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 1 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.007092 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.007092 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 13343.750000 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 46337.500000 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 5833.333333 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 28340.909091 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 28340.909091 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu2.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu2.dcache.fast_writes 0 # number of fast writes performed +system.cpu2.dcache.cache_copies 0 # number of cache copies performed +system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 18 # number of ReadReq MSHR hits +system.cpu2.dcache.ReadReq_mshr_hits::total 18 # number of ReadReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 24 # number of WriteReq MSHR hits +system.cpu2.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits +system.cpu2.dcache.demand_mshr_hits::cpu2.data 42 # number of demand (read+write) MSHR hits +system.cpu2.dcache.demand_mshr_hits::total 42 # number of demand (read+write) MSHR hits +system.cpu2.dcache.overall_mshr_hits::cpu2.data 42 # number of overall MSHR hits +system.cpu2.dcache.overall_mshr_hits::total 42 # number of overall MSHR hits +system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 30 # number of ReadReq MSHR misses +system.cpu2.dcache.ReadReq_mshr_misses::total 30 # number of ReadReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 16 # number of WriteReq MSHR misses +system.cpu2.dcache.WriteReq_mshr_misses::total 16 # number of WriteReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 3 # number of SwapReq MSHR misses +system.cpu2.dcache.SwapReq_mshr_misses::total 3 # number of SwapReq MSHR misses +system.cpu2.dcache.demand_mshr_misses::cpu2.data 46 # number of demand (read+write) MSHR misses +system.cpu2.dcache.demand_mshr_misses::total 46 # number of demand (read+write) MSHR misses +system.cpu2.dcache.overall_mshr_misses::cpu2.data 46 # number of overall MSHR misses +system.cpu2.dcache.overall_mshr_misses::total 46 # number of overall MSHR misses +system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 357000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_latency::total 357000 # number of ReadReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 613000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.WriteReq_mshr_miss_latency::total 613000 # number of WriteReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 8500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.SwapReq_mshr_miss_latency::total 8500 # number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 970000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 970000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 970000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 970000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.002672 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.013525 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003707 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003707 # mshr miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 11900 # average ReadReq mshr miss latency +system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 38312.500000 # average WriteReq mshr miss latency +system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 2833.333333 # average SwapReq mshr miss latency +system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 21086.956522 # average overall mshr miss latency +system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 21086.956522 # average overall mshr miss latency +system.cpu2.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.numCycles 61899 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.BPredUnit.lookups 12367 # Number of BP lookups +system.cpu3.BPredUnit.condPredicted 11967 # Number of conditional branches predicted +system.cpu3.BPredUnit.condIncorrect 232 # Number of conditional branches incorrect +system.cpu3.BPredUnit.BTBLookups 12137 # Number of BTB lookups +system.cpu3.BPredUnit.BTBHits 11492 # Number of BTB hits +system.cpu3.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. +system.cpu3.BPredUnit.usedRAS 77 # Number of times the RAS was used to get a target. +system.cpu3.BPredUnit.RASInCorrect 15 # Number of incorrect RAS predictions. +system.cpu3.fetch.icacheStallCycles 3147 # Number of cycles fetch is stalled on an Icache miss +system.cpu3.fetch.Insts 113374 # Number of instructions fetch has processed +system.cpu3.fetch.Branches 12367 # Number of branches that fetch encountered +system.cpu3.fetch.predictedBranches 11569 # Number of branches that fetch has predicted taken +system.cpu3.fetch.Cycles 34108 # Number of cycles fetch has run and was not squashing or blocked +system.cpu3.fetch.SquashCycles 693 # Number of cycles fetch has spent squashing +system.cpu3.fetch.BlockedCycles 3817 # Number of cycles fetch has spent blocked +system.cpu3.fetch.MiscStallCycles 4 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs +system.cpu3.fetch.NoActiveThreadStallCycles 18742 # Number of stall cycles due to no active thread to fetch from +system.cpu3.fetch.PendingTrapStallCycles 911 # Number of stall cycles due to pending traps +system.cpu3.fetch.CacheLines 1424 # Number of cache lines fetched +system.cpu3.fetch.IcacheSquashes 101 # Number of outstanding Icache misses that were squashed +system.cpu3.fetch.rateDist::samples 61159 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::mean 1.853758 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::stdev 2.922486 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::0 27051 44.23% 44.23% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::1 22050 36.05% 80.28% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::2 387 0.63% 80.92% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::3 82 0.13% 81.05% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::4 23 0.04% 81.09% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::5 33 0.05% 81.14% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::6 1064 1.74% 82.88% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::7 89 0.15% 83.03% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::8 10380 16.97% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.rateDist::total 61159 # Number of instructions fetched each cycle (Total) +system.cpu3.fetch.branchRate 0.199793 # Number of branch fetches per cycle +system.cpu3.fetch.rate 1.831597 # Number of inst fetches per cycle +system.cpu3.decode.IdleCycles 4841 # Number of cycles decode is idle +system.cpu3.decode.BlockedCycles 3128 # Number of cycles decode is blocked +system.cpu3.decode.RunCycles 33233 # Number of cycles decode is running +system.cpu3.decode.UnblockCycles 785 # Number of cycles decode is unblocking +system.cpu3.decode.SquashCycles 430 # Number of cycles decode is squashing +system.cpu3.decode.DecodedInsts 112868 # Number of instructions handled by decode +system.cpu3.rename.SquashCycles 430 # Number of cycles rename is squashing +system.cpu3.rename.IdleCycles 5255 # Number of cycles rename is idle +system.cpu3.rename.BlockCycles 476 # Number of cycles rename is blocking +system.cpu3.rename.serializeStallCycles 1038 # count of cycles rename stalled for serializing inst +system.cpu3.rename.RunCycles 33389 # Number of cycles rename is running +system.cpu3.rename.UnblockCycles 1829 # Number of cycles rename is unblocking +system.cpu3.rename.RenamedInsts 112481 # Number of instructions processed by rename +system.cpu3.rename.IQFullEvents 1538 # Number of times rename has blocked due to IQ full +system.cpu3.rename.LSQFullEvents 5 # Number of times rename has blocked due to LSQ full +system.cpu3.rename.RenamedOperands 109069 # Number of destination operands rename has renamed +system.cpu3.rename.RenameLookups 201289 # Number of register rename lookups that rename has made +system.cpu3.rename.int_rename_lookups 201289 # Number of integer rename lookups +system.cpu3.rename.CommittedMaps 106966 # Number of HB maps that are committed +system.cpu3.rename.UndoneMaps 2103 # Number of HB maps that are undone due to squashing +system.cpu3.rename.serializingInsts 114 # count of serializing insts renamed +system.cpu3.rename.tempSerializingInsts 126 # count of temporary serializing insts renamed +system.cpu3.rename.skidInsts 2837 # count of insts added to the skid buffer +system.cpu3.memDep0.insertedLoads 11889 # Number of loads inserted to the mem dependence unit. +system.cpu3.memDep0.insertedStores 1427 # Number of stores inserted to the mem dependence unit. +system.cpu3.memDep0.conflictingLoads 1300 # Number of conflicting loads. +system.cpu3.memDep0.conflictingStores 1021 # Number of conflicting stores. +system.cpu3.iq.iqInstsAdded 110188 # Number of instructions added to the IQ (excludes non-spec) +system.cpu3.iq.iqNonSpecInstsAdded 390 # Number of non-speculative instructions added to the IQ +system.cpu3.iq.iqInstsIssued 110097 # Number of instructions issued +system.cpu3.iq.iqSquashedInstsIssued 7 # Number of squashed instructions issued +system.cpu3.iq.iqSquashedInstsExamined 1701 # Number of squashed instructions iterated over during squash; mainly for profiling +system.cpu3.iq.iqSquashedOperandsExamined 1366 # Number of squashed operands that are examined and possibly removed from graph +system.cpu3.iq.iqSquashedNonSpecRemoved 75 # Number of squashed non-spec instructions that were removed +system.cpu3.iq.issued_per_cycle::samples 61159 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::mean 1.800177 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::stdev 1.825361 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::0 24999 40.88% 40.88% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::1 3335 5.45% 46.33% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::2 12283 20.08% 66.41% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::3 10202 16.68% 83.09% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::4 184 0.30% 83.39% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::5 10093 16.50% 99.90% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::6 54 0.09% 99.99% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::7 7 0.01% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::8 2 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle +system.cpu3.iq.issued_per_cycle::total 61159 # Number of insts issued each cycle +system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntAlu 4 18.18% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntMult 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::IntDiv 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatAdd 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCmp 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatCvt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatMult 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatDiv 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAdd 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdAlu 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCmp 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdCvt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMisc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMult 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShift 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 18.18% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemRead 1 4.55% 22.73% # attempts to use FU when none available +system.cpu3.iq.fu_full::MemWrite 17 77.27% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available +system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IntAlu 96645 87.78% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntMult 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 87.78% # Type of FU issued +system.cpu3.iq.FU_type_0::MemRead 12103 10.99% 98.77% # Type of FU issued +system.cpu3.iq.FU_type_0::MemWrite 1349 1.23% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued +system.cpu3.iq.FU_type_0::total 110097 # Type of FU issued +system.cpu3.iq.rate 1.778656 # Inst issue rate +system.cpu3.iq.fu_busy_cnt 22 # FU busy when requested +system.cpu3.iq.fu_busy_rate 0.000200 # FU busy rate (busy events/executed inst) +system.cpu3.iq.int_inst_queue_reads 281382 # Number of integer instruction queue reads +system.cpu3.iq.int_inst_queue_writes 112285 # Number of integer instruction queue writes +system.cpu3.iq.int_inst_queue_wakeup_accesses 109756 # Number of integer instruction queue wakeup accesses +system.cpu3.iq.fp_inst_queue_reads 0 # Number of floating instruction queue reads +system.cpu3.iq.fp_inst_queue_writes 0 # Number of floating instruction queue writes +system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 # Number of floating instruction queue wakeup accesses +system.cpu3.iq.int_alu_accesses 110119 # Number of integer alu accesses +system.cpu3.iq.fp_alu_accesses 0 # Number of floating point alu accesses +system.cpu3.iew.lsq.thread0.forwLoads 1040 # Number of loads that had data forwarded from stores +system.cpu3.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address +system.cpu3.iew.lsq.thread0.squashedLoads 336 # Number of loads squashed +system.cpu3.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed +system.cpu3.iew.lsq.thread0.memOrderViolation 6 # Number of memory ordering violations +system.cpu3.iew.lsq.thread0.squashedStores 242 # Number of stores squashed +system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address +system.cpu3.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding +system.cpu3.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled +system.cpu3.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked +system.cpu3.iew.iewIdleCycles 0 # Number of cycles IEW is idle +system.cpu3.iew.iewSquashCycles 430 # Number of cycles IEW is squashing +system.cpu3.iew.iewBlockCycles 12 # Number of cycles IEW is blocking +system.cpu3.iew.iewUnblockCycles 1 # Number of cycles IEW is unblocking +system.cpu3.iew.iewDispatchedInsts 112032 # Number of instructions dispatched to IQ +system.cpu3.iew.iewDispSquashedInsts 59 # Number of squashed instructions skipped by dispatch +system.cpu3.iew.iewDispLoadInsts 11889 # Number of dispatched load instructions +system.cpu3.iew.iewDispStoreInsts 1427 # Number of dispatched store instructions +system.cpu3.iew.iewDispNonSpecInsts 86 # Number of dispatched non-speculative instructions +system.cpu3.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall +system.cpu3.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall +system.cpu3.iew.memOrderViolationEvents 6 # Number of memory order violations +system.cpu3.iew.predictedTakenIncorrect 37 # Number of branches that were predicted taken incorrectly +system.cpu3.iew.predictedNotTakenIncorrect 232 # Number of branches that were predicted not taken incorrectly +system.cpu3.iew.branchMispredicts 269 # Number of branch mispredicts detected at execute +system.cpu3.iew.iewExecutedInsts 109899 # Number of executed instructions +system.cpu3.iew.iewExecLoadInsts 11799 # Number of load instructions executed +system.cpu3.iew.iewExecSquashedInsts 198 # Number of squashed instructions skipped in execute +system.cpu3.iew.exec_swp 0 # number of swp insts executed +system.cpu3.iew.exec_nop 1454 # number of nop insts executed +system.cpu3.iew.exec_refs 13117 # number of memory reference insts executed +system.cpu3.iew.exec_branches 11863 # Number of branches executed +system.cpu3.iew.exec_stores 1318 # Number of stores executed +system.cpu3.iew.exec_rate 1.775457 # Inst execution rate +system.cpu3.iew.wb_sent 109804 # cumulative count of insts sent to commit +system.cpu3.iew.wb_count 109756 # cumulative count of insts written-back +system.cpu3.iew.wb_producers 95602 # num instructions producing a value +system.cpu3.iew.wb_consumers 105897 # num instructions consuming a value +system.cpu3.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ +system.cpu3.iew.wb_rate 1.773147 # insts written-back per cycle +system.cpu3.iew.wb_fanout 0.902783 # average fanout of values written-back +system.cpu3.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ +system.cpu3.commit.commitCommittedInsts 109977 # The number of committed instructions +system.cpu3.commit.commitCommittedOps 109977 # The number of committed instructions +system.cpu3.commit.commitSquashedInsts 2026 # The number of squashed insts skipped by commit +system.cpu3.commit.commitNonSpecStalls 315 # The number of times commit has been forced to stall to communicate backwards +system.cpu3.commit.branchMispredicts 232 # The number of times a branch was mispredicted +system.cpu3.commit.committed_per_cycle::samples 41988 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::mean 2.619248 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::stdev 1.749488 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::0 7581 18.06% 18.06% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::1 2707 6.45% 24.50% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::2 10217 24.33% 48.84% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::3 10322 24.58% 73.42% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::4 72 0.17% 73.59% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::5 11026 26.26% 99.85% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::6 20 0.05% 99.90% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::7 12 0.03% 99.93% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::8 31 0.07% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle +system.cpu3.commit.committed_per_cycle::total 41988 # Number of insts commited each cycle +system.cpu3.commit.committedInsts 109977 # Number of instructions committed +system.cpu3.commit.committedOps 109977 # Number of ops (including micro ops) committed +system.cpu3.commit.swp_count 0 # Number of s/w prefetches committed +system.cpu3.commit.refs 12738 # Number of memory references committed +system.cpu3.commit.loads 11553 # Number of loads committed +system.cpu3.commit.membars 274 # Number of memory barriers committed +system.cpu3.commit.branches 11648 # Number of branches committed +system.cpu3.commit.fp_insts 0 # Number of committed floating point instructions. +system.cpu3.commit.int_insts 97103 # Number of committed integer instructions. +system.cpu3.commit.function_calls 15 # Number of function calls committed. +system.cpu3.commit.bw_lim_events 31 # number cycles where commit BW limit reached +system.cpu3.commit.bw_limited 0 # number of insts not committed due to BW limits +system.cpu3.rob.rob_reads 153633 # The number of ROB reads +system.cpu3.rob.rob_writes 224439 # The number of ROB writes +system.cpu3.timesIdled 57 # Number of times that the entire CPU went into an idle state and unscheduled itself +system.cpu3.idleCycles 740 # Total number of cycles that the CPU has spent unscheduled due to idling +system.cpu3.quiesceCycles 39396 # Total number of cycles that CPU has spent quiesced or waiting for an interrupt +system.cpu3.committedInsts 108368 # Number of Instructions Simulated +system.cpu3.committedOps 108368 # Number of Ops (including micro ops) Simulated +system.cpu3.committedInsts_total 108368 # Number of Instructions Simulated +system.cpu3.cpi 0.571193 # CPI: Cycles Per Instruction +system.cpu3.cpi_total 0.571193 # CPI: Total CPI of All Threads +system.cpu3.ipc 1.750723 # IPC: Instructions Per Cycle +system.cpu3.ipc_total 1.750723 # IPC: Total IPC of All Threads +system.cpu3.int_regfile_reads 185650 # number of integer regfile reads +system.cpu3.int_regfile_writes 108090 # number of integer regfile writes +system.cpu3.fp_regfile_writes 64 # number of floating regfile writes +system.cpu3.misc_regfile_reads 13276 # number of misc regfile reads +system.cpu3.misc_regfile_writes 58 # number of misc regfile writes +system.cpu3.icache.replacements 21 # number of replacements +system.cpu3.icache.tagsinuse 59.255579 # Cycle average of tags in use +system.cpu3.icache.total_refs 1275 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 126 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 10.119048 # Average number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.occ_blocks::cpu3.inst 59.255579 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.115734 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.115734 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 1275 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 1275 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 1275 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 1275 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 1275 # number of overall hits +system.cpu3.icache.overall_hits::total 1275 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 149 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 149 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 149 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 149 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 149 # number of overall misses +system.cpu3.icache.overall_misses::total 149 # number of overall misses +system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 2139500 # number of ReadReq miss cycles +system.cpu3.icache.ReadReq_miss_latency::total 2139500 # number of ReadReq miss cycles +system.cpu3.icache.demand_miss_latency::cpu3.inst 2139500 # number of demand (read+write) miss cycles +system.cpu3.icache.demand_miss_latency::total 2139500 # number of demand (read+write) miss cycles +system.cpu3.icache.overall_miss_latency::cpu3.inst 2139500 # number of overall miss cycles +system.cpu3.icache.overall_miss_latency::total 2139500 # number of overall miss cycles +system.cpu3.icache.ReadReq_accesses::cpu3.inst 1424 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.ReadReq_accesses::total 1424 # number of ReadReq accesses(hits+misses) +system.cpu3.icache.demand_accesses::cpu3.inst 1424 # number of demand (read+write) accesses +system.cpu3.icache.demand_accesses::total 1424 # number of demand (read+write) accesses +system.cpu3.icache.overall_accesses::cpu3.inst 1424 # number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 1424 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.104635 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.104635 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.104635 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14359.060403 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14359.060403 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14359.060403 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.icache.fast_writes 0 # number of fast writes performed +system.cpu3.icache.cache_copies 0 # number of cache copies performed +system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 23 # number of ReadReq MSHR hits +system.cpu3.icache.ReadReq_mshr_hits::total 23 # number of ReadReq MSHR hits +system.cpu3.icache.demand_mshr_hits::cpu3.inst 23 # number of demand (read+write) MSHR hits +system.cpu3.icache.demand_mshr_hits::total 23 # number of demand (read+write) MSHR hits +system.cpu3.icache.overall_mshr_hits::cpu3.inst 23 # number of overall MSHR hits +system.cpu3.icache.overall_mshr_hits::total 23 # number of overall MSHR hits +system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 126 # number of ReadReq MSHR misses +system.cpu3.icache.ReadReq_mshr_misses::total 126 # number of ReadReq MSHR misses +system.cpu3.icache.demand_mshr_misses::cpu3.inst 126 # number of demand (read+write) MSHR misses +system.cpu3.icache.demand_mshr_misses::total 126 # number of demand (read+write) MSHR misses +system.cpu3.icache.overall_mshr_misses::cpu3.inst 126 # number of overall MSHR misses +system.cpu3.icache.overall_mshr_misses::total 126 # number of overall MSHR misses +system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 1550000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_latency::total 1550000 # number of ReadReq MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 1550000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.demand_mshr_miss_latency::total 1550000 # number of demand (read+write) MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 1550000 # number of overall MSHR miss cycles +system.cpu3.icache.overall_mshr_miss_latency::total 1550000 # number of overall MSHR miss cycles +system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.088483 # mshr miss rate for ReadReq accesses +system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.088483 # mshr miss rate for demand accesses +system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.088483 # mshr miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 12301.587302 # average ReadReq mshr miss latency +system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 12301.587302 # average overall mshr miss latency +system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 12301.587302 # average overall mshr miss latency +system.cpu3.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu3.dcache.replacements 0 # number of replacements +system.cpu3.dcache.tagsinuse 19.148091 # Cycle average of tags in use +system.cpu3.dcache.total_refs 11437 # Total number of references to valid blocks. +system.cpu3.dcache.sampled_refs 31 # Sample count of references to valid blocks. +system.cpu3.dcache.avg_refs 368.935484 # Average number of references to valid blocks. +system.cpu3.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.dcache.occ_blocks::cpu3.data 19.148091 # Average occupied blocks per requestor +system.cpu3.dcache.occ_percent::cpu3.data 0.037399 # Average percentage of cache occupancy +system.cpu3.dcache.occ_percent::total 0.037399 # Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 10696 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 10696 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 1143 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 1143 # number of WriteReq hits +system.cpu3.dcache.demand_hits::cpu3.data 11839 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 11839 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 11839 # number of overall hits +system.cpu3.dcache.overall_hits::total 11839 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 43 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 43 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 40 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 40 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 2 # number of SwapReq misses +system.cpu3.dcache.SwapReq_misses::total 2 # number of SwapReq misses +system.cpu3.dcache.demand_misses::cpu3.data 83 # number of demand (read+write) misses +system.cpu3.dcache.demand_misses::total 83 # number of demand (read+write) misses +system.cpu3.dcache.overall_misses::cpu3.data 83 # number of overall misses +system.cpu3.dcache.overall_misses::total 83 # number of overall misses +system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 585000 # number of ReadReq miss cycles +system.cpu3.dcache.ReadReq_miss_latency::total 585000 # number of ReadReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 1859000 # number of WriteReq miss cycles +system.cpu3.dcache.WriteReq_miss_latency::total 1859000 # number of WriteReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 11000 # number of SwapReq miss cycles +system.cpu3.dcache.SwapReq_miss_latency::total 11000 # number of SwapReq miss cycles +system.cpu3.dcache.demand_miss_latency::cpu3.data 2444000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 2444000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 2444000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 2444000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 10739 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 10739 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 1183 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 1183 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 2 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 2 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 11922 # number of demand (read+write) accesses +system.cpu3.dcache.demand_accesses::total 11922 # number of demand (read+write) accesses +system.cpu3.dcache.overall_accesses::cpu3.data 11922 # number of overall (read+write) accesses +system.cpu3.dcache.overall_accesses::total 11922 # number of overall (read+write) accesses +system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.004004 # miss rate for ReadReq accesses +system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.033812 # miss rate for WriteReq accesses +system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 1 # miss rate for SwapReq accesses +system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006962 # miss rate for demand accesses +system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006962 # miss rate for overall accesses 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number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 16 # number of ReadReq MSHR hits +system.cpu3.dcache.ReadReq_mshr_hits::total 16 # number of ReadReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 24 # number of WriteReq MSHR hits +system.cpu3.dcache.WriteReq_mshr_hits::total 24 # number of WriteReq MSHR hits +system.cpu3.dcache.demand_mshr_hits::cpu3.data 40 # number of demand (read+write) MSHR hits +system.cpu3.dcache.demand_mshr_hits::total 40 # number of demand (read+write) MSHR hits +system.cpu3.dcache.overall_mshr_hits::cpu3.data 40 # number of overall MSHR hits +system.cpu3.dcache.overall_mshr_hits::total 40 # number of overall MSHR hits +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 27 # number of ReadReq MSHR misses +system.cpu3.dcache.ReadReq_mshr_misses::total 27 # number of ReadReq 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number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 441000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 441000 # number of ReadExReq MSHR miss cycles +system.l2c.ReadExReq_mshr_miss_latency::total 4913500 # number of ReadExReq MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.inst 16651000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu0.data 7088000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.inst 320000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu1.data 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.inst 40000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu2.data 521000 # number of demand (read+write) MSHR miss cycles +system.l2c.demand_mshr_miss_latency::cpu3.inst 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cycles +system.l2c.overall_mshr_miss_latency::total 25742000 # number of overall MSHR miss cycles +system.l2c.ReadReq_mshr_miss_rate::cpu0.inst 0.776536 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.977528 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.064000 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.117647 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.007937 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.117647 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.inst 0.015873 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.117647 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.500000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.776536 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.988764 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.064000 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.464286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.007937 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.464286 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.inst 0.015873 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.464286 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.776536 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.988764 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.064000 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.464286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.007937 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.464286 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.inst 0.015873 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.464286 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 39930.455635 # average ReadReq mshr miss latency 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latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 39930.455635 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40272.727273 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40076.923077 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40076.923077 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/config.ini @@ -0,0 +1,495 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=SparcTLB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=SparcInterrupts + +[system.cpu0.itb] +type=SparcTLB +size=64 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test___thread 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test___thread +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[3] + +[system.cpu1.dtb] +type=SparcTLB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[2] + +[system.cpu1.interrupts] +type=SparcInterrupts + +[system.cpu1.itb] +type=SparcTLB +size=64 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu2.dtb] +type=SparcTLB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu2.interrupts] +type=SparcInterrupts + +[system.cpu2.itb] +type=SparcTLB +size=64 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[7] + +[system.cpu3.dtb] +type=SparcTLB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[6] + +[system.cpu3.interrupts] +type=SparcInterrupts + +[system.cpu3.itb] +type=SparcTLB +size=64 + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.physmem.port[0] +slave=system.l2c.mem_side system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.master[0] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/simout @@ -0,0 +1,89 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 16:06:31 +gem5 started May 16 2012 20:20:05 +gem5 executing on SC2B0617 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/simple-atomic-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/simple-atomic-mp +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0: Constructing CPU with id 0 + 0: system.cpu1: Constructing CPU with id 1 + 0: system.cpu2: Constructing CPU with id 2 + 0: system.cpu3: Constructing CPU with id 3 +info: Entering event queue @ 0. Starting simulation... +132500: system.cpu0: syscall uname called w/arguments 1048640,0,2750464,8796093021226 +132500: system.cpu0: syscall uname returns 0 +219500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +219500: system.cpu0: syscall mmap returns 18446735277616529408 +1208000: system.cpu0: syscall brk called w/arguments 0,0,1385948,0 +1208000: system.cpu0: syscall brk returns 2752512 +1218500: system.cpu0: syscall brk called w/arguments 0,0,1385948,2891776 +1218500: global: Break Point changed to: 0X2C2000 +1218500: system.cpu0: syscall brk returns 2891776 +2488000: system.cpu0: syscall fstat called w/arguments 132620,8796093018288,8796093017992,1 +2488000: global: fstat(1, ...) +2488000: system.cpu0: syscall fstat returns 0 +2545500: system.cpu0: syscall mmap called w/arguments 34,3,8192,0 +2545500: system.cpu0: syscall mmap returns 18446735277616660480 +3124000: system.cpu0: syscall write called w/arguments 0,22,18446735277616660480,1 +Starting 4 threads... +3124000: system.cpu0: syscall write returns 22 +3308500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +3308500: system.cpu0: syscall mmap returns 18446735277616668672 +3325500: system.cpu0: syscall clone called w/arguments 0,12,18446735277616795649,69376 +3325500: global: In sys_clone: +3325500: global: Flags=10f00 +3325500: global: Child stack=fffff80000041001 +3325500: global: Found unallocated thread context +3325500: system.cpu0: syscall clone returns 1 +3341000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +3341000: system.cpu0: syscall mmap returns 18446735277616799744 +3358000: system.cpu0: syscall clone called w/arguments 0,12,18446735277616926721,69376 +3358000: global: In sys_clone: +3358000: global: Flags=10f00 +3358000: global: Child stack=fffff80000061001 +3358000: global: Found unallocated thread context +3358000: system.cpu0: syscall clone returns 1 +3373500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +3373500: system.cpu0: syscall mmap returns 18446735277616930816 +3390500: system.cpu0: syscall clone called w/arguments 0,12,18446735277617057793,69376 +3390500: global: In sys_clone: +3390500: global: Flags=10f00 +3390500: global: Child stack=fffff80000081001 +3390500: global: Found unallocated thread context +3390500: system.cpu0: syscall clone returns 1 +4136000: system.cpu1: syscall write called w/arguments 18446735277616668672,29,18446735277616660480,1 +&local[1]=0xfffff80000022038 +4136000: system.cpu1: syscall write returns 29 +4857000: system.cpu2: syscall write called w/arguments 18446735277616799744,29,18446735277616660480,1 +&local[2]=0xfffff80000042038 +4857000: system.cpu2: syscall write returns 29 +5578000: system.cpu3: syscall write called w/arguments 18446735277616930816,29,18446735277616660480,1 +&local[3]=0xfffff80000062038 +5578000: system.cpu3: syscall write returns 29 +6284500: system.cpu0: syscall write called w/arguments 0,29,18446735277616660480,1 +&local[0]=0xfffff80000000000 +6284500: system.cpu0: syscall write returns 29 +57782500: system.cpu1: syscall exit called w/arguments 3,132620,0,0 +57782500: system.cpu1: syscall exit returns 1 +58503500: system.cpu2: syscall exit called w/arguments 3,132620,0,0 +58503500: system.cpu2: syscall exit returns 1 +59224500: system.cpu3: syscall exit called w/arguments 3,132620,0,0 +59224500: system.cpu3: syscall exit returns 1 +60377000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[0] = 1031 +60377000: system.cpu0: syscall write returns 16 +61047000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[1] = 1032 +61047000: system.cpu0: syscall write returns 16 +61715500: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[2] = 1033 +61715500: system.cpu0: syscall write returns 16 +62384000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[3] = 1034 +62384000: system.cpu0: syscall write returns 16 +62653000: system.cpu0: syscall munmap called w/arguments 0,0,8192,18446735277616660480 +62653000: system.cpu0: syscall munmap returns 0 +62680500: system.cpu0: syscall exit_group called w/arguments 1504373,0,0,0 +62680500: system.cpu0: syscall exit_group returns 1 +Exiting @ tick 62680500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-atomic-mp/stats.txt @@ -0,0 +1,630 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000063 # Number of seconds simulated +sim_ticks 62680500 # Number of ticks simulated +final_tick 62680500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1989991 # Simulator instruction rate (inst/s) +host_op_rate 1989800 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 273442919 # Simulator tick rate (ticks/s) +host_mem_usage 1191664 # Number of bytes of host memory used +host_seconds 0.23 # Real time elapsed on the host +sim_insts 456072 # Number of instructions simulated +sim_ops 456072 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 35008 # Number of bytes read from this memory +system.physmem.bytes_inst_read 21568 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 547 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 558515009 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 344094256 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 558515009 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 26 # Number of system calls +system.cpu0.numCycles 125362 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 125277 # Number of instructions committed +system.cpu0.committedOps 125277 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109064 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 304 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 14081 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109064 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 223389 # number of times the integer registers were read +system.cpu0.num_int_register_writes 118985 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 16322 # number of memory refs +system.cpu0.num_load_insts 13928 # Number of load instructions +system.cpu0.num_store_insts 2394 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 125362 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.icache.replacements 168 # number of replacements +system.cpu0.icache.tagsinuse 210.387282 # Cycle average of tags in use +system.cpu0.icache.total_refs 124919 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 416 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 300.286058 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 210.387282 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.410913 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.410913 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 124919 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 124919 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 124919 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 124919 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 124919 # number of overall hits +system.cpu0.icache.overall_hits::total 124919 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 416 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 416 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 416 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 416 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 416 # number of overall misses +system.cpu0.icache.overall_misses::total 416 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 125335 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 125335 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 125335 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 125335 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 125335 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 125335 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.003319 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.003319 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.003319 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 5 # number of replacements +system.cpu0.dcache.tagsinuse 152.877402 # Cycle average of tags in use +system.cpu0.dcache.total_refs 14940 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 173 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 86.358382 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 152.877402 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.298589 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.298589 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 13833 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13833 # number of ReadReq hits +system.cpu0.dcache.WriteReq_hits::cpu0.data 2270 # number of WriteReq hits +system.cpu0.dcache.WriteReq_hits::total 2270 # number of WriteReq hits +system.cpu0.dcache.SwapReq_hits::cpu0.data 10 # number of SwapReq hits +system.cpu0.dcache.SwapReq_hits::total 10 # number of SwapReq hits +system.cpu0.dcache.demand_hits::cpu0.data 16103 # number of demand (read+write) hits +system.cpu0.dcache.demand_hits::total 16103 # number of demand (read+write) hits +system.cpu0.dcache.overall_hits::cpu0.data 16103 # number of overall hits +system.cpu0.dcache.overall_hits::total 16103 # number of overall hits +system.cpu0.dcache.ReadReq_misses::cpu0.data 86 # number of ReadReq misses +system.cpu0.dcache.ReadReq_misses::total 86 # number of ReadReq misses +system.cpu0.dcache.WriteReq_misses::cpu0.data 95 # number of WriteReq misses +system.cpu0.dcache.WriteReq_misses::total 95 # number of WriteReq misses +system.cpu0.dcache.SwapReq_misses::cpu0.data 9 # number of SwapReq misses +system.cpu0.dcache.SwapReq_misses::total 9 # number of SwapReq misses +system.cpu0.dcache.demand_misses::cpu0.data 181 # number of demand (read+write) misses +system.cpu0.dcache.demand_misses::total 181 # number of demand (read+write) misses +system.cpu0.dcache.overall_misses::cpu0.data 181 # number of overall misses +system.cpu0.dcache.overall_misses::total 181 # number of overall misses +system.cpu0.dcache.ReadReq_accesses::cpu0.data 13919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.ReadReq_accesses::total 13919 # number of ReadReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::cpu0.data 2365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.WriteReq_accesses::total 2365 # number of WriteReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::cpu0.data 19 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.SwapReq_accesses::total 19 # number of SwapReq accesses(hits+misses) +system.cpu0.dcache.demand_accesses::cpu0.data 16284 # number of demand (read+write) accesses +system.cpu0.dcache.demand_accesses::total 16284 # number of demand (read+write) accesses +system.cpu0.dcache.overall_accesses::cpu0.data 16284 # number of overall (read+write) accesses +system.cpu0.dcache.overall_accesses::total 16284 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006179 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.040169 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.473684 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.011115 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.011115 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.writebacks::writebacks 3 # number of writebacks +system.cpu0.dcache.writebacks::total 3 # number of writebacks +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 115565 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed 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12475 # number of memory refs +system.cpu1.num_load_insts 11289 # Number of load instructions +system.cpu1.num_store_insts 1186 # Number of store instructions +system.cpu1.num_idle_cycles 15161.794783 # Number of idle cycles +system.cpu1.num_busy_cycles 100403.205217 # Number of busy cycles +system.cpu1.not_idle_fraction 0.868803 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.131197 # Percentage of idle cycles +system.cpu1.icache.replacements 13 # number of replacements +system.cpu1.icache.tagsinuse 71.606728 # Cycle average of tags in use +system.cpu1.icache.total_refs 108810 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 90 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 1209 # Average number of references to valid blocks. +system.cpu1.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.icache.occ_blocks::cpu1.inst 71.606728 # Average occupied blocks per requestor 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0.014370 # miss rate for WriteReq accesses +system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 1 # miss rate for SwapReq accesses +system.cpu1.dcache.demand_miss_rate::cpu1.data 0.002968 # miss rate for demand accesses +system.cpu1.dcache.overall_miss_rate::cpu1.data 0.002968 # miss rate for overall accesses +system.cpu1.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.dcache.fast_writes 0 # number of fast writes performed +system.cpu1.dcache.cache_copies 0 # number of cache copies performed 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references to valid blocks. +system.cpu2.icache.avg_refs 1210.835165 # Average number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.icache.occ_blocks::cpu2.inst 72.773327 # Average occupied blocks per requestor +system.cpu2.icache.occ_percent::cpu2.inst 0.142135 # Average percentage of cache occupancy +system.cpu2.icache.occ_percent::total 0.142135 # Average percentage of cache occupancy +system.cpu2.icache.ReadReq_hits::cpu2.inst 110186 # number of ReadReq hits +system.cpu2.icache.ReadReq_hits::total 110186 # number of ReadReq hits +system.cpu2.icache.demand_hits::cpu2.inst 110186 # number of demand (read+write) hits +system.cpu2.icache.demand_hits::total 110186 # number of demand (read+write) hits +system.cpu2.icache.overall_hits::cpu2.inst 110186 # number of overall hits +system.cpu2.icache.overall_hits::total 110186 # number of overall hits +system.cpu2.icache.ReadReq_misses::cpu2.inst 91 # number of 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# Number of misses that were no-allocate +system.cpu2.dcache.replacements 0 # number of replacements +system.cpu2.dcache.tagsinuse 29.070389 # Cycle average of tags in use +system.cpu2.dcache.total_refs 12336 # Total number of references to valid blocks. +system.cpu2.dcache.sampled_refs 29 # Sample count of references to valid blocks. +system.cpu2.dcache.avg_refs 425.379310 # Average number of references to valid blocks. +system.cpu2.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu2.dcache.occ_blocks::cpu2.data 29.070389 # Average occupied blocks per requestor +system.cpu2.dcache.occ_percent::cpu2.data 0.056778 # Average percentage of cache occupancy +system.cpu2.dcache.occ_percent::total 0.056778 # Average percentage of cache occupancy +system.cpu2.dcache.ReadReq_hits::cpu2.data 11601 # number of ReadReq hits +system.cpu2.dcache.ReadReq_hits::total 11601 # number of ReadReq hits +system.cpu2.dcache.WriteReq_hits::cpu2.data 1166 # number of WriteReq hits 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are conditional controls +system.cpu3.num_int_insts 97947 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 198398 # number of times the integer registers were read +system.cpu3.num_int_register_writes 107382 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 13163 # number of memory refs +system.cpu3.num_load_insts 11975 # Number of load instructions +system.cpu3.num_store_insts 1188 # Number of store instructions +system.cpu3.num_idle_cycles 12938.013960 # Number of idle cycles +system.cpu3.num_busy_cycles 105510.986040 # Number of busy cycles +system.cpu3.not_idle_fraction 0.890771 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.109229 # Percentage of idle cycles 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the warmup percentage was hit. +system.l2c.occ_blocks::writebacks 1.893819 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.inst 265.380247 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu0.data 60.735652 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.inst 15.070261 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu1.data 3.772665 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.inst 1.888370 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu2.data 0.945653 # Average occupied blocks per requestor +system.l2c.occ_blocks::cpu3.data 0.945134 # Average occupied blocks per requestor +system.l2c.occ_percent::writebacks 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.inst 0.004049 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu0.data 0.000927 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.inst 0.000230 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu1.data 0.000058 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.inst 0.000029 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu2.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::cpu3.data 0.000014 # Average percentage of cache occupancy +system.l2c.occ_percent::total 0.005350 # Average percentage of cache occupancy +system.l2c.ReadReq_hits::cpu0.inst 98 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu0.data 5 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.inst 73 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu1.data 10 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.inst 89 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu2.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.inst 91 # number of ReadReq hits +system.l2c.ReadReq_hits::cpu3.data 13 # number of ReadReq hits +system.l2c.ReadReq_hits::total 392 # number of ReadReq hits +system.l2c.Writeback_hits::writebacks 3 # number of Writeback hits +system.l2c.Writeback_hits::total 3 # number of Writeback hits +system.l2c.UpgradeReq_hits::cpu0.data 2 # number of UpgradeReq hits +system.l2c.UpgradeReq_hits::total 2 # number of UpgradeReq hits +system.l2c.demand_hits::cpu0.inst 98 # number of demand (read+write) hits +system.l2c.demand_hits::cpu0.data 5 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.inst 73 # number of demand (read+write) hits +system.l2c.demand_hits::cpu1.data 10 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.inst 89 # number of demand (read+write) hits +system.l2c.demand_hits::cpu2.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.inst 91 # number of demand (read+write) hits +system.l2c.demand_hits::cpu3.data 13 # number of demand (read+write) hits +system.l2c.demand_hits::total 392 # number of demand (read+write) hits +system.l2c.overall_hits::cpu0.inst 98 # number of overall hits +system.l2c.overall_hits::cpu0.data 5 # number of overall hits +system.l2c.overall_hits::cpu1.inst 73 # number of overall hits +system.l2c.overall_hits::cpu1.data 10 # number of overall hits +system.l2c.overall_hits::cpu2.inst 89 # number of overall hits +system.l2c.overall_hits::cpu2.data 13 # number of overall hits +system.l2c.overall_hits::cpu3.inst 91 # number of overall hits +system.l2c.overall_hits::cpu3.data 13 # number of overall hits +system.l2c.overall_hits::total 392 # number of overall hits +system.l2c.ReadReq_misses::cpu0.inst 318 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu0.data 73 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.inst 17 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu1.data 4 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.inst 2 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu2.data 1 # number of ReadReq misses +system.l2c.ReadReq_misses::cpu3.data 1 # number of ReadReq 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91 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu2.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.inst 91 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::cpu3.data 14 # number of ReadReq accesses(hits+misses) +system.l2c.ReadReq_accesses::total 808 # number of ReadReq accesses(hits+misses) +system.l2c.Writeback_accesses::writebacks 3 # number of Writeback accesses(hits+misses) +system.l2c.Writeback_accesses::total 3 # number of Writeback accesses(hits+misses) +system.l2c.UpgradeReq_accesses::cpu0.data 2 # number of UpgradeReq accesses(hits+misses) +system.l2c.UpgradeReq_accesses::total 2 # number of UpgradeReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu0.data 95 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu1.data 12 # number of ReadExReq accesses(hits+misses) +system.l2c.ReadExReq_accesses::cpu2.data 12 # number of ReadExReq accesses(hits+misses) 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accesses +system.l2c.overall_accesses::cpu0.data 173 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.inst 90 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu1.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.inst 91 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu2.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.inst 91 # number of overall (read+write) accesses +system.l2c.overall_accesses::cpu3.data 26 # number of overall (read+write) accesses +system.l2c.overall_accesses::total 939 # number of overall (read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.764423 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.935897 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.188889 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.285714 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.inst 0.021978 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.071429 # miss rate for ReadReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.764423 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.971098 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.188889 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.615385 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.inst 0.021978 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.500000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.500000 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.764423 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.971098 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.188889 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.615385 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.inst 0.021978 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.500000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.500000 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/config.ini @@ -0,0 +1,206 @@ +[root] +type=Root +children=system +dummy=0 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 membus physmem +mem_mode=timing +physmem=system.physmem + +[system.cpu0] +type=TimingSimpleCPU +children=dtb itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.membus.port[1] +icache_port=system.membus.port[0] + +[system.cpu0.dtb] +type=SparcTLB +size=64 + +[system.cpu0.itb] +type=SparcTLB +size=64 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/dist/m5/regression/test-progs/m5threads/bin/sparc/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dtb itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.membus.port[3] +icache_port=system.membus.port[2] + +[system.cpu1.dtb] +type=SparcTLB +size=64 + +[system.cpu1.itb] +type=SparcTLB +size=64 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dtb itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.membus.port[5] +icache_port=system.membus.port[4] + +[system.cpu2.dtb] +type=SparcTLB +size=64 + +[system.cpu2.itb] +type=SparcTLB +size=64 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dtb itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.membus.port[7] +icache_port=system.membus.port[6] + +[system.cpu3.dtb] +type=SparcTLB +size=64 + +[system.cpu3.itb] +type=SparcTLB +size=64 + +[system.cpu3.tracer] +type=ExeTracer + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +port=system.cpu0.icache_port system.cpu0.dcache_port system.cpu1.icache_port system.cpu1.dcache_port system.cpu2.icache_port system.cpu2.dcache_port system.cpu3.icache_port system.cpu3.dcache_port system.physmem.port[0] + +[system.physmem] +type=RubyMemory +clock=1 +config_file= +config_options= +debug=false +debug_file= +file= +latency=30000 +latency_var=0 +null=false +num_cpus=4 +phase=0 +range=0:134217727 +stats_file=ruby.stats +zero=false +port=system.membus.port[8] + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/ruby.stats @@ -0,0 +1,1004 @@ + +================ Begin RubySystem Configuration Print ================ + +Ruby Configuration +------------------ +protocol: MOSI_SMP_bcast +compiled_at: 22:54:24, May 4 2009 +RUBY_DEBUG: false +hostname: piton +g_RANDOM_SEED: 1 +g_DEADLOCK_THRESHOLD: 500000 +RANDOMIZATION: false +g_SYNTHETIC_DRIVER: false +g_DETERMINISTIC_DRIVER: false +g_FILTERING_ENABLED: false +g_DISTRIBUTED_PERSISTENT_ENABLED: true +g_DYNAMIC_TIMEOUT_ENABLED: true +g_RETRY_THRESHOLD: 1 +g_FIXED_TIMEOUT_LATENCY: 300 +g_trace_warmup_length: 1000000 +g_bash_bandwidth_adaptive_threshold: 0.75 +g_tester_length: 0 +g_synthetic_locks: 2048 +g_deterministic_addrs: 1 +g_SpecifiedGenerator: DetermInvGenerator +g_callback_counter: 0 +g_NUM_COMPLETIONS_BEFORE_PASS: 0 +g_NUM_SMT_THREADS: 1 +g_think_time: 5 +g_hold_time: 5 +g_wait_time: 5 +PROTOCOL_DEBUG_TRACE: true +DEBUG_FILTER_STRING: none +DEBUG_VERBOSITY_STRING: none +DEBUG_START_TIME: 0 +DEBUG_OUTPUT_FILENAME: none +SIMICS_RUBY_MULTIPLIER: 4 +OPAL_RUBY_MULTIPLIER: 1 +TRANSACTION_TRACE_ENABLED: false +USER_MODE_DATA_ONLY: false +PROFILE_HOT_LINES: false +PROFILE_ALL_INSTRUCTIONS: false +PRINT_INSTRUCTION_TRACE: false +g_DEBUG_CYCLE: 0 +BLOCK_STC: false +PERFECT_MEMORY_SYSTEM: false +PERFECT_MEMORY_SYSTEM_LATENCY: 0 +DATA_BLOCK: false +REMOVE_SINGLE_CYCLE_DCACHE_FAST_PATH: false +L1_CACHE_ASSOC: 4 +L1_CACHE_NUM_SETS_BITS: 8 +L2_CACHE_ASSOC: 4 +L2_CACHE_NUM_SETS_BITS: 16 +g_MEMORY_SIZE_BYTES: 4294967296 +g_DATA_BLOCK_BYTES: 64 +g_PAGE_SIZE_BYTES: 4096 +g_REPLACEMENT_POLICY: PSEDUO_LRU +g_NUM_PROCESSORS: 4 +g_NUM_L2_BANKS: 4 +g_NUM_MEMORIES: 4 +g_PROCS_PER_CHIP: 1 +g_NUM_CHIPS: 4 +g_NUM_CHIP_BITS: 2 +g_MEMORY_SIZE_BITS: 32 +g_DATA_BLOCK_BITS: 6 +g_PAGE_SIZE_BITS: 12 +g_NUM_PROCESSORS_BITS: 2 +g_PROCS_PER_CHIP_BITS: 0 +g_NUM_L2_BANKS_BITS: 2 +g_NUM_L2_BANKS_PER_CHIP_BITS: 0 +g_NUM_L2_BANKS_PER_CHIP: 1 +g_NUM_MEMORIES_BITS: 2 +g_NUM_MEMORIES_PER_CHIP: 1 +g_MEMORY_MODULE_BITS: 24 +g_MEMORY_MODULE_BLOCKS: 16777216 +MAP_L2BANKS_TO_LOWEST_BITS: false +DIRECTORY_CACHE_LATENCY: 6 +NULL_LATENCY: 1 +ISSUE_LATENCY: 2 +CACHE_RESPONSE_LATENCY: 12 +L2_RESPONSE_LATENCY: 6 +L2_TAG_LATENCY: 6 +L1_RESPONSE_LATENCY: 3 +MEMORY_RESPONSE_LATENCY_MINUS_2: 158 +DIRECTORY_LATENCY: 80 +NETWORK_LINK_LATENCY: 1 +COPY_HEAD_LATENCY: 4 +ON_CHIP_LINK_LATENCY: 1 +RECYCLE_LATENCY: 10 +L2_RECYCLE_LATENCY: 5 +TIMER_LATENCY: 10000 +TBE_RESPONSE_LATENCY: 1 +PERIODIC_TIMER_WAKEUPS: true +PROFILE_EXCEPTIONS: false +PROFILE_XACT: true +PROFILE_NONXACT: false +XACT_DEBUG: true +XACT_DEBUG_LEVEL: 1 +XACT_MEMORY: false +XACT_ENABLE_TOURMALINE: false +XACT_NUM_CURRENT: 0 +XACT_LAST_UPDATE: 0 +XACT_ISOLATION_CHECK: false +PERFECT_FILTER: true +READ_WRITE_FILTER: Perfect_ +PERFECT_VIRTUAL_FILTER: true +VIRTUAL_READ_WRITE_FILTER: Perfect_ +PERFECT_SUMMARY_FILTER: true +SUMMARY_READ_WRITE_FILTER: Perfect_ +XACT_EAGER_CD: true +XACT_LAZY_VM: false +XACT_CONFLICT_RES: BASE +XACT_VISUALIZER: false +XACT_COMMIT_TOKEN_LATENCY: 0 +XACT_NO_BACKOFF: false +XACT_LOG_BUFFER_SIZE: 0 +XACT_STORE_PREDICTOR_HISTORY: 256 +XACT_STORE_PREDICTOR_ENTRIES: 256 +XACT_STORE_PREDICTOR_THRESHOLD: 4 +XACT_FIRST_ACCESS_COST: 0 +XACT_FIRST_PAGE_ACCESS_COST: 0 +ENABLE_MAGIC_WAITING: false +ENABLE_WATCHPOINT: false +XACT_ENABLE_VIRTUALIZATION_LOGTM_SE: false +ATMTP_ENABLED: false +ATMTP_ABORT_ON_NON_XACT_INST: false +ATMTP_ALLOW_SAVE_RESTORE_IN_XACT: false +ATMTP_XACT_MAX_STORES: 32 +ATMTP_DEBUG_LEVEL: 0 +L1_REQUEST_LATENCY: 2 +L2_REQUEST_LATENCY: 4 +SINGLE_ACCESS_L2_BANKS: true +SEQUENCER_TO_CONTROLLER_LATENCY: 4 +L1CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 +L2CACHE_TRANSITIONS_PER_RUBY_CYCLE: 32 +DIRECTORY_TRANSITIONS_PER_RUBY_CYCLE: 32 +g_SEQUENCER_OUTSTANDING_REQUESTS: 16 +NUMBER_OF_TBES: 128 +NUMBER_OF_L1_TBES: 32 +NUMBER_OF_L2_TBES: 32 +FINITE_BUFFERING: false +FINITE_BUFFER_SIZE: 3 +PROCESSOR_BUFFER_SIZE: 10 +PROTOCOL_BUFFER_SIZE: 32 +TSO: false +g_NETWORK_TOPOLOGY: HIERARCHICAL_SWITCH +g_CACHE_DESIGN: NUCA +g_endpoint_bandwidth: 10000 +g_adaptive_routing: true +NUMBER_OF_VIRTUAL_NETWORKS: 4 +FAN_OUT_DEGREE: 4 +g_PRINT_TOPOLOGY: true +XACT_LENGTH: 0 +XACT_SIZE: 0 +ABORT_RETRY_TIME: 0 +g_GARNET_NETWORK: false +g_DETAIL_NETWORK: false +g_NETWORK_TESTING: false +g_FLIT_SIZE: 16 +g_NUM_PIPE_STAGES: 4 +g_VCS_PER_CLASS: 4 +g_BUFFER_SIZE: 4 +MEM_BUS_CYCLE_MULTIPLIER: 10 +BANKS_PER_RANK: 8 +RANKS_PER_DIMM: 2 +DIMMS_PER_CHANNEL: 2 +BANK_BIT_0: 8 +RANK_BIT_0: 11 +DIMM_BIT_0: 12 +BANK_QUEUE_SIZE: 12 +BANK_BUSY_TIME: 11 +RANK_RANK_DELAY: 1 +READ_WRITE_DELAY: 2 +BASIC_BUS_BUSY_TIME: 2 +MEM_CTL_LATENCY: 12 +REFRESH_PERIOD: 1560 +TFAW: 0 +MEM_RANDOM_ARBITRATE: 0 +MEM_FIXED_DELAY: 0 + +Chip Config +----------- +Total_Chips: 4 + +L1Cache_TBEs numberPerChip: 1 +TBEs_per_TBETable: 128 + +L1Cache_L1IcacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L1I + cache_associativity: 4 + num_cache_sets_bits: 8 + num_cache_sets: 256 + cache_set_size_bytes: 16384 + cache_set_size_Kbytes: 16 + cache_set_size_Mbytes: 0.015625 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 + +L1Cache_L1DcacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L1D + cache_associativity: 4 + num_cache_sets_bits: 8 + num_cache_sets: 256 + cache_set_size_bytes: 16384 + cache_set_size_Kbytes: 16 + cache_set_size_Mbytes: 0.015625 + cache_size_bytes: 65536 + cache_size_Kbytes: 64 + cache_size_Mbytes: 0.0625 + +L1Cache_L2cacheMemory numberPerChip: 1 +Cache config: L1Cache_0_L2 + cache_associativity: 4 + num_cache_sets_bits: 16 + num_cache_sets: 65536 + cache_set_size_bytes: 4194304 + cache_set_size_Kbytes: 4096 + cache_set_size_Mbytes: 4 + cache_size_bytes: 16777216 + cache_size_Kbytes: 16384 + cache_size_Mbytes: 16 + +L1Cache_mandatoryQueue numberPerChip: 1 + +L1Cache_sequencer numberPerChip: 1 +sequencer: Sequencer - SC + max_outstanding_requests: 16 + +L1Cache_storeBuffer numberPerChip: 1 +Store buffer entries: 128 (Only valid if TSO is enabled) + +Directory_directory numberPerChip: 1 +Memory config: + memory_bits: 32 + memory_size_bytes: 4294967296 + memory_size_Kbytes: 4.1943e+06 + memory_size_Mbytes: 4096 + memory_size_Gbytes: 4 + module_bits: 24 + module_size_lines: 16777216 + module_size_bytes: 1073741824 + module_size_Kbytes: 1.04858e+06 + module_size_Mbytes: 1024 + + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: HIERARCHICAL_SWITCH + +virtual_net_0: active, ordered +virtual_net_1: active, unordered +virtual_net_2: inactive +virtual_net_3: inactive + +--- Begin Topology Print --- + +Topology print ONLY indicates the _NETWORK_ latency between two machines +It does NOT include the latency within the machines + +L1Cache-0 Network Latencies + L1Cache-0 -> L1Cache-1 net_lat: 9 + L1Cache-0 -> L1Cache-2 net_lat: 9 + L1Cache-0 -> L1Cache-3 net_lat: 9 + L1Cache-0 -> Directory-0 net_lat: 9 + L1Cache-0 -> Directory-1 net_lat: 9 + L1Cache-0 -> Directory-2 net_lat: 9 + L1Cache-0 -> Directory-3 net_lat: 9 + +L1Cache-1 Network Latencies + L1Cache-1 -> L1Cache-0 net_lat: 9 + L1Cache-1 -> L1Cache-2 net_lat: 9 + L1Cache-1 -> L1Cache-3 net_lat: 9 + L1Cache-1 -> Directory-0 net_lat: 9 + L1Cache-1 -> Directory-1 net_lat: 9 + L1Cache-1 -> Directory-2 net_lat: 9 + L1Cache-1 -> Directory-3 net_lat: 9 + +L1Cache-2 Network Latencies + L1Cache-2 -> L1Cache-0 net_lat: 9 + L1Cache-2 -> L1Cache-1 net_lat: 9 + L1Cache-2 -> L1Cache-3 net_lat: 9 + L1Cache-2 -> Directory-0 net_lat: 9 + L1Cache-2 -> Directory-1 net_lat: 9 + L1Cache-2 -> Directory-2 net_lat: 9 + L1Cache-2 -> Directory-3 net_lat: 9 + +L1Cache-3 Network Latencies + L1Cache-3 -> L1Cache-0 net_lat: 9 + L1Cache-3 -> L1Cache-1 net_lat: 9 + L1Cache-3 -> L1Cache-2 net_lat: 9 + L1Cache-3 -> Directory-0 net_lat: 9 + L1Cache-3 -> Directory-1 net_lat: 9 + L1Cache-3 -> Directory-2 net_lat: 9 + L1Cache-3 -> Directory-3 net_lat: 9 + +Directory-0 Network Latencies + Directory-0 -> L1Cache-0 net_lat: 9 + Directory-0 -> L1Cache-1 net_lat: 9 + Directory-0 -> L1Cache-2 net_lat: 9 + Directory-0 -> L1Cache-3 net_lat: 9 + Directory-0 -> Directory-1 net_lat: 9 + Directory-0 -> Directory-2 net_lat: 9 + Directory-0 -> Directory-3 net_lat: 9 + +Directory-1 Network Latencies + Directory-1 -> L1Cache-0 net_lat: 9 + Directory-1 -> L1Cache-1 net_lat: 9 + Directory-1 -> L1Cache-2 net_lat: 9 + Directory-1 -> L1Cache-3 net_lat: 9 + Directory-1 -> Directory-0 net_lat: 9 + Directory-1 -> Directory-2 net_lat: 9 + Directory-1 -> Directory-3 net_lat: 9 + +Directory-2 Network Latencies + Directory-2 -> L1Cache-0 net_lat: 9 + Directory-2 -> L1Cache-1 net_lat: 9 + Directory-2 -> L1Cache-2 net_lat: 9 + Directory-2 -> L1Cache-3 net_lat: 9 + Directory-2 -> Directory-0 net_lat: 9 + Directory-2 -> Directory-1 net_lat: 9 + Directory-2 -> Directory-3 net_lat: 9 + +Directory-3 Network Latencies + Directory-3 -> L1Cache-0 net_lat: 9 + Directory-3 -> L1Cache-1 net_lat: 9 + Directory-3 -> L1Cache-2 net_lat: 9 + Directory-3 -> L1Cache-3 net_lat: 9 + Directory-3 -> Directory-0 net_lat: 9 + Directory-3 -> Directory-1 net_lat: 9 + Directory-3 -> Directory-2 net_lat: 9 + +--- End Topology Print --- + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: May/05/2009 07:34:42 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 40 +Elapsed_time_in_minutes: 0.666667 +Elapsed_time_in_hours: 0.0111111 +Elapsed_time_in_days: 0.000462963 + +Virtual_time_in_seconds: 37.33 +Virtual_time_in_minutes: 0.622167 +Virtual_time_in_hours: 0.0103694 +Virtual_time_in_days: 0.0103694 + +Ruby_current_time: 2480212001 +Ruby_start_time: 1 +Ruby_cycles: 2480212000 + +mbytes_resident: 90.6484 +mbytes_total: 252.043 +resident_ratio: 0.35967 + +Total_misses: 1949 +total_misses: 1949 [ 424 409 702 414 ] +user_misses: 1949 [ 424 409 702 414 ] +supervisor_misses: 0 [ 0 0 0 0 ] + +instruction_executed: 4 [ 1 1 1 1 ] +cycles_executed: 4 [ 1 1 1 1 ] +cycles_per_instruction: 2.48021e+09 [ 2.48021e+09 2.48021e+09 2.48021e+09 2.48021e+09 ] +misses_per_thousand_instructions: 487250 [ 424000 409000 702000 414000 ] + +transactions_started: 0 [ 0 0 0 0 ] +transactions_ended: 0 [ 0 0 0 0 ] +instructions_per_transaction: 0 [ 0 0 0 0 ] +cycles_per_transaction: 0 [ 0 0 0 0 ] +misses_per_transaction: 0 [ 0 0 0 0 ] + +L1D_cache cache stats: + L1D_cache_total_misses: 1340 + L1D_cache_total_demand_misses: 1340 + L1D_cache_total_prefetches: 0 + L1D_cache_total_sw_prefetches: 0 + L1D_cache_total_hw_prefetches: 0 + L1D_cache_misses_per_transaction: 1340 + L1D_cache_misses_per_instruction: 1340 + L1D_cache_instructions_per_misses: 0.000746269 + + L1D_cache_request_type_LD: 47.4627% + L1D_cache_request_type_ST: 38.0597% + L1D_cache_request_type_ATOMIC: 14.4776% + + L1D_cache_access_mode_type_UserMode: 1340 100% + L1D_cache_request_size: [binsize: log2 max: 8 count: 1340 average: 3.48881 | standard deviation: 2.44812 | 0 527 4 583 226 ] + +L1I_cache cache stats: + L1I_cache_total_misses: 610 + L1I_cache_total_demand_misses: 610 + L1I_cache_total_prefetches: 0 + L1I_cache_total_sw_prefetches: 0 + L1I_cache_total_hw_prefetches: 0 + L1I_cache_misses_per_transaction: 610 + L1I_cache_misses_per_instruction: 610 + L1I_cache_instructions_per_misses: 0.00163934 + + L1I_cache_request_type_IFETCH: 100% + + L1I_cache_access_mode_type_UserMode: 610 100% + L1I_cache_request_size: [binsize: log2 max: 4 count: 610 average: 4 | standard deviation: 0 | 0 0 0 610 ] + +L2_cache cache stats: + L2_cache_total_misses: 1949 + L2_cache_total_demand_misses: 1949 + L2_cache_total_prefetches: 0 + L2_cache_total_sw_prefetches: 0 + L2_cache_total_hw_prefetches: 0 + L2_cache_misses_per_transaction: 1949 + L2_cache_misses_per_instruction: 1949 + L2_cache_instructions_per_misses: 0.000513084 + + L2_cache_request_type_LD: 32.6321% + L2_cache_request_type_ST: 26.1673% + L2_cache_request_type_ATOMIC: 9.95382% + L2_cache_request_type_IFETCH: 31.2468% + + L2_cache_access_mode_type_UserMode: 1949 100% + L2_cache_request_size: [binsize: log2 max: 8 count: 1949 average: 3.64854 | standard deviation: 2.04355 | 0 527 4 1192 226 ] + + +Busy Controller Counts: +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 +Directory-0:0 Directory-1:0 Directory-2:0 Directory-3:0 + +Busy Bank Count:0 + +L1TBE_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +L2TBE_usage: [binsize: 1 max: 0 count: 1949 average: 0 | standard deviation: 0 | 1949 ] +StopTable_usage: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1950 average: 1 | standard deviation: 0 | 0 1950 ] +store_buffer_size: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +unique_blocks_in_store_buffer: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ] +miss_latency_LD: [binsize: 1 max: 184 count: 636 average: 57.2925 | standard deviation: 53.9711 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 536 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 15 19 26 17 23 ] +miss_latency_ST: [binsize: 1 max: 184 count: 510 average: 73.749 | standard deviation: 69.6824 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 280 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 34 27 26 19 42 ] +miss_latency_ATOMIC: [binsize: 1 max: 183 count: 194 average: 37.7887 | standard deviation: 23.3543 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 189 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 2 0 1 ] +miss_latency_IFETCH: [binsize: 1 max: 184 count: 610 average: 181.728 | standard deviation: 7.34165 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 113 125 131 117 123 ] +miss_latency_NULL: [binsize: 1 max: 184 count: 1950 average: 98.5821 | standard deviation: 74.4128 | 0 0 0 0 1 0 0 0 0 0 0 0 0 0 82 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1005 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 164 173 183 154 188 ] +miss_latency_L2Miss: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +multicast_retries: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +gets_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +getx_mask_prediction_count: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +explicit_training_mask: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +conflicting_histogram: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 6 7 6 10 37 57 33 164 243 38 123 210 142 218 449 203 ] +conflicting_histogram_percent: [binsize: log2 max: 2480202004 count: 1949 average: 7.71124e+08 | standard deviation: nan | 0 0 0 0.0513084 0 0 0 0 0 0 0 0 0 0 0.0513084 0 0.0513084 0.30785 0.359159 0.30785 0.513084 1.89841 2.92458 1.69318 8.41457 12.4679 1.94972 6.31093 10.7748 7.28579 11.1852 23.0375 10.4156 ] + +Request vs. RubySystem State Profile +-------------------------------- + + I M GETS 310 15.9056 + I M GETX 216 11.0826 + I OS GETS 142 7.28579 + I OS GETX 33 1.69318 + I OSS GETS 54 2.77065 + I OSS GETX 15 0.769625 + NP C GETS 75 3.84813 + NP C GETX 136 6.97794 + NP C GET_INSTR 348 17.8553 + NP M GETS 17 0.872242 + NP M GETX 11 0.564392 + NP OS GETS 6 0.30785 + NP OSS GETS 7 0.359159 + NP S GETS 9 0.461775 + NP S GET_INSTR 93 4.77168 + NP SS GETS 16 0.820934 + NP SS GET_INSTR 168 8.61981 + O OS GETX 22 1.12878 + O OSS GETX 60 3.0785 + S OS GETX 124 6.36224 + S OSS GETX 70 3.59159 + S S GETX 17 0.872242 + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 37 +system_time: 0 +page_reclaims: 23404 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 656 +MessageBuffer: [Chip 0 0, L1Cache, mandatoryQueue_in] stats - msgs:424 full:0 +MessageBuffer: [Chip 1 0, L1Cache, mandatoryQueue_in] stats - msgs:409 full:0 +MessageBuffer: [Chip 2 0, L1Cache, mandatoryQueue_in] stats - msgs:703 full:0 +MessageBuffer: [Chip 3 0, L1Cache, mandatoryQueue_in] stats - msgs:414 full:0 + +Network Stats +------------- + +switch_0_inlinks: 1 +switch_0_outlinks: 1 +links_utilized_percent_switch_0: 8.82828e-05 + links_utilized_percent_switch_0_link_0: 8.82828e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Control: 424 3392 [ 424 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Data: 257 18504 [ 0 257 0 0 ] base_latency: 1 + +switch_1_inlinks: 1 +switch_1_outlinks: 1 +links_utilized_percent_switch_1: 8.92504e-05 + links_utilized_percent_switch_1_link_0: 8.92504e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Control: 409 3272 [ 409 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Data: 262 18864 [ 0 262 0 0 ] base_latency: 1 + +switch_2_inlinks: 1 +switch_2_outlinks: 1 +links_utilized_percent_switch_2: 8.94117e-05 + links_utilized_percent_switch_2_link_0: 8.94117e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Control: 702 5616 [ 702 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Data: 230 16560 [ 0 230 0 0 ] base_latency: 1 + +switch_3_inlinks: 1 +switch_3_outlinks: 1 +links_utilized_percent_switch_3: 8.76699e-05 + links_utilized_percent_switch_3_link_0: 8.76699e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Control: 414 3312 [ 414 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Data: 256 18432 [ 0 256 0 0 ] base_latency: 1 + +switch_4_inlinks: 1 +switch_4_outlinks: 1 +links_utilized_percent_switch_4: 6.76394e-05 + links_utilized_percent_switch_4_link_0: 6.76394e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Data: 233 16776 [ 0 233 0 0 ] base_latency: 1 + +switch_5_inlinks: 1 +switch_5_outlinks: 1 +links_utilized_percent_switch_5: 6.21237e-05 + links_utilized_percent_switch_5_link_0: 6.21237e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Data: 214 15408 [ 0 214 0 0 ] base_latency: 1 + +switch_6_inlinks: 1 +switch_6_outlinks: 1 +links_utilized_percent_switch_6: 5.9511e-05 + links_utilized_percent_switch_6_link_0: 5.9511e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_6_link_0_Data: 205 14760 [ 0 205 0 0 ] base_latency: 1 + +switch_7_inlinks: 1 +switch_7_outlinks: 1 +links_utilized_percent_switch_7: 6.09625e-05 + links_utilized_percent_switch_7_link_0: 6.09625e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_7_link_0_Data: 210 15120 [ 0 210 0 0 ] base_latency: 1 + +switch_8_inlinks: 4 +switch_8_outlinks: 1 +links_utilized_percent_switch_8: 0.000354615 + links_utilized_percent_switch_8_link_0: 0.000354615 bw: 10000 base_latency: 1 + + outgoing_messages_switch_8_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_8_link_0_Data: 1005 72360 [ 0 1005 0 0 ] base_latency: 1 + +switch_9_inlinks: 4 +switch_9_outlinks: 1 +links_utilized_percent_switch_9: 0.000250237 + links_utilized_percent_switch_9_link_0: 0.000250237 bw: 10000 base_latency: 1 + + outgoing_messages_switch_9_link_0_Data: 862 62064 [ 0 862 0 0 ] base_latency: 1 + +switch_10_inlinks: 2 +switch_10_outlinks: 2 +links_utilized_percent_switch_10: 0.000333859 + links_utilized_percent_switch_10_link_0: 0.000604852 bw: 10000 base_latency: 1 + links_utilized_percent_switch_10_link_1: 6.28656e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_10_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_0_Data: 1867 134424 [ 0 1867 0 0 ] base_latency: 1 + outgoing_messages_switch_10_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + +switch_11_inlinks: 1 +switch_11_outlinks: 4 +links_utilized_percent_switch_11: 0.000198362 + links_utilized_percent_switch_11_link_0: 0.000181597 bw: 10000 base_latency: 1 + links_utilized_percent_switch_11_link_1: 0.000176082 bw: 10000 base_latency: 1 + links_utilized_percent_switch_11_link_2: 0.000257655 bw: 10000 base_latency: 1 + links_utilized_percent_switch_11_link_3: 0.000178114 bw: 10000 base_latency: 1 + + outgoing_messages_switch_11_link_0_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_0_Data: 409 29448 [ 0 409 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_1_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_1_Data: 390 28080 [ 0 390 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_2_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_2_Data: 671 48312 [ 0 671 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_3_Control: 1949 15592 [ 1949 0 0 0 ] base_latency: 1 + outgoing_messages_switch_11_link_3_Data: 397 28584 [ 0 397 0 0 ] base_latency: 1 + +switch_12_inlinks: 1 +switch_12_outlinks: 4 +links_utilized_percent_switch_12: 1.57164e-05 + links_utilized_percent_switch_12_link_0: 2.37399e-05 bw: 10000 base_latency: 1 + links_utilized_percent_switch_12_link_1: 1.05475e-05 bw: 10000 base_latency: 1 + links_utilized_percent_switch_12_link_2: 6.87038e-06 bw: 10000 base_latency: 1 + links_utilized_percent_switch_12_link_3: 2.17078e-05 bw: 10000 base_latency: 1 + + outgoing_messages_switch_12_link_0_Control: 736 5888 [ 736 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_1_Control: 327 2616 [ 327 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_2_Control: 213 1704 [ 213 0 0 0 ] base_latency: 1 + outgoing_messages_switch_12_link_3_Control: 673 5384 [ 673 0 0 0 ] base_latency: 1 + + +Chip Stats +---------- + + --- L1Cache --- + - Event Counts - +Load 636 +Ifetch 610 +Store 704 +L1_to_L2 3 +L2_to_L1D 0 +L2_to_L1I 1 +L2_Replacement 0 +Own_GETS 636 +Own_GET_INSTR 609 +Own_GETX 704 +Own_PUTX 0 +Other_GETS 1908 +Other_GET_INSTR 1827 +Other_GETX 2112 +Other_PUTX 0 +Data 1867 + + - Transitions - +NP Load 130 +NP Ifetch 609 +NP Store 147 +NP Other_GETS 289 +NP Other_GET_INSTR 1323 +NP Other_GETX 514 +NP Other_PUTX 0 <-- + +I Load 506 +I Ifetch 0 <-- +I Store 264 +I L1_to_L2 0 <-- +I L2_to_L1D 0 <-- +I L2_to_L1I 0 <-- +I L2_Replacement 0 <-- +I Other_GETS 765 +I Other_GET_INSTR 0 <-- +I Other_GETX 796 +I Other_PUTX 0 <-- + +S Load 0 <-- +S Ifetch 1 +S Store 211 +S L1_to_L2 2 +S L2_to_L1D 0 <-- +S L2_to_L1I 1 +S L2_Replacement 0 <-- +S Other_GETS 318 +S Other_GET_INSTR 504 +S Other_GETX 333 +S Other_PUTX 0 <-- + +O Load 0 <-- +O Ifetch 0 <-- +O Store 82 +O L1_to_L2 0 <-- +O L2_to_L1D 0 <-- +O L2_to_L1I 0 <-- +O L2_Replacement 0 <-- +O Other_GETS 209 +O Other_GET_INSTR 0 <-- +O Other_GETX 242 +O Other_PUTX 0 <-- + +M Load 0 <-- +M Ifetch 0 <-- +M Store 0 <-- +M L1_to_L2 1 +M L2_to_L1D 0 <-- +M L2_to_L1I 0 <-- +M L2_Replacement 0 <-- +M Other_GETS 327 +M Other_GET_INSTR 0 <-- +M Other_GETX 227 +M Other_PUTX 0 <-- + +IS_AD Load 0 <-- +IS_AD Ifetch 0 <-- +IS_AD Store 0 <-- +IS_AD L1_to_L2 0 <-- +IS_AD L2_to_L1D 0 <-- +IS_AD L2_to_L1I 0 <-- +IS_AD L2_Replacement 0 <-- +IS_AD Own_GETS 636 +IS_AD Own_GET_INSTR 609 +IS_AD Other_GETS 0 <-- +IS_AD Other_GET_INSTR 0 <-- +IS_AD Other_GETX 0 <-- +IS_AD Other_PUTX 0 <-- +IS_AD Data 0 <-- + +IM_AD Load 0 <-- +IM_AD Ifetch 0 <-- +IM_AD Store 0 <-- +IM_AD L1_to_L2 0 <-- +IM_AD L2_to_L1D 0 <-- +IM_AD L2_to_L1I 0 <-- +IM_AD L2_Replacement 0 <-- +IM_AD Own_GETX 411 +IM_AD Other_GETS 0 <-- +IM_AD Other_GET_INSTR 0 <-- +IM_AD Other_GETX 0 <-- +IM_AD Other_PUTX 0 <-- +IM_AD Data 0 <-- + +SM_AD Load 0 <-- +SM_AD Ifetch 0 <-- +SM_AD Store 0 <-- +SM_AD L1_to_L2 0 <-- +SM_AD L2_to_L1D 0 <-- +SM_AD L2_to_L1I 0 <-- +SM_AD L2_Replacement 0 <-- +SM_AD Own_GETX 211 +SM_AD Other_GETS 0 <-- +SM_AD Other_GET_INSTR 0 <-- +SM_AD Other_GETX 0 <-- +SM_AD Other_PUTX 0 <-- +SM_AD Data 0 <-- + +OM_A Load 0 <-- +OM_A Ifetch 0 <-- +OM_A Store 0 <-- +OM_A L1_to_L2 0 <-- +OM_A L2_to_L1D 0 <-- +OM_A L2_to_L1I 0 <-- +OM_A L2_Replacement 0 <-- +OM_A Own_GETX 82 +OM_A Other_GETS 0 <-- +OM_A Other_GET_INSTR 0 <-- +OM_A Other_GETX 0 <-- +OM_A Other_PUTX 0 <-- +OM_A Data 0 <-- + +IS_A Load 0 <-- +IS_A Ifetch 0 <-- +IS_A Store 0 <-- +IS_A L1_to_L2 0 <-- +IS_A L2_to_L1D 0 <-- +IS_A L2_to_L1I 0 <-- +IS_A L2_Replacement 0 <-- +IS_A Own_GETS 0 <-- +IS_A Own_GET_INSTR 0 <-- +IS_A Other_GETS 0 <-- +IS_A Other_GET_INSTR 0 <-- +IS_A Other_GETX 0 <-- +IS_A Other_PUTX 0 <-- + +IM_A Load 0 <-- +IM_A Ifetch 0 <-- +IM_A Store 0 <-- +IM_A L1_to_L2 0 <-- +IM_A L2_to_L1D 0 <-- +IM_A L2_to_L1I 0 <-- +IM_A L2_Replacement 0 <-- +IM_A Own_GETX 0 <-- +IM_A Other_GETS 0 <-- +IM_A Other_GET_INSTR 0 <-- +IM_A Other_GETX 0 <-- +IM_A Other_PUTX 0 <-- + +SM_A Load 0 <-- +SM_A Ifetch 0 <-- +SM_A Store 0 <-- +SM_A L1_to_L2 0 <-- +SM_A L2_to_L1D 0 <-- +SM_A L2_to_L1I 0 <-- +SM_A L2_Replacement 0 <-- +SM_A Own_GETX 0 <-- +SM_A Other_GETS 0 <-- +SM_A Other_GET_INSTR 0 <-- +SM_A Other_GETX 0 <-- +SM_A Other_PUTX 0 <-- + +MI_A Load 0 <-- +MI_A Ifetch 0 <-- +MI_A Store 0 <-- +MI_A L1_to_L2 0 <-- +MI_A L2_to_L1D 0 <-- +MI_A L2_to_L1I 0 <-- +MI_A L2_Replacement 0 <-- +MI_A Own_PUTX 0 <-- +MI_A Other_GETS 0 <-- +MI_A Other_GET_INSTR 0 <-- +MI_A Other_GETX 0 <-- +MI_A Other_PUTX 0 <-- + +OI_A Load 0 <-- +OI_A Ifetch 0 <-- +OI_A Store 0 <-- +OI_A L1_to_L2 0 <-- +OI_A L2_to_L1D 0 <-- +OI_A L2_to_L1I 0 <-- +OI_A L2_Replacement 0 <-- +OI_A Own_PUTX 0 <-- +OI_A Other_GETS 0 <-- +OI_A Other_GET_INSTR 0 <-- +OI_A Other_GETX 0 <-- +OI_A Other_PUTX 0 <-- + +II_A Load 0 <-- +II_A Ifetch 0 <-- +II_A Store 0 <-- +II_A L1_to_L2 0 <-- +II_A L2_to_L1D 0 <-- +II_A L2_to_L1I 0 <-- +II_A L2_Replacement 0 <-- +II_A Own_PUTX 0 <-- +II_A Other_GETS 0 <-- +II_A Other_GET_INSTR 0 <-- +II_A Other_GETX 0 <-- +II_A Other_PUTX 0 <-- + +IS_D Load 0 <-- +IS_D Ifetch 0 <-- +IS_D Store 0 <-- +IS_D L1_to_L2 0 <-- +IS_D L2_to_L1D 0 <-- +IS_D L2_to_L1I 0 <-- +IS_D L2_Replacement 0 <-- +IS_D Other_GETS 0 <-- +IS_D Other_GET_INSTR 0 <-- +IS_D Other_GETX 0 <-- +IS_D Other_PUTX 0 <-- +IS_D Data 1245 + +IS_D_I Load 0 <-- +IS_D_I Ifetch 0 <-- +IS_D_I Store 0 <-- +IS_D_I L1_to_L2 0 <-- +IS_D_I L2_to_L1D 0 <-- +IS_D_I L2_to_L1I 0 <-- +IS_D_I L2_Replacement 0 <-- +IS_D_I Other_GETS 0 <-- +IS_D_I Other_GET_INSTR 0 <-- +IS_D_I Other_GETX 0 <-- +IS_D_I Other_PUTX 0 <-- +IS_D_I Data 0 <-- + +IM_D Load 0 <-- +IM_D Ifetch 0 <-- +IM_D Store 0 <-- +IM_D L1_to_L2 0 <-- +IM_D L2_to_L1D 0 <-- +IM_D L2_to_L1I 0 <-- +IM_D L2_Replacement 0 <-- +IM_D Other_GETS 0 <-- +IM_D Other_GET_INSTR 0 <-- +IM_D Other_GETX 0 <-- +IM_D Other_PUTX 0 <-- +IM_D Data 411 + +IM_D_O Load 0 <-- +IM_D_O Ifetch 0 <-- +IM_D_O Store 0 <-- +IM_D_O L1_to_L2 0 <-- +IM_D_O L2_to_L1D 0 <-- +IM_D_O L2_to_L1I 0 <-- +IM_D_O L2_Replacement 0 <-- +IM_D_O Other_GETS 0 <-- +IM_D_O Other_GET_INSTR 0 <-- +IM_D_O Other_GETX 0 <-- +IM_D_O Other_PUTX 0 <-- +IM_D_O Data 0 <-- + +IM_D_I Load 0 <-- +IM_D_I Ifetch 0 <-- +IM_D_I Store 0 <-- +IM_D_I L1_to_L2 0 <-- +IM_D_I L2_to_L1D 0 <-- +IM_D_I L2_to_L1I 0 <-- +IM_D_I L2_Replacement 0 <-- +IM_D_I Other_GETS 0 <-- +IM_D_I Other_GET_INSTR 0 <-- +IM_D_I Other_GETX 0 <-- +IM_D_I Other_PUTX 0 <-- +IM_D_I Data 0 <-- + +IM_D_OI Load 0 <-- +IM_D_OI Ifetch 0 <-- +IM_D_OI Store 0 <-- +IM_D_OI L1_to_L2 0 <-- +IM_D_OI L2_to_L1D 0 <-- +IM_D_OI L2_to_L1I 0 <-- +IM_D_OI L2_Replacement 0 <-- +IM_D_OI Other_GETS 0 <-- +IM_D_OI Other_GET_INSTR 0 <-- +IM_D_OI Other_GETX 0 <-- +IM_D_OI Other_PUTX 0 <-- +IM_D_OI Data 0 <-- + +SM_D Load 0 <-- +SM_D Ifetch 0 <-- +SM_D Store 0 <-- +SM_D L1_to_L2 0 <-- +SM_D L2_to_L1D 0 <-- +SM_D L2_to_L1I 0 <-- +SM_D L2_Replacement 0 <-- +SM_D Other_GETS 0 <-- +SM_D Other_GET_INSTR 0 <-- +SM_D Other_GETX 0 <-- +SM_D Other_PUTX 0 <-- +SM_D Data 211 + +SM_D_O Load 0 <-- +SM_D_O Ifetch 0 <-- +SM_D_O Store 0 <-- +SM_D_O L1_to_L2 0 <-- +SM_D_O L2_to_L1D 0 <-- +SM_D_O L2_to_L1I 0 <-- +SM_D_O L2_Replacement 0 <-- +SM_D_O Other_GETS 0 <-- +SM_D_O Other_GET_INSTR 0 <-- +SM_D_O Other_GETX 0 <-- +SM_D_O Other_PUTX 0 <-- +SM_D_O Data 0 <-- + + --- Directory --- + - Event Counts - +OtherAddress 0 +GETS 636 +GET_INSTR 609 +GETX 704 +PUTX_Owner 0 +PUTX_NotOwner 0 + + - Transitions - +C OtherAddress 0 <-- +C GETS 75 +C GET_INSTR 348 +C GETX 136 + +I GETS 0 <-- +I GET_INSTR 0 <-- +I GETX 0 <-- +I PUTX_NotOwner 0 <-- + +S GETS 9 +S GET_INSTR 93 +S GETX 17 +S PUTX_NotOwner 0 <-- + +SS GETS 16 +SS GET_INSTR 168 +SS GETX 0 <-- +SS PUTX_NotOwner 0 <-- + +OS GETS 148 +OS GET_INSTR 0 <-- +OS GETX 179 +OS PUTX_Owner 0 <-- +OS PUTX_NotOwner 0 <-- + +OSS GETS 61 +OSS GET_INSTR 0 <-- +OSS GETX 145 +OSS PUTX_Owner 0 <-- +OSS PUTX_NotOwner 0 <-- + +M GETS 327 +M GET_INSTR 0 <-- +M GETX 227 +M PUTX_Owner 0 <-- +M PUTX_NotOwner 0 <-- + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simerr b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simerr @@ -0,0 +1,3 @@ +warn: Sockets disabled, not accepting gdb connections +For more information see: http://www.m5sim.org/warn/d946bea6 +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simout b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/simout @@ -0,0 +1,94 @@ +M5 Simulator System + +Copyright (c) 2001-2008 +The Regents of The University of Michigan +All Rights Reserved + + +M5 compiled May 5 2009 07:34:00 +M5 revision 8bea207e2193 6172 default qtip tip ruby_tests_refs.diff +M5 started May 5 2009 07:34:02 +M5 executing on piton +command line: /n/piton/z/nate/build/xgem5/build/SPARC_SE/m5.fast -d /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby -re tests/run.py /n/piton/z/nate/build/xgem5/build/SPARC_SE/tests/fast/quick/40.m5threads-test-atomic/sparc/linux/simple-timing-mp-ruby +Global frequency set at 1000000000000 ticks per second +Ruby Timing Mode +Creating event queue... +Creating event queue done +Creating system... + Processors: 4 +Creating system done +Ruby initialization complete +info: Entering event queue @ 0. Starting simulation... +Init done +[Iteration 1, Thread 1] Got lock +[Iteration 1, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 1, Thread 3] Got lock +[Iteration 1, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 1, Thread 2] Got lock +[Iteration 1, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 1 completed +[Iteration 2, Thread 3] Got lock +[Iteration 2, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 2, Thread 1] Got lock +[Iteration 2, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 2, Thread 2] Got lock +[Iteration 2, Thread 2] Critical section done, previously next=1, now next=2 +Iteration 2 completed +[Iteration 3, Thread 2] Got lock +[Iteration 3, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 3, Thread 3] Got lock +[Iteration 3, Thread 3] Critical section done, previously next=2, now next=3 +[Iteration 3, Thread 1] Got lock +[Iteration 3, Thread 1] Critical section done, previously next=3, now next=1 +Iteration 3 completed +[Iteration 4, Thread 2] Got lock +[Iteration 4, Thread 2] Critical section done, previously next=0, now next=2 +[Iteration 4, Thread 1] Got lock +[Iteration 4, Thread 1] Critical section done, previously next=2, now next=1 +[Iteration 4, Thread 3] Got lock +[Iteration 4, Thread 3] Critical section done, previously next=1, now next=3 +Iteration 4 completed +[Iteration 5, Thread 3] Got lock +[Iteration 5, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 5, Thread 2] Got lock +[Iteration 5, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 5, Thread 1] Got lock +[Iteration 5, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 5 completed +[Iteration 6, Thread 1] Got lock +[Iteration 6, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 6, Thread 3] Got lock +[Iteration 6, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 6, Thread 2] Got lock +[Iteration 6, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 6 completed +[Iteration 7, Thread 3] Got lock +[Iteration 7, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 7, Thread 2] Got lock +[Iteration 7, Thread 2] Critical section done, previously next=3, now next=2 +[Iteration 7, Thread 1] Got lock +[Iteration 7, Thread 1] Critical section done, previously next=2, now next=1 +Iteration 7 completed +[Iteration 8, Thread 3] Got lock +[Iteration 8, Thread 3] Critical section done, previously next=0, now next=3 +[Iteration 8, Thread 1] Got lock +[Iteration 8, Thread 1] Critical section done, previously next=3, now next=1 +[Iteration 8, Thread 2] Got lock +[Iteration 8, Thread 2] Critical section done, previously next=1, now next=2 +Iteration 8 completed +[Iteration 9, Thread 1] Got lock +[Iteration 9, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 9, Thread 2] Got lock +[Iteration 9, Thread 2] Critical section done, previously next=1, now next=2 +[Iteration 9, Thread 3] Got lock +[Iteration 9, Thread 3] Critical section done, previously next=2, now next=3 +Iteration 9 completed +[Iteration 10, Thread 1] Got lock +[Iteration 10, Thread 1] Critical section done, previously next=0, now next=1 +[Iteration 10, Thread 3] Got lock +[Iteration 10, Thread 3] Critical section done, previously next=1, now next=3 +[Iteration 10, Thread 2] Got lock +[Iteration 10, Thread 2] Critical section done, previously next=3, now next=2 +Iteration 10 completed +PASSED :-) +Exiting @ tick 2480212000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/skip b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/skip --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/skip @@ -0,0 +1,1 @@ +Skipping for now due to broken atomics in ruby diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp-ruby/stats.txt @@ -0,0 +1,33 @@ + +---------- Begin Simulation Statistics ---------- +host_inst_rate 15492 # Simulator instruction rate (inst/s) +host_mem_usage 258096 # Number of bytes of host memory used +host_seconds 39.33 # Real time elapsed on the host +host_tick_rate 63054672 # Simulator tick rate (ticks/s) +sim_freq 1000000000000 # Frequency of simulated ticks +sim_insts 609352 # Number of instructions simulated +sim_seconds 0.002480 # Number of seconds simulated +sim_ticks 2480212000 # Number of ticks simulated +system.cpu0.idle_fraction 0.011975 # Percentage of idle cycles +system.cpu0.not_idle_fraction 0.988025 # Percentage of non-idle cycles +system.cpu0.numCycles 4944742 # number of cpu cycles simulated +system.cpu0.num_insts 156931 # Number of instructions executed +system.cpu0.num_refs 47256 # Number of memory references +system.cpu0.workload.PROG:num_syscalls 89 # Number of system calls +system.cpu1.idle_fraction 0.012259 # Percentage of idle cycles +system.cpu1.not_idle_fraction 0.987741 # Percentage of non-idle cycles +system.cpu1.numCycles 4944666 # number of cpu cycles simulated +system.cpu1.num_insts 152657 # Number of instructions executed +system.cpu1.num_refs 51452 # Number of memory references +system.cpu2.idle_fraction 0 # Percentage of idle cycles +system.cpu2.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu2.numCycles 4960424 # number of cpu cycles simulated +system.cpu2.num_insts 146173 # Number of instructions executed +system.cpu2.num_refs 67815 # Number of memory references +system.cpu3.idle_fraction 0.011794 # Percentage of idle cycles +system.cpu3.not_idle_fraction 0.988206 # Percentage of non-idle cycles +system.cpu3.numCycles 4944758 # number of cpu cycles simulated +system.cpu3.num_insts 153591 # Number of instructions executed +system.cpu3.num_refs 50671 # Number of memory references + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/config.ini @@ -0,0 +1,479 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[1] + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=SparcTLB +size=64 + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=SparcInterrupts + +[system.cpu0.itb] +type=SparcTLB +size=64 + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test___thread 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/sparc/linux/test___thread +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[3] + +[system.cpu1.dtb] +type=SparcTLB +size=64 + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[2] + +[system.cpu1.interrupts] +type=SparcInterrupts + +[system.cpu1.itb] +type=SparcTLB +size=64 + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu2.dtb] +type=SparcTLB +size=64 + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu2.interrupts] +type=SparcInterrupts + +[system.cpu2.itb] +type=SparcTLB +size=64 + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[7] + +[system.cpu3.dtb] +type=SparcTLB +size=64 + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[6] + +[system.cpu3.interrupts] +type=SparcInterrupts + +[system.cpu3.itb] +type=SparcTLB +size=64 + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.physmem.port[0] +slave=system.l2c.mem_side system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[0] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu3.icache.mem_side system.cpu3.dcache.mem_side + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simerr @@ -0,0 +1,2 @@ +warn: Sockets disabled, not accepting gdb connections +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/simout @@ -0,0 +1,89 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 16:06:31 +gem5 started May 16 2012 20:20:05 +gem5 executing on SC2B0617 +command line: build/SPARC/gem5.opt -d build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/simple-timing-mp -re tests/run.py build/SPARC/tests/opt/quick/se/40.m5threads-test___thread/sparc/linux/simple-timing-mp +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0: Constructing CPU with id 0 + 0: system.cpu1: Constructing CPU with id 1 + 0: system.cpu2: Constructing CPU with id 2 + 0: system.cpu3: Constructing CPU with id 3 +info: Entering event queue @ 0. Starting simulation... +1859000: system.cpu0: syscall uname called w/arguments 1048640,0,2750464,8796093021226 +1859000: system.cpu0: syscall uname returns 0 +2942000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +2942000: system.cpu0: syscall mmap returns 18446735277616529408 +12523000: system.cpu0: syscall brk called w/arguments 0,0,1385948,0 +12523000: system.cpu0: syscall brk returns 2752512 +12601000: system.cpu0: syscall brk called w/arguments 0,0,1385948,2891776 +12601000: global: Break Point changed to: 0X2C2000 +12601000: system.cpu0: syscall brk returns 2891776 +24900000: system.cpu0: syscall fstat called w/arguments 132620,8796093018288,8796093017992,1 +24900000: global: fstat(1, ...) +24900000: system.cpu0: syscall fstat returns 0 +25785000: system.cpu0: syscall mmap called w/arguments 34,3,8192,0 +25785000: system.cpu0: syscall mmap returns 18446735277616660480 +29918000: system.cpu0: syscall write called w/arguments 0,22,18446735277616660480,1 +Starting 4 threads... +29918000: system.cpu0: syscall write returns 22 +31651000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +31651000: system.cpu0: syscall mmap returns 18446735277616668672 +31817000: system.cpu0: syscall clone called w/arguments 0,12,18446735277616795649,69376 +31817000: global: In sys_clone: +31817000: global: Flags=10f00 +31817000: global: Child stack=fffff80000041001 +31817000: global: Found unallocated thread context +31817000: system.cpu0: syscall clone returns 1 +31875000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +31875000: system.cpu0: syscall mmap returns 18446735277616799744 +31973000: system.cpu0: syscall clone called w/arguments 0,12,18446735277616926721,69376 +31973000: global: In sys_clone: +31973000: global: Flags=10f00 +31973000: global: Child stack=fffff80000061001 +31973000: global: Found unallocated thread context +31973000: system.cpu0: syscall clone returns 1 +32032000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +32032000: system.cpu0: syscall mmap returns 18446735277616930816 +32130000: system.cpu0: syscall clone called w/arguments 0,12,18446735277617057793,69376 +32130000: global: In sys_clone: +32130000: global: Flags=10f00 +32130000: global: Child stack=fffff80000081001 +32130000: global: Found unallocated thread context +32130000: system.cpu0: syscall clone returns 1 +34975000: system.cpu0: syscall write called w/arguments 0,29,18446735277616660480,1 +&local[0]=0xfffff80000000000 +34975000: system.cpu0: syscall write returns 29 +37949000: system.cpu1: syscall write called w/arguments 18446735277616668672,29,18446735277616660480,1 +&local[1]=0xfffff80000022038 +37949000: system.cpu1: syscall write returns 29 +41037000: system.cpu3: syscall write called w/arguments 18446735277616930816,29,18446735277616660480,1 +&local[3]=0xfffff80000062038 +41037000: system.cpu3: syscall write returns 29 +44129000: system.cpu2: syscall write called w/arguments 18446735277616799744,29,18446735277616660480,1 +&local[2]=0xfffff80000042038 +44129000: system.cpu2: syscall write returns 29 +155773000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[0] = 1031 +155773000: system.cpu0: syscall write returns 16 +157799000: system.cpu1: syscall exit called w/arguments 3,132620,0,0 +157799000: system.cpu1: syscall exit returns 1 +159348000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[1] = 1032 +159348000: system.cpu0: syscall write returns 16 +160651000: system.cpu3: syscall exit called w/arguments 3,132620,0,0 +160651000: system.cpu3: syscall exit returns 1 +163845000: system.cpu2: syscall exit called w/arguments 3,132620,0,0 +163845000: system.cpu2: syscall exit returns 1 +165381000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[2] = 1033 +165381000: system.cpu0: syscall write returns 16 +167210000: system.cpu0: syscall write called w/arguments 0,16,18446735277616660480,1 +local[3] = 1034 +167210000: system.cpu0: syscall write returns 16 +170458000: system.cpu0: syscall munmap called w/arguments 0,0,8192,18446735277616660480 +170458000: system.cpu0: syscall munmap returns 0 +170879000: system.cpu0: syscall exit_group called w/arguments 1504373,0,0,0 +170879000: system.cpu0: syscall exit_group returns 1 +Exiting @ tick 170879000 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/sparc/linux/simple-timing-mp/stats.txt @@ -0,0 +1,1112 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000171 # Number of seconds simulated +sim_ticks 170879000 # Number of ticks simulated +final_tick 170879000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 1128906 # Simulator instruction rate (inst/s) +host_op_rate 1128822 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 396051055 # Simulator tick rate (ticks/s) +host_mem_usage 274160 # Number of bytes of host memory used +host_seconds 0.43 # Real time elapsed on the host +sim_insts 487010 # Number of instructions simulated +sim_ops 487010 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 35904 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22016 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 561 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 210113589 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 128839705 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 210113589 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 26 # Number of system calls +system.cpu0.numCycles 341758 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 124774 # Number of instructions committed +system.cpu0.committedOps 124774 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 109440 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 304 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13643 # number of instructions that are conditional controls +system.cpu0.num_int_insts 109440 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 225393 # number of times the integer registers were read +system.cpu0.num_int_register_writes 120424 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 17136 # number of memory refs +system.cpu0.num_load_insts 14119 # Number of load instructions +system.cpu0.num_store_insts 3017 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 341758 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu0.icache.replacements 167 # number of replacements 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rate for overall accesses +system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 47289.855072 # average ReadReq miss latency +system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 47289.855072 # average overall miss latency +system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 47289.855072 # average overall miss latency +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 414 # number of ReadReq MSHR misses +system.cpu0.icache.ReadReq_mshr_misses::total 414 # number of ReadReq MSHR misses +system.cpu0.icache.demand_mshr_misses::cpu0.inst 414 # number of demand (read+write) MSHR misses +system.cpu0.icache.demand_mshr_misses::total 414 # number of demand (read+write) MSHR misses +system.cpu0.icache.overall_mshr_misses::cpu0.inst 414 # number of overall MSHR misses +system.cpu0.icache.overall_mshr_misses::total 414 # number of overall MSHR misses +system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 18336000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.ReadReq_mshr_miss_latency::total 18336000 # number of ReadReq MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 18336000 # number of demand (read+write) MSHR miss cycles +system.cpu0.icache.demand_mshr_miss_latency::total 18336000 # number of demand (read+write) MSHR miss cycles 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(read+write) accesses +system.cpu0.dcache.overall_accesses::total 17101 # number of overall (read+write) accesses +system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006166 # miss rate for ReadReq accesses +system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.032765 # miss rate for WriteReq accesses +system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.375000 # miss rate for SwapReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.010818 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.010818 # miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 51896.551724 # average ReadReq miss latency +system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 52622.448980 # average WriteReq miss latency +system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 47500 # average SwapReq miss latency +system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 52281.081081 # average overall miss latency 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rate for WriteReq accesses +system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.375000 # mshr miss rate for SwapReq accesses +system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.010818 # mshr miss rate for demand accesses +system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.010818 # mshr miss rate for overall accesses +system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 48896.551724 # average ReadReq mshr miss latency +system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 49622.448980 # average WriteReq mshr miss latency +system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 44500 # average SwapReq mshr miss latency +system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 49281.081081 # average overall mshr miss latency +system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 49281.081081 # average overall mshr miss latency +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 341758 # number of cpu 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0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 15364 # number of memory refs +system.cpu1.num_load_insts 14174 # Number of load instructions +system.cpu1.num_store_insts 1190 # Number of store instructions +system.cpu1.num_idle_cycles 89794.001475 # Number of idle cycles +system.cpu1.num_busy_cycles 251963.998525 # Number of busy cycles +system.cpu1.not_idle_fraction 0.737259 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.262741 # Percentage of idle cycles +system.cpu1.icache.replacements 14 # number of replacements +system.cpu1.icache.tagsinuse 62.270563 # Cycle average of tags in use +system.cpu1.icache.total_refs 120405 # Total number of references to valid blocks. +system.cpu1.icache.sampled_refs 98 # Sample count of references to valid blocks. +system.cpu1.icache.avg_refs 1228.622449 # Average number of references to valid blocks. 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21045.918367 # average overall miss latency +system.cpu1.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu1.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu1.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu1.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu1.icache.fast_writes 0 # number of fast writes performed +system.cpu1.icache.cache_copies 0 # number of cache copies performed +system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 98 # number of ReadReq MSHR misses +system.cpu1.icache.ReadReq_mshr_misses::total 98 # number of ReadReq MSHR misses +system.cpu1.icache.demand_mshr_misses::cpu1.inst 98 # number of demand (read+write) MSHR misses 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921000 # number of WriteReq miss cycles +system.cpu1.dcache.WriteReq_miss_latency::total 921000 # number of WriteReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 10000 # number of SwapReq miss cycles +system.cpu1.dcache.SwapReq_miss_latency::total 10000 # number of SwapReq miss cycles +system.cpu1.dcache.demand_miss_latency::cpu1.data 1279000 # number of demand (read+write) miss cycles +system.cpu1.dcache.demand_miss_latency::total 1279000 # number of demand (read+write) miss cycles +system.cpu1.dcache.overall_miss_latency::cpu1.data 1279000 # number of overall miss cycles +system.cpu1.dcache.overall_miss_latency::total 1279000 # number of overall miss cycles +system.cpu1.dcache.ReadReq_accesses::cpu1.data 14167 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.ReadReq_accesses::total 14167 # number of ReadReq accesses(hits+misses) +system.cpu1.dcache.WriteReq_accesses::cpu1.data 1186 # number of WriteReq accesses(hits+misses) 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for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.016863 # miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 1 # miss rate for SwapReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.003044 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.003044 # miss rate for overall accesses +system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 12000 # average ReadReq miss latency +system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 45850 # average WriteReq miss latency +system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6250 # average SwapReq miss latency +system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 26404.255319 # average overall miss latency +system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 26404.255319 # average overall miss latency +system.cpu2.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu2.dcache.blocked_cycles::no_targets 0 # number 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number of SwapReq MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 1100000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.demand_mshr_miss_latency::total 1100000 # number of demand (read+write) MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 1100000 # number of overall MSHR miss cycles +system.cpu2.dcache.overall_mshr_miss_latency::total 1100000 # number of overall MSHR miss cycles +system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.001894 # mshr miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.016863 # mshr miss rate for WriteReq accesses +system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for SwapReq accesses +system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003044 # mshr miss rate for demand accesses +system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003044 # mshr miss rate for overall accesses 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instructions +system.cpu3.num_idle_cycles 84716.001504 # Number of idle cycles +system.cpu3.num_busy_cycles 257041.998496 # Number of busy cycles +system.cpu3.not_idle_fraction 0.752117 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.247883 # Percentage of idle cycles +system.cpu3.icache.replacements 14 # number of replacements +system.cpu3.icache.tagsinuse 61.160605 # Cycle average of tags in use +system.cpu3.icache.total_refs 120813 # Total number of references to valid blocks. +system.cpu3.icache.sampled_refs 98 # Sample count of references to valid blocks. +system.cpu3.icache.avg_refs 1232.785714 # Average number of references to valid blocks. +system.cpu3.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu3.icache.occ_blocks::cpu3.inst 61.160605 # Average occupied blocks per requestor +system.cpu3.icache.occ_percent::cpu3.inst 0.119454 # Average percentage of cache occupancy +system.cpu3.icache.occ_percent::total 0.119454 # Average percentage of cache occupancy +system.cpu3.icache.ReadReq_hits::cpu3.inst 120813 # number of ReadReq hits +system.cpu3.icache.ReadReq_hits::total 120813 # number of ReadReq hits +system.cpu3.icache.demand_hits::cpu3.inst 120813 # number of demand (read+write) hits +system.cpu3.icache.demand_hits::total 120813 # number of demand (read+write) hits +system.cpu3.icache.overall_hits::cpu3.inst 120813 # number of overall hits +system.cpu3.icache.overall_hits::total 120813 # number of overall hits +system.cpu3.icache.ReadReq_misses::cpu3.inst 98 # number of ReadReq misses +system.cpu3.icache.ReadReq_misses::total 98 # number of ReadReq misses +system.cpu3.icache.demand_misses::cpu3.inst 98 # number of demand (read+write) misses +system.cpu3.icache.demand_misses::total 98 # number of demand (read+write) misses +system.cpu3.icache.overall_misses::cpu3.inst 98 # number of overall misses +system.cpu3.icache.overall_misses::total 98 # number of overall misses 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number of overall (read+write) accesses +system.cpu3.icache.overall_accesses::total 120911 # number of overall (read+write) accesses +system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.000811 # miss rate for ReadReq accesses +system.cpu3.icache.demand_miss_rate::cpu3.inst 0.000811 # miss rate for demand accesses +system.cpu3.icache.overall_miss_rate::cpu3.inst 0.000811 # miss rate for overall accesses +system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 14188.775510 # average ReadReq miss latency +system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 14188.775510 # average overall miss latency +system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 14188.775510 # average overall miss latency +system.cpu3.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.icache.blocked::no_targets 0 # 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Average percentage of cache occupancy +system.cpu3.dcache.ReadReq_hits::cpu3.data 14243 # number of ReadReq hits +system.cpu3.dcache.ReadReq_hits::total 14243 # number of ReadReq hits +system.cpu3.dcache.WriteReq_hits::cpu3.data 1167 # number of WriteReq hits +system.cpu3.dcache.WriteReq_hits::total 1167 # number of WriteReq hits +system.cpu3.dcache.demand_hits::cpu3.data 15410 # number of demand (read+write) hits +system.cpu3.dcache.demand_hits::total 15410 # number of demand (read+write) hits +system.cpu3.dcache.overall_hits::cpu3.data 15410 # number of overall hits +system.cpu3.dcache.overall_hits::total 15410 # number of overall hits +system.cpu3.dcache.ReadReq_misses::cpu3.data 25 # number of ReadReq misses +system.cpu3.dcache.ReadReq_misses::total 25 # number of ReadReq misses +system.cpu3.dcache.WriteReq_misses::cpu3.data 19 # number of WriteReq misses +system.cpu3.dcache.WriteReq_misses::total 19 # number of WriteReq misses +system.cpu3.dcache.SwapReq_misses::cpu3.data 3 # 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1120000 # number of demand (read+write) miss cycles +system.cpu3.dcache.demand_miss_latency::total 1120000 # number of demand (read+write) miss cycles +system.cpu3.dcache.overall_miss_latency::cpu3.data 1120000 # number of overall miss cycles +system.cpu3.dcache.overall_miss_latency::total 1120000 # number of overall miss cycles +system.cpu3.dcache.ReadReq_accesses::cpu3.data 14268 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.ReadReq_accesses::total 14268 # number of ReadReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::cpu3.data 1186 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.WriteReq_accesses::total 1186 # number of WriteReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::cpu3.data 3 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.SwapReq_accesses::total 3 # number of SwapReq accesses(hits+misses) +system.cpu3.dcache.demand_accesses::cpu3.data 15454 # number of demand (read+write) accesses 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SwapReq miss latency +system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 25454.545455 # average overall miss latency +system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 25454.545455 # average overall miss latency +system.cpu3.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu3.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu3.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu3.dcache.fast_writes 0 # number of fast writes performed +system.cpu3.dcache.cache_copies 0 # number of cache copies performed +system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 25 # number of ReadReq MSHR misses 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+system.l2c.ReadReq_mshr_miss_rate::cpu0.data 0.974359 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.inst 0.153061 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu1.data 0.133333 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.inst 0.010204 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu2.data 0.066667 # mshr miss rate for ReadReq accesses +system.l2c.ReadReq_mshr_miss_rate::cpu3.data 0.066667 # mshr miss rate for ReadReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu0.data 0.250000 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.UpgradeReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for UpgradeReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 # mshr miss rate for ReadExReq accesses +system.l2c.demand_mshr_miss_rate::cpu0.inst 0.792271 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu0.data 0.988439 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.inst 0.153061 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu1.data 0.551724 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.inst 0.010204 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu2.data 0.517241 # mshr miss rate for demand accesses +system.l2c.demand_mshr_miss_rate::cpu3.data 0.517241 # mshr miss rate for demand accesses +system.l2c.overall_mshr_miss_rate::cpu0.inst 0.792271 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu0.data 0.988439 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.inst 0.153061 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu1.data 0.551724 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.inst 0.010204 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu2.data 0.517241 # mshr miss rate for overall accesses +system.l2c.overall_mshr_miss_rate::cpu3.data 0.517241 # mshr miss rate for overall accesses +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu0.data 40013.157895 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.inst 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadReq mshr miss latency +system.l2c.ReadReq_avg_mshr_miss_latency::cpu3.data 40000 # average ReadReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu0.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu1.data 40000 # average UpgradeReq mshr miss latency +system.l2c.UpgradeReq_avg_mshr_miss_latency::cpu2.data 40000 # average UpgradeReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 40000 # average ReadExReq mshr miss latency +system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 40071.428571 # average ReadExReq mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu0.data 40005.847953 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.demand_avg_mshr_miss_latency::cpu3.data 40066.666667 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu0.data 40005.847953 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu1.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu2.data 40000 # average overall mshr miss latency +system.l2c.overall_avg_mshr_miss_latency::cpu3.data 40066.666667 # average overall mshr miss latency +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/config.ini @@ -0,0 +1,1887 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer workload +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=0 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu0.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu0.interrupts +issueToExecuteDelay=1 +issueWidth=8 +itb=system.cpu0.itb +localCtrBits=2 +localHistoryBits=11 +localHistoryTableSize=2048 +localPredictorSize=2048 +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +needsTSO=true +numIQEntries=64 +numPhysFloatRegs=256 +numPhysIntRegs=256 +numROBEntries=192 +numRobs=1 +numThreads=1 +phase=0 +predType=tournament +profile=0 +progress_interval=0 +renameToDecodeDelay=1 +renameToFetchDelay=1 +renameToIEWDelay=2 +renameToROBDelay=1 +renameWidth=8 +smtCommitPolicy=RoundRobin +smtFetchPolicy=SingleThread +smtIQPolicy=Partitioned +smtIQThreshold=100 +smtLSQPolicy=Partitioned +smtLSQThreshold=100 +smtNumFetchingThreads=1 +smtROBPolicy=Partitioned +smtROBThreshold=100 +squashWidth=8 +store_set_clear_period=250000 +system=system +tracer=system.cpu0.tracer +trapLatency=13 +wbDepth=1 +wbWidth=8 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[3] + +[system.cpu0.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu0.fuPool.FUList0 system.cpu0.fuPool.FUList1 system.cpu0.fuPool.FUList2 system.cpu0.fuPool.FUList3 system.cpu0.fuPool.FUList4 system.cpu0.fuPool.FUList5 system.cpu0.fuPool.FUList6 system.cpu0.fuPool.FUList7 system.cpu0.fuPool.FUList8 + +[system.cpu0.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu0.fuPool.FUList0.opList + +[system.cpu0.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu0.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu0.fuPool.FUList1.opList0 system.cpu0.fuPool.FUList1.opList1 + +[system.cpu0.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu0.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu0.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu0.fuPool.FUList2.opList0 system.cpu0.fuPool.FUList2.opList1 system.cpu0.fuPool.FUList2.opList2 + +[system.cpu0.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu0.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu0.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu0.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu0.fuPool.FUList3.opList0 system.cpu0.fuPool.FUList3.opList1 system.cpu0.fuPool.FUList3.opList2 + +[system.cpu0.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu0.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu0.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu0.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList4.opList + +[system.cpu0.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu0.fuPool.FUList5.opList00 system.cpu0.fuPool.FUList5.opList01 system.cpu0.fuPool.FUList5.opList02 system.cpu0.fuPool.FUList5.opList03 system.cpu0.fuPool.FUList5.opList04 system.cpu0.fuPool.FUList5.opList05 system.cpu0.fuPool.FUList5.opList06 system.cpu0.fuPool.FUList5.opList07 system.cpu0.fuPool.FUList5.opList08 system.cpu0.fuPool.FUList5.opList09 system.cpu0.fuPool.FUList5.opList10 system.cpu0.fuPool.FUList5.opList11 system.cpu0.fuPool.FUList5.opList12 system.cpu0.fuPool.FUList5.opList13 system.cpu0.fuPool.FUList5.opList14 system.cpu0.fuPool.FUList5.opList15 system.cpu0.fuPool.FUList5.opList16 system.cpu0.fuPool.FUList5.opList17 system.cpu0.fuPool.FUList5.opList18 system.cpu0.fuPool.FUList5.opList19 + +[system.cpu0.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu0.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu0.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu0.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu0.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu0.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu0.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu0.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu0.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu0.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu0.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu0.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu0.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu0.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu0.fuPool.FUList6.opList + +[system.cpu0.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu0.fuPool.FUList7.opList0 system.cpu0.fuPool.FUList7.opList1 + +[system.cpu0.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu0.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu0.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu0.fuPool.FUList8.opList + +[system.cpu0.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=DerivO3CPU +children=dcache dtb fuPool icache interrupts itb tracer +BTBEntries=4096 +BTBTagSize=16 +LFSTSize=1024 +LQEntries=32 +LSQCheckLoads=true +LSQDepCheckShift=4 +RASSize=16 +SQEntries=32 +SSITSize=1024 +activity=0 +backComSize=5 +cachePorts=200 +checker=Null +choiceCtrBits=2 +choicePredictorSize=8192 +clock=500 +commitToDecodeDelay=1 +commitToFetchDelay=1 +commitToIEWDelay=1 +commitToRenameDelay=1 +commitWidth=8 +cpu_id=1 +decodeToFetchDelay=1 +decodeToRenameDelay=1 +decodeWidth=8 +defer_registration=false +dispatchWidth=8 +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fetchToDecodeDelay=1 +fetchTrapLatency=1 +fetchWidth=8 +forwardComSize=5 +fuPool=system.cpu1.fuPool +function_trace=false +function_trace_start=0 +globalCtrBits=2 +globalHistoryBits=13 +globalPredictorSize=8192 +iewToCommitDelay=1 +iewToDecodeDelay=1 +iewToFetchDelay=1 +iewToRenameDelay=1 +instShiftAmt=2 +interrupts=system.cpu1.interrupts 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+system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[13] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[15] + +[system.cpu3.fuPool] +type=FUPool +children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 +FUList=system.cpu3.fuPool.FUList0 system.cpu3.fuPool.FUList1 system.cpu3.fuPool.FUList2 system.cpu3.fuPool.FUList3 system.cpu3.fuPool.FUList4 system.cpu3.fuPool.FUList5 system.cpu3.fuPool.FUList6 system.cpu3.fuPool.FUList7 system.cpu3.fuPool.FUList8 + +[system.cpu3.fuPool.FUList0] +type=FUDesc +children=opList +count=6 +opList=system.cpu3.fuPool.FUList0.opList + +[system.cpu3.fuPool.FUList0.opList] +type=OpDesc +issueLat=1 +opClass=IntAlu +opLat=1 + +[system.cpu3.fuPool.FUList1] +type=FUDesc +children=opList0 opList1 +count=2 +opList=system.cpu3.fuPool.FUList1.opList0 system.cpu3.fuPool.FUList1.opList1 + +[system.cpu3.fuPool.FUList1.opList0] +type=OpDesc +issueLat=1 +opClass=IntMult +opLat=3 + +[system.cpu3.fuPool.FUList1.opList1] +type=OpDesc +issueLat=19 +opClass=IntDiv +opLat=20 + +[system.cpu3.fuPool.FUList2] +type=FUDesc +children=opList0 opList1 opList2 +count=4 +opList=system.cpu3.fuPool.FUList2.opList0 system.cpu3.fuPool.FUList2.opList1 system.cpu3.fuPool.FUList2.opList2 + +[system.cpu3.fuPool.FUList2.opList0] +type=OpDesc +issueLat=1 +opClass=FloatAdd +opLat=2 + +[system.cpu3.fuPool.FUList2.opList1] +type=OpDesc +issueLat=1 +opClass=FloatCmp +opLat=2 + +[system.cpu3.fuPool.FUList2.opList2] +type=OpDesc +issueLat=1 +opClass=FloatCvt +opLat=2 + +[system.cpu3.fuPool.FUList3] +type=FUDesc +children=opList0 opList1 opList2 +count=2 +opList=system.cpu3.fuPool.FUList3.opList0 system.cpu3.fuPool.FUList3.opList1 system.cpu3.fuPool.FUList3.opList2 + +[system.cpu3.fuPool.FUList3.opList0] +type=OpDesc +issueLat=1 +opClass=FloatMult +opLat=4 + +[system.cpu3.fuPool.FUList3.opList1] +type=OpDesc +issueLat=12 +opClass=FloatDiv +opLat=12 + +[system.cpu3.fuPool.FUList3.opList2] +type=OpDesc +issueLat=24 +opClass=FloatSqrt +opLat=24 + +[system.cpu3.fuPool.FUList4] +type=FUDesc +children=opList +count=0 +opList=system.cpu3.fuPool.FUList4.opList + +[system.cpu3.fuPool.FUList4.opList] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu3.fuPool.FUList5] +type=FUDesc +children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 +count=4 +opList=system.cpu3.fuPool.FUList5.opList00 system.cpu3.fuPool.FUList5.opList01 system.cpu3.fuPool.FUList5.opList02 system.cpu3.fuPool.FUList5.opList03 system.cpu3.fuPool.FUList5.opList04 system.cpu3.fuPool.FUList5.opList05 system.cpu3.fuPool.FUList5.opList06 system.cpu3.fuPool.FUList5.opList07 system.cpu3.fuPool.FUList5.opList08 system.cpu3.fuPool.FUList5.opList09 system.cpu3.fuPool.FUList5.opList10 system.cpu3.fuPool.FUList5.opList11 system.cpu3.fuPool.FUList5.opList12 system.cpu3.fuPool.FUList5.opList13 system.cpu3.fuPool.FUList5.opList14 system.cpu3.fuPool.FUList5.opList15 system.cpu3.fuPool.FUList5.opList16 system.cpu3.fuPool.FUList5.opList17 system.cpu3.fuPool.FUList5.opList18 system.cpu3.fuPool.FUList5.opList19 + +[system.cpu3.fuPool.FUList5.opList00] +type=OpDesc +issueLat=1 +opClass=SimdAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList01] +type=OpDesc +issueLat=1 +opClass=SimdAddAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList02] +type=OpDesc +issueLat=1 +opClass=SimdAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList03] +type=OpDesc +issueLat=1 +opClass=SimdCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList04] +type=OpDesc +issueLat=1 +opClass=SimdCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList05] +type=OpDesc +issueLat=1 +opClass=SimdMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList06] +type=OpDesc +issueLat=1 +opClass=SimdMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList07] +type=OpDesc +issueLat=1 +opClass=SimdMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList08] +type=OpDesc +issueLat=1 +opClass=SimdShift +opLat=1 + +[system.cpu3.fuPool.FUList5.opList09] +type=OpDesc +issueLat=1 +opClass=SimdShiftAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList10] +type=OpDesc +issueLat=1 +opClass=SimdSqrt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList11] +type=OpDesc +issueLat=1 +opClass=SimdFloatAdd +opLat=1 + +[system.cpu3.fuPool.FUList5.opList12] +type=OpDesc +issueLat=1 +opClass=SimdFloatAlu +opLat=1 + +[system.cpu3.fuPool.FUList5.opList13] +type=OpDesc +issueLat=1 +opClass=SimdFloatCmp +opLat=1 + +[system.cpu3.fuPool.FUList5.opList14] +type=OpDesc +issueLat=1 +opClass=SimdFloatCvt +opLat=1 + +[system.cpu3.fuPool.FUList5.opList15] +type=OpDesc +issueLat=1 +opClass=SimdFloatDiv +opLat=1 + +[system.cpu3.fuPool.FUList5.opList16] +type=OpDesc +issueLat=1 +opClass=SimdFloatMisc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList17] +type=OpDesc +issueLat=1 +opClass=SimdFloatMult +opLat=1 + +[system.cpu3.fuPool.FUList5.opList18] +type=OpDesc +issueLat=1 +opClass=SimdFloatMultAcc +opLat=1 + +[system.cpu3.fuPool.FUList5.opList19] +type=OpDesc +issueLat=1 +opClass=SimdFloatSqrt +opLat=1 + +[system.cpu3.fuPool.FUList6] +type=FUDesc +children=opList +count=0 +opList=system.cpu3.fuPool.FUList6.opList + +[system.cpu3.fuPool.FUList6.opList] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList7] +type=FUDesc +children=opList0 opList1 +count=4 +opList=system.cpu3.fuPool.FUList7.opList0 system.cpu3.fuPool.FUList7.opList1 + +[system.cpu3.fuPool.FUList7.opList0] +type=OpDesc +issueLat=1 +opClass=MemRead +opLat=1 + +[system.cpu3.fuPool.FUList7.opList1] +type=OpDesc +issueLat=1 +opClass=MemWrite +opLat=1 + +[system.cpu3.fuPool.FUList8] +type=FUDesc +children=opList +count=1 +opList=system.cpu3.fuPool.FUList8.opList + +[system.cpu3.fuPool.FUList8.opList] +type=OpDesc +issueLat=3 +opClass=IprAccess +opLat=3 + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=20 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simerr @@ -0,0 +1,4 @@ +fatal: Can't load object file /proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic + @ cycle 0 +[create:build/X86/sim/process.cc, line 608] +Memory Usage: 252636 KBytes diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/simout @@ -0,0 +1,8 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 10:54:19 +gem5 started May 16 2012 14:10:25 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/o3-timing-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/o3-timing-mp +Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/skip b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/skip diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/o3-timing-mp/stats.txt diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/config.ini @@ -0,0 +1,579 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=atomic +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu0.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test___thread 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test___thread +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu1.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[7] + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[3] +pio=system.membus.master[2] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[6] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu2.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[9] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[11] + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[8] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[3] +int_slave=system.membus.master[5] +pio=system.membus.master[4] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[10] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=AtomicSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +fastmem=false +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +simulate_data_stalls=false +simulate_inst_stalls=false +system=system +tracer=system.cpu3.tracer +width=1 +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[13] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[15] + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:1073741823 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/simout @@ -0,0 +1,149 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 20:10:02 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test___thread/x86/linux/simple-atomic-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test___thread/x86/linux/simple-atomic-mp +Global frequency set at 1000000000000 ticks per second + 0: system.cpu0: Constructing CPU with id 0 + 0: system.cpu1: Constructing CPU with id 1 + 0: system.cpu2: Constructing CPU with id 2 + 0: system.cpu3: Constructing CPU with id 3 +info: Entering event queue @ 0. Starting simulation... +262000: system.cpu0: syscall uname called w/arguments 4194368,0,0,140737488350144 +262000: system.cpu0: syscall uname returns 0 +447500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +447500: system.cpu0: syscall mmap returns 46912496119808 +525500: system.cpu0: syscall arch_prctl called w/arguments 6920928,0,46912496119960,4098 +525500: system.cpu0: syscall arch_prctl returns 0 +1987500: system.cpu0: syscall brk called w/arguments 6920928,131136,0,0 +1987500: system.cpu0: syscall brk returns 7024640 +2007000: system.cpu0: syscall brk called w/arguments 6920928,7024640,7159808,7159808 +2007000: global: Break Point changed to: 0X6D4000 +2007000: system.cpu0: syscall brk returns 7159808 +3908000: system.cpu0: syscall fstat called w/arguments 0,140737488347824,140737488347824,1 +3908000: system.cpu0: syscall fstat returns 0 +3948000: system.cpu0: syscall mmap called w/arguments 34,3,8192,0 +3948000: system.cpu0: syscall mmap returns 46912496250880 +5320500: system.cpu0: syscall write called w/arguments 34,22,46912496250880,1 +Starting 4 threads... +5320500: system.cpu0: syscall write returns 22 +5752500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +5752500: system.cpu0: syscall mmap returns 46912496259072 +5784500: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496388080,69376 +5784500: global: In sys_clone: +5784500: global: Flags=10f00 +5784500: global: Child stack=2aaaaaaec7f0 +5784500: global: Found unallocated thread context +5784500: system.cpu0: syscall clone returns 1 +5797000: system.cpu1: syscall getpid called w/arguments 0,0,0,0 +5797000: system.cpu1: syscall getpid returns 100 +5823000: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +5823000: system.cpu0: syscall mmap returns 46912496390144 +5855000: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496519152,69376 +5855000: global: In sys_clone: +5855000: global: Flags=10f00 +5855000: global: Child stack=2aaaaab0c7f0 +5855000: global: Found unallocated thread context +5855000: system.cpu0: syscall clone returns 1 +5867500: system.cpu2: syscall getpid called w/arguments 0,0,0,0 +5867500: system.cpu2: syscall getpid returns 100 +5882000: system.cpu1: syscall arch_prctl called w/arguments 6920928,0,46912496259280,4098 +5882000: system.cpu1: syscall arch_prctl returns 0 +5893500: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +5893500: system.cpu0: syscall mmap returns 46912496521216 +5925500: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496650224,69376 +5925500: global: In sys_clone: +5925500: global: Flags=10f00 +5925500: global: Child stack=2aaaaab2c7f0 +5925500: global: Found unallocated thread context +5925500: system.cpu0: syscall clone returns 1 +5938000: system.cpu3: syscall getpid called w/arguments 0,0,0,0 +5938000: system.cpu3: syscall getpid returns 100 +5952500: system.cpu2: syscall arch_prctl called w/arguments 6920928,0,46912496390352,4098 +5952500: system.cpu2: syscall arch_prctl returns 0 +6023000: system.cpu3: syscall arch_prctl called w/arguments 6920928,0,46912496521424,4098 +6023000: system.cpu3: syscall arch_prctl returns 0 +6165500: system.cpu0: syscall futex called w/arguments 0,2,0,7012912 +6165500: global: In sys_futex: +6165500: global: Address=6b0230 +6165500: global: op=0 +6165500: global: val=2 +6165500: global: sys_futex: FUTEX_WAIT, suspending calling thread context +6165500: system.cpu0: syscall futex returns 0 +6181000: system.cpu2: syscall futex called w/arguments 0,2,0,7012912 +6181000: global: In sys_futex: +6181000: global: Address=6b0230 +6181000: global: op=0 +6181000: global: val=2 +6181000: global: sys_futex: FUTEX_WAIT, suspending calling thread context +6181000: system.cpu2: syscall futex returns 0 +6247000: system.cpu3: syscall futex called w/arguments 0,2,0,7012912 +6247000: global: In sys_futex: +6247000: global: Address=6b0230 +6247000: global: op=0 +6247000: global: val=2 +6247000: global: sys_futex: FUTEX_WAIT, suspending calling thread context +6247000: system.cpu3: syscall futex returns 0 +7505000: system.cpu1: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[1]=0x2aaaaaacd038 +7505000: system.cpu1: syscall write returns 25 +7658500: system.cpu1: syscall futex called w/arguments 6920928,1,1,7012912 +7658500: global: In sys_futex: +7658500: global: Address=6b0230 +7658500: global: op=1 +7658500: global: val=1 +7658500: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +7658500: system.cpu1: syscall futex returns 1 +9077500: system.cpu0: syscall write called w/arguments 140737488350144,25,46912496250880,1 +&local[0]=0x2aaaaaaab000 +9077500: system.cpu0: syscall write returns 25 +9231000: system.cpu0: syscall futex called w/arguments 140737488350144,1,1,7012912 +9231000: global: In sys_futex: +9231000: global: Address=6b0230 +9231000: global: op=1 +9231000: global: val=1 +9231000: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +9231000: system.cpu0: syscall futex returns 1 +10653500: system.cpu2: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[2]=0x2aaaaaaed038 +10653500: system.cpu2: syscall write returns 25 +10807000: system.cpu2: syscall futex called w/arguments 6920928,1,1,7012912 +10807000: global: In sys_futex: +10807000: global: Address=6b0230 +10807000: global: op=1 +10807000: global: val=1 +10807000: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +10807000: system.cpu2: syscall futex returns 1 +12229500: system.cpu3: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[3]=0x2aaaaab0d038 +12229500: system.cpu3: syscall write returns 25 +12383000: system.cpu3: syscall futex called w/arguments 6920928,1,1,7012912 +12383000: global: In sys_futex: +12383000: global: Address=6b0230 +12383000: global: op=1 +12383000: global: val=1 +12383000: global: sys_futex: FUTEX_WAKE, activated 0 waiting thread contexts +12383000: system.cpu3: syscall futex returns 0 +129374000: system.cpu1: syscall exit called w/arguments 46912496259280,10000,1999,0 +129374000: system.cpu1: syscall exit returns 1 +131941500: system.cpu0: syscall write called w/arguments 140737488350144,16,46912496250880,1 +local[0] = 1031 +131941500: system.cpu0: syscall write returns 16 +132522500: system.cpu2: syscall exit called w/arguments 46912496390352,10000,1999,0 +132522500: system.cpu2: syscall exit returns 1 +133485500: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[1] = 1032 +133485500: system.cpu0: syscall write returns 16 +134098500: system.cpu3: syscall exit called w/arguments 46912496521424,10000,1999,0 +134098500: system.cpu3: syscall exit returns 1 +135027000: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[2] = 1033 +135027000: system.cpu0: syscall write returns 16 +136568500: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[3] = 1034 +136568500: system.cpu0: syscall write returns 16 +137256500: system.cpu0: syscall exit_group called w/arguments 0,0,60,0 +137256500: system.cpu0: syscall exit_group returns 1 +Exiting @ tick 137256500 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-atomic-mp/stats.txt @@ -0,0 +1,592 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.000137 # Number of seconds simulated +sim_ticks 137256500 # Number of ticks simulated +final_tick 137256500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000000 # Frequency of simulated ticks +host_inst_rate 708931 # Simulator instruction rate (inst/s) +host_op_rate 1033307 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 161393741 # Simulator tick rate (ticks/s) +host_mem_usage 1193516 # Number of bytes of host memory used +host_seconds 0.85 # Real time elapsed on the host +sim_insts 602873 # Number of instructions simulated +sim_ops 878749 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 36352 # Number of bytes read from this memory +system.physmem.bytes_inst_read 22208 # Number of instructions bytes read from this memory +system.physmem.bytes_written 0 # Number of bytes written to this memory +system.physmem.num_reads 568 # Number of read requests responded to by this memory +system.physmem.num_writes 0 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 264847202 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 161799259 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_total 264847202 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 39 # Number of system calls +system.cpu0.numCycles 274614 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 159084 # Number of instructions committed +system.cpu0.committedOps 235140 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 235005 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 13206 # number of instructions that are conditional controls +system.cpu0.num_int_insts 235005 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 513523 # number of times the integer registers were read +system.cpu0.num_int_register_writes 305690 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 16913 # number of memory refs +system.cpu0.num_load_insts 13780 # Number of load instructions +system.cpu0.num_store_insts 3133 # Number of store instructions +system.cpu0.num_idle_cycles 2987.098600 # Number of idle cycles +system.cpu0.num_busy_cycles 271626.901400 # Number of busy cycles +system.cpu0.not_idle_fraction 0.989123 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0.010877 # Percentage of idle cycles +system.cpu0.icache.replacements 140 # number of replacements +system.cpu0.icache.tagsinuse 227.197033 # Cycle average of tags in use +system.cpu0.icache.total_refs 195167 # Total number of references to valid blocks. +system.cpu0.icache.sampled_refs 405 # Sample count of references to valid blocks. +system.cpu0.icache.avg_refs 481.893827 # Average number of references to valid blocks. +system.cpu0.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.icache.occ_blocks::cpu0.inst 227.197033 # Average occupied blocks per requestor +system.cpu0.icache.occ_percent::cpu0.inst 0.443744 # Average percentage of cache occupancy +system.cpu0.icache.occ_percent::total 0.443744 # Average percentage of cache occupancy +system.cpu0.icache.ReadReq_hits::cpu0.inst 195167 # number of ReadReq hits +system.cpu0.icache.ReadReq_hits::total 195167 # number of ReadReq hits +system.cpu0.icache.demand_hits::cpu0.inst 195167 # number of demand (read+write) hits +system.cpu0.icache.demand_hits::total 195167 # number of demand (read+write) hits +system.cpu0.icache.overall_hits::cpu0.inst 195167 # number of overall hits +system.cpu0.icache.overall_hits::total 195167 # number of overall hits +system.cpu0.icache.ReadReq_misses::cpu0.inst 405 # number of ReadReq misses +system.cpu0.icache.ReadReq_misses::total 405 # number of ReadReq misses +system.cpu0.icache.demand_misses::cpu0.inst 405 # number of demand (read+write) misses +system.cpu0.icache.demand_misses::total 405 # number of demand (read+write) misses +system.cpu0.icache.overall_misses::cpu0.inst 405 # number of overall misses +system.cpu0.icache.overall_misses::total 405 # number of overall misses +system.cpu0.icache.ReadReq_accesses::cpu0.inst 195572 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.ReadReq_accesses::total 195572 # number of ReadReq accesses(hits+misses) +system.cpu0.icache.demand_accesses::cpu0.inst 195572 # number of demand (read+write) accesses +system.cpu0.icache.demand_accesses::total 195572 # number of demand (read+write) accesses +system.cpu0.icache.overall_accesses::cpu0.inst 195572 # number of overall (read+write) accesses +system.cpu0.icache.overall_accesses::total 195572 # number of overall (read+write) accesses +system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.002071 # miss rate for ReadReq accesses +system.cpu0.icache.demand_miss_rate::cpu0.inst 0.002071 # miss rate for demand accesses +system.cpu0.icache.overall_miss_rate::cpu0.inst 0.002071 # miss rate for overall accesses +system.cpu0.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.icache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.icache.fast_writes 0 # number of fast writes performed +system.cpu0.icache.cache_copies 0 # number of cache copies performed +system.cpu0.icache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu0.dcache.replacements 1 # number of replacements +system.cpu0.dcache.tagsinuse 144.285415 # Cycle average of tags in use +system.cpu0.dcache.total_refs 16552 # Total number of references to valid blocks. +system.cpu0.dcache.sampled_refs 163 # Sample count of references to valid blocks. +system.cpu0.dcache.avg_refs 101.546012 # Average number of references to valid blocks. +system.cpu0.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu0.dcache.occ_blocks::cpu0.data 144.285415 # Average occupied blocks per requestor +system.cpu0.dcache.occ_percent::cpu0.data 0.281807 # Average percentage of cache occupancy +system.cpu0.dcache.occ_percent::total 0.281807 # Average percentage of cache occupancy +system.cpu0.dcache.ReadReq_hits::cpu0.data 13695 # number of ReadReq hits +system.cpu0.dcache.ReadReq_hits::total 13695 # number of ReadReq hits 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for WriteReq accesses +system.cpu0.dcache.demand_miss_rate::cpu0.data 0.011116 # miss rate for demand accesses +system.cpu0.dcache.overall_miss_rate::cpu0.data 0.011116 # miss rate for overall accesses +system.cpu0.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_mshrs 0 # number of cycles access was blocked +system.cpu0.dcache.blocked::no_targets 0 # number of cycles access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.cpu0.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.cpu0.dcache.fast_writes 0 # number of fast writes performed +system.cpu0.dcache.cache_copies 0 # number of cache copies performed +system.cpu0.dcache.no_allocate_misses 0 # Number of misses that were no-allocate +system.cpu1.numCycles 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replacements +system.cpu1.dcache.tagsinuse 34.388058 # Cycle average of tags in use +system.cpu1.dcache.total_refs 12566 # Total number of references to valid blocks. +system.cpu1.dcache.sampled_refs 33 # Sample count of references to valid blocks. +system.cpu1.dcache.avg_refs 380.787879 # Average number of references to valid blocks. +system.cpu1.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. +system.cpu1.dcache.occ_blocks::cpu1.data 34.388058 # Average occupied blocks per requestor +system.cpu1.dcache.occ_percent::cpu1.data 0.067164 # Average percentage of cache occupancy +system.cpu1.dcache.occ_percent::total 0.067164 # Average percentage of cache occupancy +system.cpu1.dcache.ReadReq_hits::cpu1.data 11401 # number of ReadReq hits +system.cpu1.dcache.ReadReq_hits::total 11401 # number of ReadReq hits +system.cpu1.dcache.WriteReq_hits::cpu1.data 1266 # number of WriteReq hits +system.cpu1.dcache.WriteReq_hits::total 1266 # number of WriteReq hits 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number of times the floating registers were written +system.cpu2.num_mem_refs 12725 # number of memory refs +system.cpu2.num_load_insts 11431 # Number of load instructions +system.cpu2.num_store_insts 1294 # Number of store instructions +system.cpu2.num_idle_cycles 26338.470679 # Number of idle cycles +system.cpu2.num_busy_cycles 238719.529321 # Number of busy cycles +system.cpu2.not_idle_fraction 0.900631 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.099369 # Percentage of idle cycles +system.cpu2.icache.replacements 6 # number of replacements +system.cpu2.icache.tagsinuse 97.342701 # Cycle average of tags in use +system.cpu2.icache.total_refs 180520 # Total number of references to valid blocks. +system.cpu2.icache.sampled_refs 110 # Sample count of references to valid blocks. +system.cpu2.icache.avg_refs 1641.090909 # Average number of references to valid blocks. +system.cpu2.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 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of ReadReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::cpu2.data 1294 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.WriteReq_accesses::total 1294 # number of WriteReq accesses(hits+misses) +system.cpu2.dcache.demand_accesses::cpu2.data 12725 # number of demand (read+write) accesses +system.cpu2.dcache.demand_accesses::total 12725 # number of demand (read+write) accesses +system.cpu2.dcache.overall_accesses::cpu2.data 12725 # number of overall (read+write) accesses +system.cpu2.dcache.overall_accesses::total 12725 # number of overall (read+write) accesses +system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.002275 # miss rate for ReadReq accesses +system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.018547 # miss rate for WriteReq accesses +system.cpu2.dcache.demand_miss_rate::cpu2.data 0.003929 # miss rate for demand accesses +system.cpu2.dcache.overall_miss_rate::cpu2.data 0.003929 # miss rate for overall accesses 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(read+write) accesses +system.l2c.ReadReq_miss_rate::cpu0.inst 0.802469 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu0.data 0.960000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.inst 0.201835 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu1.data 0.400000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu2.data 0.200000 # miss rate for ReadReq accesses +system.l2c.ReadReq_miss_rate::cpu3.data 0.200000 # miss rate for ReadReq accesses +system.l2c.ReadExReq_miss_rate::cpu0.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu1.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu2.data 1 # miss rate for ReadExReq accesses +system.l2c.ReadExReq_miss_rate::cpu3.data 1 # miss rate for ReadExReq accesses +system.l2c.demand_miss_rate::cpu0.inst 0.802469 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu0.data 0.981928 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.inst 0.201835 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu1.data 0.709677 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu2.data 0.600000 # miss rate for demand accesses +system.l2c.demand_miss_rate::cpu3.data 0.600000 # miss rate for demand accesses +system.l2c.overall_miss_rate::cpu0.inst 0.802469 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu0.data 0.981928 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.inst 0.201835 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu1.data 0.709677 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu2.data 0.600000 # miss rate for overall accesses +system.l2c.overall_miss_rate::cpu3.data 0.600000 # miss rate for overall accesses +system.l2c.blocked_cycles::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked_cycles::no_targets 0 # number of cycles access was blocked +system.l2c.blocked::no_mshrs 0 # number of cycles access was blocked +system.l2c.blocked::no_targets 0 # number of cycles access was blocked +system.l2c.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked +system.l2c.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked +system.l2c.fast_writes 0 # number of fast writes performed +system.l2c.cache_copies 0 # number of cache copies performed +system.l2c.no_allocate_misses 0 # Number of misses that were no-allocate + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/config.ini @@ -0,0 +1,690 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000 +time_sync_spin_threshold=100000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 dir_cntrl0 l1_cntrl0 l1_cntrl1 l1_cntrl2 l1_cntrl3 physmem ruby sys_port_proxy +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.sys_port_proxy.slave[0] + +[system.cpu0] +type=TimingSimpleCPU +children=dtb interrupts itb tracer workload +checker=Null +clock=1 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl0.sequencer.slave[1] +icache_port=system.l1_cntrl0.sequencer.slave[0] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[3] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl0.sequencer.slave[4] +int_slave=system.l1_cntrl0.sequencer.master[1] +pio=system.l1_cntrl0.sequencer.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl0.sequencer.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test___thread 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test___thread +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl1.sequencer.slave[1] +icache_port=system.l1_cntrl1.sequencer.slave[0] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl1.sequencer.slave[3] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl1.sequencer.slave[4] +int_slave=system.l1_cntrl1.sequencer.master[1] +pio=system.l1_cntrl1.sequencer.master[0] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl1.sequencer.slave[2] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl2.sequencer.slave[1] +icache_port=system.l1_cntrl2.sequencer.slave[0] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl2.sequencer.slave[3] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl2.sequencer.slave[4] +int_slave=system.l1_cntrl2.sequencer.master[1] +pio=system.l1_cntrl2.sequencer.master[0] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl2.sequencer.slave[2] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dtb interrupts itb tracer +checker=Null +clock=1 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.l1_cntrl3.sequencer.slave[1] +icache_port=system.l1_cntrl3.sequencer.slave[0] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl3.sequencer.slave[3] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1 +pio_addr=2305843009213693952 +pio_latency=1 +system=system +int_master=system.l1_cntrl3.sequencer.slave[4] +int_slave=system.l1_cntrl3.sequencer.master[1] +pio=system.l1_cntrl3.sequencer.master[0] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.l1_cntrl3.sequencer.slave[2] + +[system.cpu3.tracer] +type=ExeTracer + +[system.dir_cntrl0] +type=Directory_Controller +children=directory memBuffer +buffer_size=0 +cntrl_id=4 +directory=system.dir_cntrl0.directory +directory_latency=12 +memBuffer=system.dir_cntrl0.memBuffer +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +transitions_per_cycle=32 +version=0 + +[system.dir_cntrl0.directory] +type=RubyDirectoryMemory +map_levels=4 +numa_high_bit=6 +size=134217728 +use_map=false +version=0 + +[system.dir_cntrl0.memBuffer] +type=RubyMemoryControl +bank_bit_0=8 +bank_busy_time=11 +bank_queue_size=12 +banks_per_rank=8 +basic_bus_busy_time=2 +dimm_bit_0=12 +dimms_per_channel=2 +mem_bus_cycle_multiplier=10 +mem_ctl_latency=12 +mem_fixed_delay=0 +mem_random_arbitrate=0 +rank_bit_0=11 +rank_rank_delay=1 +ranks_per_dimm=2 +read_write_delay=2 +refresh_period=1560 +tFaw=0 +version=0 + +[system.l1_cntrl0] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl0.cacheMemory +cache_response_latency=12 +cntrl_id=0 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl0.sequencer +transitions_per_cycle=32 +version=0 + +[system.l1_cntrl0.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl0.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl0.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl0.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave +slave=system.cpu0.icache_port system.cpu0.dcache_port system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu0.interrupts.int_master + +[system.l1_cntrl1] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl1.cacheMemory +cache_response_latency=12 +cntrl_id=1 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl1.sequencer +transitions_per_cycle=32 +version=1 + +[system.l1_cntrl1.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl1.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl1.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl1.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=1 +master=system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave +slave=system.cpu1.icache_port system.cpu1.dcache_port system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu1.interrupts.int_master + +[system.l1_cntrl2] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl2.cacheMemory +cache_response_latency=12 +cntrl_id=2 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl2.sequencer +transitions_per_cycle=32 +version=2 + +[system.l1_cntrl2.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl2.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl2.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl2.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=2 +master=system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave +slave=system.cpu2.icache_port system.cpu2.dcache_port system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu2.interrupts.int_master + +[system.l1_cntrl3] +type=L1Cache_Controller +children=cacheMemory sequencer +buffer_size=0 +cacheMemory=system.l1_cntrl3.cacheMemory +cache_response_latency=12 +cntrl_id=3 +issue_latency=2 +number_of_TBEs=256 +recycle_latency=10 +ruby_system=system.ruby +send_evictions=false +sequencer=system.l1_cntrl3.sequencer +transitions_per_cycle=32 +version=3 + +[system.l1_cntrl3.cacheMemory] +type=RubyCache +assoc=2 +is_icache=false +latency=3 +replacement_policy=PSEUDO_LRU +size=256 +start_index_bit=6 + +[system.l1_cntrl3.sequencer] +type=RubySequencer +access_phys_mem=true +dcache=system.l1_cntrl3.cacheMemory +deadlock_threshold=500000 +icache=system.l1_cntrl3.cacheMemory +max_outstanding_requests=16 +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=3 +master=system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave +slave=system.cpu3.icache_port system.cpu3.dcache_port system.cpu3.itb.walker.port system.cpu3.dtb.walker.port system.cpu3.interrupts.int_master + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30 +latency_var=0 +null=false +range=0:134217727 +zero=false + +[system.ruby] +type=RubySystem +children=network profiler +block_size_bytes=64 +clock=1 +mem_size=134217728 +no_mem_vec=false +random_seed=1234 +randomization=false +stats_filename=ruby.stats + +[system.ruby.network] +type=SimpleNetwork +children=topology +adaptive_routing=false +buffer_size=0 +control_msg_size=8 +endpoint_bandwidth=1000 +number_of_virtual_networks=10 +ruby_system=system.ruby +topology=system.ruby.network.topology + +[system.ruby.network.topology] +type=Topology +children=ext_links0 ext_links1 ext_links2 ext_links3 ext_links4 int_links0 int_links1 int_links2 int_links3 int_links4 routers0 routers1 routers2 routers3 routers4 routers5 +description=Crossbar +ext_links=system.ruby.network.topology.ext_links0 system.ruby.network.topology.ext_links1 system.ruby.network.topology.ext_links2 system.ruby.network.topology.ext_links3 system.ruby.network.topology.ext_links4 +int_links=system.ruby.network.topology.int_links0 system.ruby.network.topology.int_links1 system.ruby.network.topology.int_links2 system.ruby.network.topology.int_links3 system.ruby.network.topology.int_links4 +print_config=false +routers=system.ruby.network.topology.routers0 system.ruby.network.topology.routers1 system.ruby.network.topology.routers2 system.ruby.network.topology.routers3 system.ruby.network.topology.routers4 system.ruby.network.topology.routers5 + +[system.ruby.network.topology.ext_links0] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl0 +int_node=system.ruby.network.topology.routers0 +latency=1 +link_id=0 +weight=1 + +[system.ruby.network.topology.ext_links1] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl1 +int_node=system.ruby.network.topology.routers1 +latency=1 +link_id=1 +weight=1 + +[system.ruby.network.topology.ext_links2] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl2 +int_node=system.ruby.network.topology.routers2 +latency=1 +link_id=2 +weight=1 + +[system.ruby.network.topology.ext_links3] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.l1_cntrl3 +int_node=system.ruby.network.topology.routers3 +latency=1 +link_id=3 +weight=1 + +[system.ruby.network.topology.ext_links4] +type=SimpleExtLink +bandwidth_factor=16 +ext_node=system.dir_cntrl0 +int_node=system.ruby.network.topology.routers4 +latency=1 +link_id=4 +weight=1 + +[system.ruby.network.topology.int_links0] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=5 +node_a=system.ruby.network.topology.routers0 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links1] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=6 +node_a=system.ruby.network.topology.routers1 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links2] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=7 +node_a=system.ruby.network.topology.routers2 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links3] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=8 +node_a=system.ruby.network.topology.routers3 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.int_links4] +type=SimpleIntLink +bandwidth_factor=16 +latency=1 +link_id=9 +node_a=system.ruby.network.topology.routers4 +node_b=system.ruby.network.topology.routers5 +weight=1 + +[system.ruby.network.topology.routers0] +type=BasicRouter +router_id=0 + +[system.ruby.network.topology.routers1] +type=BasicRouter +router_id=1 + +[system.ruby.network.topology.routers2] +type=BasicRouter +router_id=2 + +[system.ruby.network.topology.routers3] +type=BasicRouter +router_id=3 + +[system.ruby.network.topology.routers4] +type=BasicRouter +router_id=4 + +[system.ruby.network.topology.routers5] +type=BasicRouter +router_id=5 + +[system.ruby.profiler] +type=RubyProfiler +all_instructions=false +hot_lines=false +num_of_sequencers=4 +ruby_system=system.ruby + +[system.sys_port_proxy] +type=RubyPortProxy +access_phys_mem=true +ruby_system=system.ruby +support_data_reqs=true +support_inst_reqs=true +system=system +using_network_tester=false +using_ruby_tester=false +version=0 +slave=system.system_port + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/ruby.stats b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/ruby.stats --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/ruby.stats @@ -0,0 +1,409 @@ + +================ Begin RubySystem Configuration Print ================ + +RubySystem config: + random_seed: 1234 + randomization: 0 + cycle_period: 1 + block_size_bytes: 64 + block_size_bits: 6 + memory_size_bytes: 134217728 + memory_size_bits: 27 + +Network Configuration +--------------------- +network: SIMPLE_NETWORK +topology: + +virtual_net_0: active, ordered +virtual_net_1: active, ordered +virtual_net_2: active, ordered +virtual_net_3: active, ordered +virtual_net_4: active, ordered +virtual_net_5: inactive +virtual_net_6: inactive +virtual_net_7: inactive +virtual_net_8: inactive +virtual_net_9: inactive + + +Profiler Configuration +---------------------- +periodic_stats_period: 1000000 + +================ End RubySystem Configuration Print ================ + + +Real time: May/16/2012 20:10:24 + +Profiler Stats +-------------- +Elapsed_time_in_seconds: 21 +Elapsed_time_in_minutes: 0.35 +Elapsed_time_in_hours: 0.00583333 +Elapsed_time_in_days: 0.000243056 + +Virtual_time_in_seconds: 21.58 +Virtual_time_in_minutes: 0.359667 +Virtual_time_in_hours: 0.00599444 +Virtual_time_in_days: 0.000249769 + +Ruby_current_time: 6215517 +Ruby_start_time: 0 +Ruby_cycles: 6215517 + +mbytes_resident: 55.1523 +mbytes_total: 271.371 +resident_ratio: 0.203293 + +ruby_cycles_executed: [ 6215518 6215518 6215518 6215518 ] + +Busy Controller Counts: +L1Cache-0:0 L1Cache-1:0 L1Cache-2:0 L1Cache-3:0 +Directory-0:0 + + +Busy Bank Count:0 + +sequencer_requests_outstanding: [binsize: 1 max: 1 count: 1885053 average: 1 | standard deviation: 0 | 0 1885053 ] + +All Non-Zero Cycle Demand Cache Accesses +---------------------------------------- +miss_latency: [binsize: 4 max: 595 count: 1885052 average: 10.9057 | standard deviation: 19.582 | 1589085 0 0 0 0 0 0 0 0 0 0 107123 21891 131331 15752 12667 2264 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 9 9 49 41 60 2041 1492 594 34 35 72 57 33 5 6 4 6 10 5 7 5 4 4 5 3 4 3 60 108 92 11 11 10 7 9 3 1 1 1 2 5 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD: [binsize: 4 max: 595 count: 290757 average: 6.66523 | standard deviation: 17.5945 | 272898 0 0 0 0 0 0 0 0 0 0 13696 30 1 105 2156 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 9 12 24 728 649 214 12 23 24 22 13 0 2 3 3 2 3 3 4 1 2 1 1 3 1 29 35 17 3 3 5 1 4 1 1 1 0 2 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST: [binsize: 4 max: 521 count: 128349 average: 4.29773 | standard deviation: 15.3811 | 127411 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 10 12 10 394 287 98 10 5 14 13 5 4 1 0 1 3 1 0 1 2 1 2 1 1 1 10 12 16 0 2 1 1 1 0 0 0 1 0 3 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH: [binsize: 4 max: 455 count: 1465794 average: 12.3215 | standard deviation: 20.0221 | 1188666 0 0 0 0 0 0 0 0 0 0 93424 21860 131330 15647 10511 2262 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 9 29 17 26 900 543 277 12 7 33 22 15 1 3 1 2 4 1 4 0 1 1 2 1 0 1 21 61 59 8 6 4 5 4 2 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_RMW_Read: [binsize: 1 max: 175 count: 44 average: 102.727 | standard deviation: 83.9896 | 0 0 0 18 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 10 0 2 0 0 0 13 ] +miss_latency_Locked_RMW_Read: [binsize: 2 max: 216 count: 54 average: 49.8333 | standard deviation: 76.8493 | 0 38 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 5 0 0 5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Write: [binsize: 1 max: 3 count: 54 average: 3 | standard deviation: 0 | 0 0 0 54 ] +miss_latency_L1Cache: [binsize: 1 max: 3 count: 1589085 average: 3 | standard deviation: 0 | 0 0 0 1589085 ] +miss_latency_Directory: [binsize: 4 max: 595 count: 4938 average: 180.816 | standard deviation: 28.5856 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 9 49 41 60 2041 1492 594 34 35 72 57 33 5 6 4 6 10 5 7 5 4 4 5 3 4 3 60 108 92 11 11 10 7 9 3 1 1 1 2 5 1 0 1 1 1 0 0 0 1 1 1 0 1 0 1 1 1 0 0 0 1 0 0 0 1 0 1 1 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_L1Cache_wCC: [binsize: 1 max: 151 count: 291029 average: 51.1895 | standard deviation: 3.99443 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 107123 114 18743 88 2946 5 128849 9 2468 115 15521 2 114 215 11916 1 535 1 2263 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_wCC_issue_to_initial_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_initial_forward_request: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_forward_to_first_response: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +miss_latency_wCC_first_response_to_completion: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +imcomplete_wCC_Times: 291029 +miss_latency_dir_issue_to_initial_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_initial_forward_request: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_forward_to_first_response: [binsize: 1 max: 0 count: 1 average: 0 | standard deviation: 0 | 1 ] +miss_latency_dir_first_response_to_completion: [binsize: 1 max: 159 count: 1 average: 159 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +imcomplete_dir_Times: 4937 +miss_latency_LD_L1Cache: [binsize: 1 max: 3 count: 272898 average: 3 | standard deviation: 0 | 0 0 0 272898 ] +miss_latency_LD_Directory: [binsize: 4 max: 595 count: 1869 average: 179.973 | standard deviation: 25.6356 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 9 12 24 728 649 214 12 23 24 22 13 0 2 3 3 2 3 3 4 1 2 1 1 3 1 29 35 17 3 3 5 1 4 1 1 1 0 2 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_LD_L1Cache_wCC: [binsize: 1 max: 65 count: 15990 average: 48.9618 | standard deviation: 4.82346 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 13696 1 10 3 16 1 0 0 0 0 52 0 53 105 2051 0 0 1 1 ] +miss_latency_ST_L1Cache: [binsize: 1 max: 3 count: 127411 average: 3 | standard deviation: 0 | 0 0 0 127411 ] +miss_latency_ST_Directory: [binsize: 4 max: 521 count: 936 average: 180.853 | standard deviation: 32.1979 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 3 0 10 12 10 394 287 98 10 5 14 13 5 4 1 0 1 3 1 0 1 2 1 2 1 1 1 10 12 16 0 2 1 1 1 0 0 0 1 0 3 1 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_ST_L1Cache_wCC: [binsize: 1 max: 51 count: 2 average: 49 | standard deviation: 2.82843 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 ] +miss_latency_IFETCH_L1Cache: [binsize: 1 max: 3 count: 1188666 average: 3 | standard deviation: 0 | 0 0 0 1188666 ] +miss_latency_IFETCH_Directory: [binsize: 4 max: 455 count: 2093 average: 181.688 | standard deviation: 29.5739 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 9 29 17 26 900 543 277 12 7 33 22 15 1 3 1 2 4 1 4 0 1 1 2 1 0 1 21 61 59 8 6 4 5 4 2 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_IFETCH_L1Cache_wCC: [binsize: 1 max: 151 count: 275035 average: 51.319 | standard deviation: 3.90196 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 93424 113 18733 85 2929 4 128849 9 2468 115 15469 2 61 110 9865 1 535 0 2262 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ] +miss_latency_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 18 average: 3 | standard deviation: 0 | 0 0 0 18 ] +miss_latency_RMW_Read_Directory: [binsize: 1 max: 175 count: 26 average: 171.769 | standard deviation: 3.8833 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 10 0 2 0 0 0 13 ] +miss_latency_Locked_RMW_Read_L1Cache: [binsize: 1 max: 3 count: 38 average: 3 | standard deviation: 0 | 0 0 0 38 ] +miss_latency_Locked_RMW_Read_Directory: [binsize: 2 max: 216 count: 14 average: 177.357 | standard deviation: 12.3163 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 5 0 0 5 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 ] +miss_latency_Locked_RMW_Read_L1Cache_wCC: [binsize: 1 max: 47 count: 2 average: 47 | standard deviation: 0 | 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 2 ] +miss_latency_Locked_RMW_Write_L1Cache: [binsize: 1 max: 3 count: 54 average: 3 | standard deviation: 0 | 0 0 0 54 ] + +All Non-Zero Cycle SW Prefetch Requests +------------------------------------ +prefetch_latency: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +prefetch_latency_L2Miss:[binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] +Request vs. RubySystem State Profile +-------------------------------- + + +filter_action: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Message Delayed Cycles +---------------------- +Total_delay_cycles: [binsize: 1 max: 18 count: 591929 average: 2.05791 | standard deviation: 3.45148 | 406042 67 18702 82 5065 13 128855 9 2519 222 17516 2 62 111 9865 1 534 0 2262 ] +Total_nonPF_delay_cycles: [binsize: 1 max: 18 count: 591929 average: 2.05791 | standard deviation: 3.45148 | 406042 67 18702 82 5065 13 128855 9 2519 222 17516 2 62 111 9865 1 534 0 2262 ] + virtual_network_0_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_1_delay_cycles: [binsize: 1 max: 4 count: 295967 average: 0.0312298 | standard deviation: 0.350276 | 293610 0 92 1 2264 ] + virtual_network_2_delay_cycles: [binsize: 1 max: 18 count: 295962 average: 4.08463 | standard deviation: 3.93546 | 112432 67 18610 81 2801 13 128855 9 2519 222 17516 2 62 111 9865 1 534 0 2262 ] + virtual_network_3_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_4_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_5_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_6_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_7_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_8_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + virtual_network_9_delay_cycles: [binsize: 1 max: 0 count: 0 average: NaN |standard deviation: NaN | 0 ] + +Resource Usage +-------------- +page_size: 4096 +user_time: 21 +system_time: 0 +page_reclaims: 15234 +page_faults: 0 +swaps: 0 +block_inputs: 0 +block_outputs: 0 + +Network Stats +------------- + +total_msg_count_Control: 887901 7103208 +total_msg_count_Data: 14799 1065528 +total_msg_count_Response_Data: 887901 63928872 +total_msg_count_Writeback_Control: 887886 7103088 +total_msgs: 2678487 total_bytes: 79200696 + +switch_0_inlinks: 2 +switch_0_outlinks: 2 +links_utilized_percent_switch_0: 0.926029 + links_utilized_percent_switch_0_link_0: 0.926061 bw: 16000 base_latency: 1 + links_utilized_percent_switch_0_link_1: 0.925997 bw: 16000 base_latency: 1 + + outgoing_messages_switch_0_link_0_Response_Data: 11512 828864 [ 0 0 0 0 11512 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_0_Writeback_Control: 11511 92088 [ 0 0 0 11511 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Control: 11512 92096 [ 0 0 11512 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Data: 3482 250704 [ 0 0 3482 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_0_link_1_Response_Data: 8029 578088 [ 0 0 0 0 8029 0 0 0 0 0 ] base_latency: 1 + +switch_1_inlinks: 2 +switch_1_outlinks: 2 +links_utilized_percent_switch_1: 7.87541 + links_utilized_percent_switch_1_link_0: 7.87551 bw: 16000 base_latency: 1 + links_utilized_percent_switch_1_link_1: 7.87531 bw: 16000 base_latency: 1 + + outgoing_messages_switch_1_link_0_Response_Data: 97901 7048872 [ 0 0 0 0 97901 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_0_Writeback_Control: 97898 783184 [ 0 0 0 97898 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Control: 97901 783208 [ 0 0 97901 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Data: 481 34632 [ 0 0 481 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_1_link_1_Response_Data: 97417 7014024 [ 0 0 0 0 97417 0 0 0 0 0 ] base_latency: 1 + +switch_2_inlinks: 2 +switch_2_outlinks: 2 +links_utilized_percent_switch_2: 7.51888 + links_utilized_percent_switch_2_link_0: 7.51892 bw: 16000 base_latency: 1 + links_utilized_percent_switch_2_link_1: 7.51885 bw: 16000 base_latency: 1 + + outgoing_messages_switch_2_link_0_Response_Data: 93468 6729696 [ 0 0 0 0 93468 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_0_Writeback_Control: 93467 747736 [ 0 0 0 93467 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Control: 93468 747744 [ 0 0 93468 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Data: 484 34848 [ 0 0 484 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_2_link_1_Response_Data: 92983 6694776 [ 0 0 0 0 92983 0 0 0 0 0 ] base_latency: 1 + +switch_3_inlinks: 2 +switch_3_outlinks: 2 +links_utilized_percent_switch_3: 7.48819 + links_utilized_percent_switch_3_link_0: 7.48819 bw: 16000 base_latency: 1 + links_utilized_percent_switch_3_link_1: 7.48819 bw: 16000 base_latency: 1 + + outgoing_messages_switch_3_link_0_Response_Data: 93086 6702192 [ 0 0 0 0 93086 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_0_Writeback_Control: 93086 744688 [ 0 0 0 93086 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Control: 93086 744688 [ 0 0 93086 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Data: 486 34992 [ 0 0 486 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_3_link_1_Response_Data: 92600 6667200 [ 0 0 0 0 92600 0 0 0 0 0 ] base_latency: 1 + +switch_4_inlinks: 2 +switch_4_outlinks: 2 +links_utilized_percent_switch_4: 2.73818 + links_utilized_percent_switch_4_link_0: 2.73802 bw: 16000 base_latency: 1 + links_utilized_percent_switch_4_link_1: 2.73834 bw: 16000 base_latency: 1 + + outgoing_messages_switch_4_link_0_Control: 295967 2367736 [ 0 0 295967 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_0_Data: 4933 355176 [ 0 0 4933 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Response_Data: 4938 355536 [ 0 0 0 0 4938 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_4_link_1_Writeback_Control: 295962 2367696 [ 0 0 0 295962 0 0 0 0 0 0 ] base_latency: 1 + +switch_5_inlinks: 5 +switch_5_outlinks: 5 +links_utilized_percent_switch_5: 5.30934 + links_utilized_percent_switch_5_link_0: 0.926061 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_1: 7.87551 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_2: 7.51892 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_3: 7.48819 bw: 16000 base_latency: 1 + links_utilized_percent_switch_5_link_4: 2.73802 bw: 16000 base_latency: 1 + + outgoing_messages_switch_5_link_0_Response_Data: 11512 828864 [ 0 0 0 0 11512 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_0_Writeback_Control: 11511 92088 [ 0 0 0 11511 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Response_Data: 97901 7048872 [ 0 0 0 0 97901 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_1_Writeback_Control: 97898 783184 [ 0 0 0 97898 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Response_Data: 93468 6729696 [ 0 0 0 0 93468 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_2_Writeback_Control: 93467 747736 [ 0 0 0 93467 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Response_Data: 93086 6702192 [ 0 0 0 0 93086 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_3_Writeback_Control: 93086 744688 [ 0 0 0 93086 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_4_Control: 295967 2367736 [ 0 0 295967 0 0 0 0 0 0 0 ] base_latency: 1 + outgoing_messages_switch_5_link_4_Data: 4933 355176 [ 0 0 4933 0 0 0 0 0 0 0 ] base_latency: 1 + +Cache Stats: system.l1_cntrl0.cacheMemory + system.l1_cntrl0.cacheMemory_total_misses: 11512 + system.l1_cntrl0.cacheMemory_total_demand_misses: 11512 + system.l1_cntrl0.cacheMemory_total_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl0.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl0.cacheMemory_request_type_LD: 80.9937% + system.l1_cntrl0.cacheMemory_request_type_ST: 5.959% + system.l1_cntrl0.cacheMemory_request_type_IFETCH: 13.0473% + + system.l1_cntrl0.cacheMemory_access_mode_type_Supervisor: 11512 100% + + --- L1Cache --- + - Event Counts - +Load [256497 11420 11420 11420 ] 290757 +Ifetch [923912 180630 180626 180626 ] 1465794 +Store [124590 1305 1303 1303 ] 128501 +Data [11512 97901 93468 93086 ] 295967 +Fwd_GETX [8029 97417 92983 92600 ] 291029 +Inv [0 0 0 0 ] 0 +Replacement [3490 491 491 491 ] 4963 +Writeback_Ack [3479 481 484 485 ] 4929 +Writeback_Nack [3 0 0 1 ] 4 + + - Transitions - +I Load [9324 8164 183 188 ] 17859 +I Ifetch [1502 89637 93188 92801 ] 277128 +I Store [686 100 97 97 ] 980 +I Inv [0 0 0 0 ] 0 +I Replacement [8 10 7 5 ] 30 + +II Writeback_Nack [3 0 0 1 ] 4 + +M Load [247173 3256 11237 11232 ] 272898 +M Ifetch [922410 90993 87438 87825 ] 1188666 +M Store [123904 1205 1206 1206 ] 127521 +M Fwd_GETX [8026 97417 92983 92599 ] 291025 +M Inv [0 0 0 0 ] 0 +M Replacement [3482 481 484 486 ] 4933 + +MI Fwd_GETX [3 0 0 1 ] 4 +MI Inv [0 0 0 0 ] 0 +MI Writeback_Ack [3479 481 484 485 ] 4929 +MI Writeback_Nack [0 0 0 0 ] 0 + +MII Fwd_GETX [0 0 0 0 ] 0 + +IS Data [10826 97801 93371 92989 ] 294987 + +IM Data [686 100 97 97 ] 980 + +Cache Stats: system.l1_cntrl1.cacheMemory + system.l1_cntrl1.cacheMemory_total_misses: 97901 + system.l1_cntrl1.cacheMemory_total_demand_misses: 97901 + system.l1_cntrl1.cacheMemory_total_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl1.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl1.cacheMemory_request_type_LD: 8.33904% + system.l1_cntrl1.cacheMemory_request_type_ST: 0.102144% + system.l1_cntrl1.cacheMemory_request_type_IFETCH: 91.5588% + + system.l1_cntrl1.cacheMemory_access_mode_type_Supervisor: 97901 100% + +Cache Stats: system.l1_cntrl2.cacheMemory + system.l1_cntrl2.cacheMemory_total_misses: 93468 + system.l1_cntrl2.cacheMemory_total_demand_misses: 93468 + system.l1_cntrl2.cacheMemory_total_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl2.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl2.cacheMemory_request_type_LD: 0.195789% + system.l1_cntrl2.cacheMemory_request_type_ST: 0.103779% + system.l1_cntrl2.cacheMemory_request_type_IFETCH: 99.7004% + + system.l1_cntrl2.cacheMemory_access_mode_type_Supervisor: 93468 100% + +Cache Stats: system.l1_cntrl3.cacheMemory + system.l1_cntrl3.cacheMemory_total_misses: 93086 + system.l1_cntrl3.cacheMemory_total_demand_misses: 93086 + system.l1_cntrl3.cacheMemory_total_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_sw_prefetches: 0 + system.l1_cntrl3.cacheMemory_total_hw_prefetches: 0 + + system.l1_cntrl3.cacheMemory_request_type_LD: 0.201964% + system.l1_cntrl3.cacheMemory_request_type_ST: 0.104205% + system.l1_cntrl3.cacheMemory_request_type_IFETCH: 99.6938% + + system.l1_cntrl3.cacheMemory_access_mode_type_Supervisor: 93086 100% + +Memory controller: system.dir_cntrl0.memBuffer: + memory_total_requests: 9867 + memory_reads: 4938 + memory_writes: 4929 + memory_refreshes: 2093 + memory_total_request_delays: 13845 + memory_delays_per_request: 1.40316 + memory_delays_in_input_queue: 2561 + memory_delays_behind_head_of_bank_queue: 401 + memory_delays_stalled_at_head_of_bank_queue: 10883 + memory_stalls_for_bank_busy: 4314 + memory_stalls_for_random_busy: 0 + memory_stalls_for_anti_starvation: 3 + memory_stalls_for_arbitration: 657 + memory_stalls_for_bus: 5208 + memory_stalls_for_tfaw: 0 + memory_stalls_for_read_write_turnaround: 626 + memory_stalls_for_read_read_turnaround: 75 + accesses_per_bank: 462 92 212 72 94 112 136 146 294 414 252 84 237 252 456 132 741 1142 108 474 628 541 219 399 230 304 532 546 42 222 146 146 + + --- Directory --- + - Event Counts - +GETX [296030 ] 296030 +GETS [0 ] 0 +PUTX [4929 ] 4929 +PUTX_NotOwner [4 ] 4 +DMA_READ [0 ] 0 +DMA_WRITE [0 ] 0 +Memory_Data [4938 ] 4938 +Memory_Ack [4929 ] 4929 + + - Transitions - +I GETX [4938 ] 4938 +I PUTX_NotOwner [0 ] 0 +I DMA_READ [0 ] 0 +I DMA_WRITE [0 ] 0 + +M GETX [291029 ] 291029 +M PUTX [4929 ] 4929 +M PUTX_NotOwner [4 ] 4 +M DMA_READ [0 ] 0 +M DMA_WRITE [0 ] 0 + +M_DRD GETX [0 ] 0 +M_DRD PUTX [0 ] 0 + +M_DWR GETX [0 ] 0 +M_DWR PUTX [0 ] 0 + +M_DWRI GETX [0 ] 0 +M_DWRI Memory_Ack [0 ] 0 + +M_DRDI GETX [0 ] 0 +M_DRDI Memory_Ack [0 ] 0 + +IM GETX [11 ] 11 +IM GETS [0 ] 0 +IM PUTX [0 ] 0 +IM PUTX_NotOwner [0 ] 0 +IM DMA_READ [0 ] 0 +IM DMA_WRITE [0 ] 0 +IM Memory_Data [4938 ] 4938 + +MI GETX [52 ] 52 +MI GETS [0 ] 0 +MI PUTX [0 ] 0 +MI PUTX_NotOwner [0 ] 0 +MI DMA_READ [0 ] 0 +MI DMA_WRITE [0 ] 0 +MI Memory_Ack [4929 ] 4929 + +ID GETX [0 ] 0 +ID GETS [0 ] 0 +ID PUTX [0 ] 0 +ID PUTX_NotOwner [0 ] 0 +ID DMA_READ [0 ] 0 +ID DMA_WRITE [0 ] 0 +ID Memory_Data [0 ] 0 + +ID_W GETX [0 ] 0 +ID_W GETS [0 ] 0 +ID_W PUTX [0 ] 0 +ID_W PUTX_NotOwner [0 ] 0 +ID_W DMA_READ [0 ] 0 +ID_W DMA_WRITE [0 ] 0 +ID_W Memory_Ack [0 ] 0 + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simerr b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simerr @@ -0,0 +1,4 @@ +warn: Sockets disabled, not accepting gdb connections +warn: instruction 'fnstcw_Mw' unimplemented +warn: instruction 'fldcw_Mw' unimplemented +hack: be nice to actually delete the event here diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simout b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/simout @@ -0,0 +1,149 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 15:37:55 +gem5 started May 16 2012 20:10:02 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test___thread/x86/linux/simple-timing-mp-ruby -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test___thread/x86/linux/simple-timing-mp-ruby +Global frequency set at 1000000000 ticks per second + 0: system.cpu0: Constructing CPU with id 0 + 0: system.cpu1: Constructing CPU with id 1 + 0: system.cpu2: Constructing CPU with id 2 + 0: system.cpu3: Constructing CPU with id 3 +info: Entering event queue @ 0. Starting simulation... +13784: system.cpu0: syscall uname called w/arguments 4194368,0,0,140737488350144 +13784: system.cpu0: syscall uname returns 0 +19308: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +19308: system.cpu0: syscall mmap returns 46912496119808 +23532: system.cpu0: syscall arch_prctl called w/arguments 6920928,0,46912496119960,4098 +23532: system.cpu0: syscall arch_prctl returns 0 +73718: system.cpu0: syscall brk called w/arguments 6920928,131136,0,0 +73718: system.cpu0: syscall brk returns 7024640 +74678: system.cpu0: syscall brk called w/arguments 6920928,7024640,7159808,7159808 + 74678: global: Break Point changed to: 0X6D4000 +74678: system.cpu0: syscall brk returns 7159808 +172222: system.cpu0: syscall fstat called w/arguments 0,140737488347824,140737488347824,1 +172222: system.cpu0: syscall fstat returns 0 +174518: system.cpu0: syscall mmap called w/arguments 34,3,8192,0 +174518: system.cpu0: syscall mmap returns 46912496250880 +249054: system.cpu0: syscall write called w/arguments 34,22,46912496250880,1 +Starting 4 threads... +249054: system.cpu0: syscall write returns 22 +273138: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +273138: system.cpu0: syscall mmap returns 46912496259072 +275078: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496388080,69376 + 275078: global: In sys_clone: + 275078: global: Flags=10f00 + 275078: global: Child stack=2aaaaaaec7f0 + 275078: global: Found unallocated thread context +275078: system.cpu0: syscall clone returns 1 +275334: system.cpu1: syscall getpid called w/arguments 0,0,0,0 +275334: system.cpu1: syscall getpid returns 100 +276938: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +276938: system.cpu0: syscall mmap returns 46912496390144 +278928: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496519152,69376 + 278928: global: In sys_clone: + 278928: global: Flags=10f00 + 278928: global: Child stack=2aaaaab0c7f0 + 278928: global: Found unallocated thread context +278928: system.cpu0: syscall clone returns 1 +279184: system.cpu2: syscall getpid called w/arguments 0,0,0,0 +279184: system.cpu2: syscall getpid returns 100 +280750: system.cpu1: syscall arch_prctl called w/arguments 6920928,0,46912496259280,4098 +280750: system.cpu1: syscall arch_prctl returns 0 +280898: system.cpu0: syscall mmap called w/arguments 34,3,131072,0 +280898: system.cpu0: syscall mmap returns 46912496521216 +283188: system.cpu0: syscall clone called w/arguments 140737488350144,4294967295,46912496650224,69376 + 283188: global: In sys_clone: + 283188: global: Flags=10f00 + 283188: global: Child stack=2aaaaab2c7f0 + 283188: global: Found unallocated thread context +283188: system.cpu0: syscall clone returns 1 +283444: system.cpu3: syscall getpid called w/arguments 0,0,0,0 +283444: system.cpu3: syscall getpid returns 100 +285586: system.cpu2: syscall arch_prctl called w/arguments 6920928,0,46912496390352,4098 +285586: system.cpu2: syscall arch_prctl returns 0 +289792: system.cpu3: syscall arch_prctl called w/arguments 6920928,0,46912496521424,4098 +289792: system.cpu3: syscall arch_prctl returns 0 +295304: system.cpu1: syscall futex called w/arguments 0,2,0,7012912 + 295304: global: In sys_futex: + 295304: global: Address=6b0230 + 295304: global: op=0 + 295304: global: val=2 + 295304: global: sys_futex: FUTEX_WAIT, suspending calling thread context +295304: system.cpu1: syscall futex returns 0 +298400: system.cpu2: syscall futex called w/arguments 0,2,0,7012912 + 298400: global: In sys_futex: + 298400: global: Address=6b0230 + 298400: global: op=0 + 298400: global: val=2 + 298400: global: sys_futex: FUTEX_WAIT, suspending calling thread context +298400: system.cpu2: syscall futex returns 0 +302280: system.cpu3: syscall futex called w/arguments 0,2,0,7012912 + 302280: global: In sys_futex: + 302280: global: Address=6b0230 + 302280: global: op=0 + 302280: global: val=2 + 302280: global: sys_futex: FUTEX_WAIT, suspending calling thread context +302280: system.cpu3: syscall futex returns 0 +364344: system.cpu0: syscall write called w/arguments 140737488350144,25,46912496250880,1 +&local[0]=0x2aaaaaaab000 +364344: system.cpu0: syscall write returns 25 +373636: system.cpu0: syscall futex called w/arguments 140737488350144,1,1,7012912 + 373636: global: In sys_futex: + 373636: global: Address=6b0230 + 373636: global: op=1 + 373636: global: val=1 + 373636: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +373636: system.cpu0: syscall futex returns 1 +443996: system.cpu1: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[1]=0x2aaaaaacd038 +443996: system.cpu1: syscall write returns 25 +453326: system.cpu1: syscall futex called w/arguments 6920928,1,1,7012912 + 453326: global: In sys_futex: + 453326: global: Address=6b0230 + 453326: global: op=1 + 453326: global: val=1 + 453326: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +453326: system.cpu1: syscall futex returns 1 +523516: system.cpu2: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[2]=0x2aaaaaaed038 +523516: system.cpu2: syscall write returns 25 +532896: system.cpu2: syscall futex called w/arguments 6920928,1,1,7012912 + 532896: global: In sys_futex: + 532896: global: Address=6b0230 + 532896: global: op=1 + 532896: global: val=1 + 532896: global: sys_futex: FUTEX_WAKE, activated 1 waiting thread contexts +532896: system.cpu2: syscall futex returns 1 +603356: system.cpu3: syscall write called w/arguments 6920928,25,46912496250880,1 +&local[3]=0x2aaaaab0d038 +603356: system.cpu3: syscall write returns 25 +612656: system.cpu3: syscall futex called w/arguments 6920928,1,1,7012912 + 612656: global: In sys_futex: + 612656: global: Address=6b0230 + 612656: global: op=1 + 612656: global: val=1 + 612656: global: sys_futex: FUTEX_WAKE, activated 0 waiting thread contexts +612656: system.cpu3: syscall futex returns 0 +1180748: system.cpu0: syscall write called w/arguments 140737488350144,16,46912496250880,1 +local[0] = 1031 +1180748: system.cpu0: syscall write returns 16 +5759148: system.cpu2: syscall exit called w/arguments 46912496390352,10000,1999,0 +5759148: system.cpu2: syscall exit returns 1 +5825629: system.cpu3: syscall exit called w/arguments 46912496521424,10000,1999,0 +5825629: system.cpu3: syscall exit returns 1 +5943577: system.cpu1: syscall exit called w/arguments 46912496259280,10000,1999,0 +5943577: system.cpu1: syscall exit returns 1 +6012525: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[1] = 1032 +6012525: system.cpu0: syscall write returns 16 +6092215: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[2] = 1033 +6092215: system.cpu0: syscall write returns 16 +6171775: system.cpu0: syscall write called w/arguments 0,16,46912496250880,1 +local[3] = 1034 +6171775: system.cpu0: syscall write returns 16 +6215517: system.cpu0: syscall exit_group called w/arguments 0,0,60,0 +6215517: system.cpu0: syscall exit_group returns 1 +Exiting @ tick 6215517 because target called exit() diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/stats.txt --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp-ruby/stats.txt @@ -0,0 +1,114 @@ + +---------- Begin Simulation Statistics ---------- +sim_seconds 0.006216 # Number of seconds simulated +sim_ticks 6215517 # Number of ticks simulated +final_tick 6215517 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) +sim_freq 1000000000 # Frequency of simulated ticks +host_inst_rate 56470 # Simulator instruction rate (inst/s) +host_op_rate 80679 # Simulator op (including micro ops) rate (op/s) +host_tick_rate 290114 # Simulator tick rate (ticks/s) +host_mem_usage 277888 # Number of bytes of host memory used +host_seconds 21.42 # Real time elapsed on the host +sim_insts 1209844 # Number of instructions simulated +sim_ops 1728504 # Number of ops (including micro ops) simulated +system.physmem.bytes_read 12896316 # Number of bytes read from this memory +system.physmem.bytes_inst_read 11726352 # Number of instructions bytes read from this memory +system.physmem.bytes_written 520583 # Number of bytes written to this memory +system.physmem.num_reads 1756649 # Number of read requests responded to by this memory +system.physmem.num_writes 128403 # Number of write requests responded to by this memory +system.physmem.num_other 0 # Number of other requests responded to by this memory +system.physmem.bw_read 2074858133 # Total read bandwidth from this memory (bytes/s) +system.physmem.bw_inst_read 1886625360 # Instruction read bandwidth from this memory (bytes/s) +system.physmem.bw_write 83755382 # Write bandwidth from this memory (bytes/s) +system.physmem.bw_total 2158613515 # Total bandwidth to/from this memory (bytes/s) +system.cpu0.workload.num_syscalls 39 # Number of system calls +system.cpu0.numCycles 6215517 # number of cpu cycles simulated +system.cpu0.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu0.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu0.committedInsts 766035 # Number of instructions committed +system.cpu0.committedOps 1084853 # Number of ops (including micro ops) committed +system.cpu0.num_int_alu_accesses 1084722 # Number of integer alu accesses +system.cpu0.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu0.num_func_calls 0 # number of times a function call or return occured +system.cpu0.num_conditional_control_insts 134598 # number of instructions that are conditional controls +system.cpu0.num_int_insts 1084722 # number of integer instructions +system.cpu0.num_fp_insts 0 # number of float instructions +system.cpu0.num_int_register_reads 2698528 # number of times the integer registers were read +system.cpu0.num_int_register_writes 1034017 # number of times the integer registers were written +system.cpu0.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu0.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu0.num_mem_refs 381087 # number of memory refs +system.cpu0.num_load_insts 256564 # Number of load instructions +system.cpu0.num_store_insts 124523 # Number of store instructions +system.cpu0.num_idle_cycles 0 # Number of idle cycles +system.cpu0.num_busy_cycles 6215517 # Number of busy cycles +system.cpu0.not_idle_fraction 1 # Percentage of non-idle cycles +system.cpu0.idle_fraction 0 # Percentage of idle cycles +system.cpu1.numCycles 5943577 # number of cpu cycles simulated +system.cpu1.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu1.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu1.committedInsts 147939 # Number of instructions committed +system.cpu1.committedOps 214557 # Number of ops (including micro ops) committed +system.cpu1.num_int_alu_accesses 214539 # Number of integer alu accesses +system.cpu1.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu1.num_func_calls 0 # number of times a function call or return occured +system.cpu1.num_conditional_control_insts 11329 # number of instructions that are conditional controls +system.cpu1.num_int_insts 214539 # number of integer instructions +system.cpu1.num_fp_insts 0 # number of float instructions +system.cpu1.num_int_register_reads 468756 # number of times the integer registers were read +system.cpu1.num_int_register_writes 285542 # number of times the integer registers were written +system.cpu1.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu1.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu1.num_mem_refs 12725 # number of memory refs +system.cpu1.num_load_insts 11431 # Number of load instructions +system.cpu1.num_store_insts 1294 # Number of store instructions +system.cpu1.num_idle_cycles 597990.677612 # Number of idle cycles +system.cpu1.num_busy_cycles 5345586.322388 # Number of busy cycles +system.cpu1.not_idle_fraction 0.899389 # Percentage of non-idle cycles +system.cpu1.idle_fraction 0.100611 # Percentage of idle cycles +system.cpu2.numCycles 5759148 # number of cpu cycles simulated +system.cpu2.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu2.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu2.committedInsts 147935 # Number of instructions committed +system.cpu2.committedOps 214547 # Number of ops (including micro ops) committed +system.cpu2.num_int_alu_accesses 214531 # Number of integer alu accesses +system.cpu2.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu2.num_func_calls 0 # number of times a function call or return occured +system.cpu2.num_conditional_control_insts 11328 # number of instructions that are conditional controls +system.cpu2.num_int_insts 214531 # number of integer instructions +system.cpu2.num_fp_insts 0 # number of float instructions +system.cpu2.num_int_register_reads 468735 # number of times the integer registers were read +system.cpu2.num_int_register_writes 285535 # number of times the integer registers were written +system.cpu2.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu2.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu2.num_mem_refs 12723 # number of memory refs +system.cpu2.num_load_insts 11430 # Number of load instructions +system.cpu2.num_store_insts 1293 # Number of store instructions +system.cpu2.num_idle_cycles 824859.934305 # Number of idle cycles +system.cpu2.num_busy_cycles 4934288.065695 # Number of busy cycles +system.cpu2.not_idle_fraction 0.856774 # Percentage of non-idle cycles +system.cpu2.idle_fraction 0.143226 # Percentage of idle cycles +system.cpu3.numCycles 5825629 # number of cpu cycles simulated +system.cpu3.numWorkItemsStarted 0 # number of work items this cpu started +system.cpu3.numWorkItemsCompleted 0 # number of work items this cpu completed +system.cpu3.committedInsts 147935 # Number of instructions committed +system.cpu3.committedOps 214547 # Number of ops (including micro ops) committed +system.cpu3.num_int_alu_accesses 214531 # Number of integer alu accesses +system.cpu3.num_fp_alu_accesses 0 # Number of float alu accesses +system.cpu3.num_func_calls 0 # number of times a function call or return occured +system.cpu3.num_conditional_control_insts 11328 # number of instructions that are conditional controls +system.cpu3.num_int_insts 214531 # number of integer instructions +system.cpu3.num_fp_insts 0 # number of float instructions +system.cpu3.num_int_register_reads 468735 # number of times the integer registers were read +system.cpu3.num_int_register_writes 285535 # number of times the integer registers were written +system.cpu3.num_fp_register_reads 0 # number of times the floating registers were read +system.cpu3.num_fp_register_writes 0 # number of times the floating registers were written +system.cpu3.num_mem_refs 12723 # number of memory refs +system.cpu3.num_load_insts 11430 # Number of load instructions +system.cpu3.num_store_insts 1293 # Number of store instructions +system.cpu3.num_idle_cycles 847005.856615 # Number of idle cycles +system.cpu3.num_busy_cycles 4978623.143385 # Number of busy cycles +system.cpu3.not_idle_fraction 0.854607 # Percentage of non-idle cycles +system.cpu3.idle_fraction 0.145393 # Percentage of idle cycles + +---------- End Simulation Statistics ---------- diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/config.ini b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/config.ini --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/config.ini @@ -0,0 +1,563 @@ +[root] +type=Root +children=system +full_system=false +time_sync_enable=false +time_sync_period=100000000000 +time_sync_spin_threshold=100000000 + +[system] +type=System +children=cpu0 cpu1 cpu2 cpu3 l2c membus physmem toL2Bus +boot_osflags=a +init_param=0 +kernel= +load_addr_mask=1099511627775 +mem_mode=timing +memories=system.physmem +num_work_ids=16 +readfile= +symbolfile= +work_begin_ckpt_count=0 +work_begin_cpu_id_exit=-1 +work_begin_exit_count=0 +work_cpus_ckpt_count=0 +work_end_ckpt_count=0 +work_end_exit_count=0 +work_item_id=-1 +system_port=system.membus.slave[5] + +[system.cpu0] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer workload +checker=Null +clock=500 +cpu_id=0 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu0.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu0.interrupts +itb=system.cpu0.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu0.tracer +workload=system.cpu0.workload +dcache_port=system.cpu0.dcache.cpu_side +icache_port=system.cpu0.icache.cpu_side + +[system.cpu0.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.dcache_port +mem_side=system.toL2Bus.slave[1] + +[system.cpu0.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.dtb.walker + +[system.cpu0.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[3] + +[system.cpu0.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu0.icache_port +mem_side=system.toL2Bus.slave[0] + +[system.cpu0.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[1] +int_slave=system.membus.master[1] +pio=system.membus.master[0] + +[system.cpu0.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu0.itb.walker + +[system.cpu0.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[2] + +[system.cpu0.tracer] +type=ExeTracer + +[system.cpu0.workload] +type=LiveProcess +cmd=test_atomic 4 +cwd= +egid=100 +env= +errout=cerr +euid=100 +executable=/proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic +gid=100 +input=cin +max_stack_size=67108864 +output=cout +pid=100 +ppid=99 +simpoint=0 +system=system +uid=100 + +[system.cpu1] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=1 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu1.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu1.interrupts +itb=system.cpu1.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu1.tracer +workload=system.cpu0.workload +dcache_port=system.cpu1.dcache.cpu_side +icache_port=system.cpu1.icache.cpu_side + +[system.cpu1.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.dcache_port +mem_side=system.toL2Bus.slave[5] + +[system.cpu1.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.dtb.walker + +[system.cpu1.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[7] + +[system.cpu1.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu1.icache_port +mem_side=system.toL2Bus.slave[4] + +[system.cpu1.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[2] +int_slave=system.membus.master[3] +pio=system.membus.master[2] + +[system.cpu1.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu1.itb.walker + +[system.cpu1.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[6] + +[system.cpu1.tracer] +type=ExeTracer + +[system.cpu2] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=2 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu2.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu2.interrupts +itb=system.cpu2.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu2.tracer +workload=system.cpu0.workload +dcache_port=system.cpu2.dcache.cpu_side +icache_port=system.cpu2.icache.cpu_side + +[system.cpu2.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.dcache_port +mem_side=system.toL2Bus.slave[9] + +[system.cpu2.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.dtb.walker + +[system.cpu2.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[11] + +[system.cpu2.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu2.icache_port +mem_side=system.toL2Bus.slave[8] + +[system.cpu2.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[3] +int_slave=system.membus.master[5] +pio=system.membus.master[4] + +[system.cpu2.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu2.itb.walker + +[system.cpu2.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[10] + +[system.cpu2.tracer] +type=ExeTracer + +[system.cpu3] +type=TimingSimpleCPU +children=dcache dtb icache interrupts itb tracer +checker=Null +clock=500 +cpu_id=3 +defer_registration=false +do_checkpoint_insts=true +do_quiesce=true +do_statistics_insts=true +dtb=system.cpu3.dtb +function_trace=false +function_trace_start=0 +interrupts=system.cpu3.interrupts +itb=system.cpu3.itb +max_insts_all_threads=0 +max_insts_any_thread=0 +max_loads_all_threads=0 +max_loads_any_thread=0 +numThreads=1 +phase=0 +profile=0 +progress_interval=0 +system=system +tracer=system.cpu3.tracer +workload=system.cpu0.workload +dcache_port=system.cpu3.dcache.cpu_side +icache_port=system.cpu3.icache.cpu_side + +[system.cpu3.dcache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=4 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.dcache_port +mem_side=system.toL2Bus.slave[13] + +[system.cpu3.dtb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.dtb.walker + +[system.cpu3.dtb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[15] + +[system.cpu3.icache] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=1 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=true +latency=1000 +max_miss_count=0 +mshrs=4 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=32768 +subblock_size=0 +system=system +tgts_per_mshr=8 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.cpu3.icache_port +mem_side=system.toL2Bus.slave[12] + +[system.cpu3.interrupts] +type=X86LocalApic +int_latency=1000 +pio_addr=2305843009213693952 +pio_latency=1000 +system=system +int_master=system.membus.slave[4] +int_slave=system.membus.master[7] +pio=system.membus.master[6] + +[system.cpu3.itb] +type=X86TLB +children=walker +size=64 +walker=system.cpu3.itb.walker + +[system.cpu3.itb.walker] +type=X86PagetableWalker +system=system +port=system.toL2Bus.slave[14] + +[system.cpu3.tracer] +type=ExeTracer + +[system.l2c] +type=BaseCache +addr_ranges=0:18446744073709551615 +assoc=8 +block_size=64 +forward_snoops=true +hash_delay=1 +is_top_level=false +latency=10000 +max_miss_count=0 +mshrs=92 +prefetch_on_access=false +prefetcher=Null +prioritizeRequests=false +repl=Null +size=4194304 +subblock_size=0 +system=system +tgts_per_mshr=16 +trace_addr=0 +two_queue=false +write_buffers=8 +cpu_side=system.toL2Bus.master[0] +mem_side=system.membus.slave[0] + +[system.membus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.cpu0.interrupts.pio system.cpu0.interrupts.int_slave system.cpu1.interrupts.pio system.cpu1.interrupts.int_slave system.cpu2.interrupts.pio system.cpu2.interrupts.int_slave system.cpu3.interrupts.pio system.cpu3.interrupts.int_slave system.physmem.port[0] +slave=system.l2c.mem_side system.cpu0.interrupts.int_master system.cpu1.interrupts.int_master system.cpu2.interrupts.int_master system.cpu3.interrupts.int_master system.system_port + +[system.physmem] +type=SimpleMemory +conf_table_reported=false +file= +in_addr_map=true +latency=30000 +latency_var=0 +null=false +range=0:134217727 +zero=false +port=system.membus.master[8] + +[system.toL2Bus] +type=Bus +block_size=64 +bus_id=0 +clock=1000 +header_cycles=1 +use_default_range=false +width=64 +master=system.l2c.cpu_side +slave=system.cpu0.icache.mem_side system.cpu0.dcache.mem_side system.cpu0.itb.walker.port system.cpu0.dtb.walker.port system.cpu1.icache.mem_side system.cpu1.dcache.mem_side system.cpu1.itb.walker.port system.cpu1.dtb.walker.port system.cpu2.icache.mem_side system.cpu2.dcache.mem_side system.cpu2.itb.walker.port system.cpu2.dtb.walker.port system.cpu3.icache.mem_side system.cpu3.dcache.mem_side system.cpu3.itb.walker.port system.cpu3.dtb.walker.port + diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simerr b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simerr --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simerr @@ -0,0 +1,4 @@ +fatal: Can't load object file /proj/aatl_perfmod_arch/m5_system_files/regression/test-progs/m5threads/bin/x86/linux/test_atomic + @ cycle 0 +[create:build/X86/sim/process.cc, line 608] +Memory Usage: 251964 KBytes diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simout b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simout --- /dev/null +++ b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/simout @@ -0,0 +1,8 @@ +gem5 Simulator System. http://gem5.org +gem5 is copyrighted software; use the --copyright option for details. + +gem5 compiled May 16 2012 10:54:19 +gem5 started May 16 2012 14:10:27 +gem5 executing on SC2B0617 +command line: build/X86/gem5.opt -d build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp -re tests/run.py build/X86/tests/opt/quick/se/40.m5threads-test-atomic/x86/linux/simple-timing-mp +Global frequency set at 1000000000000 ticks per second diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/skip b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/skip diff --git a/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/stats.txt b/tests/quick/se/40.m5threads-test___thread/ref/x86/linux/simple-timing-mp/stats.txt