diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/alpha/decoder.hh --- a/src/arch/alpha/decoder.hh Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/alpha/decoder.hh Mon May 28 00:49:27 2012 -0700 @@ -50,8 +50,11 @@ ExtMachInst ext_inst; bool instDone; + int fullSystem; + public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) + Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), + fullSystem(FullSystem ? 1 : 0) {} ThreadContext * @@ -101,7 +104,8 @@ protected: /// A cache of decoded instruction objects. - static GenericISA::BasicDecodeCache defaultCache; + static GenericISA::BasicDecodeCache fsCache; + static GenericISA::BasicDecodeCache seCache; public: StaticInstPtr decodeInst(ExtMachInst mach_inst); @@ -112,7 +116,10 @@ StaticInstPtr decode(ExtMachInst mach_inst, Addr addr) { - return defaultCache.decode(this, mach_inst, addr); + if (fullSystem) + return fsCache.decode(this, mach_inst, addr); + else + return seCache.decode(this, mach_inst, addr); } StaticInstPtr diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/alpha/decoder.cc --- a/src/arch/alpha/decoder.cc Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/alpha/decoder.cc Mon May 28 00:49:27 2012 -0700 @@ -33,6 +33,7 @@ namespace AlphaISA { -GenericISA::BasicDecodeCache Decoder::defaultCache; +GenericISA::BasicDecodeCache Decoder::fsCache; +GenericISA::BasicDecodeCache Decoder::seCache; } diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/alpha/isa/decoder.isa --- a/src/arch/alpha/isa/decoder.isa Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/alpha/isa/decoder.isa Mon May 28 00:49:27 2012 -0700 @@ -805,14 +805,14 @@ 0x4400: wmb({{ }}, IsWriteBarrier, MemWriteOp); } - 0xe000: decode FullSystemInt { + 0xe000: decode fullSystem { 0: FailUnimpl::rc_se(); default: BasicOperate::rc({{ Ra = IntrFlag; IntrFlag = 0; }}, IsNonSpeculative, IsUnverifiable); } - 0xf000: decode FullSystemInt { + 0xf000: decode fullSystem { 0: FailUnimpl::rs_se(); default: BasicOperate::rs({{ Ra = IntrFlag; @@ -821,7 +821,7 @@ } } - 0x00: decode FullSystemInt { + 0x00: decode fullSystem { 0: decode PALFUNC { format EmulatedCallPal { 0x00: halt ({{ diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/mips/decoder.hh --- a/src/arch/mips/decoder.hh Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/mips/decoder.hh Mon May 28 00:49:27 2012 -0700 @@ -36,6 +36,7 @@ #include "base/misc.hh" #include "base/types.hh" #include "cpu/static_inst.hh" +#include "sim/full_system.hh" class ThreadContext; @@ -50,8 +51,11 @@ ExtMachInst emi; bool instDone; + int fullSystem; + public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) + Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), + fullSystem(FullSystem ? 1 : 0) {} ThreadContext *getTC() @@ -99,7 +103,8 @@ protected: /// A cache of decoded instruction objects. - static GenericISA::BasicDecodeCache defaultCache; + static GenericISA::BasicDecodeCache fsCache; + static GenericISA::BasicDecodeCache seCache; public: StaticInstPtr decodeInst(ExtMachInst mach_inst); @@ -110,7 +115,10 @@ StaticInstPtr decode(ExtMachInst mach_inst, Addr addr) { - return defaultCache.decode(this, mach_inst, addr); + if (fullSystem) + return fsCache.decode(this, mach_inst, addr); + else + return seCache.decode(this, mach_inst, addr); } StaticInstPtr diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/mips/decoder.cc --- a/src/arch/mips/decoder.cc Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/mips/decoder.cc Mon May 28 00:49:27 2012 -0700 @@ -33,6 +33,7 @@ namespace MipsISA { -GenericISA::BasicDecodeCache Decoder::defaultCache; +GenericISA::BasicDecodeCache Decoder::seCache; +GenericISA::BasicDecodeCache Decoder::fsCache; } diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/mips/isa/decoder.isa --- a/src/arch/mips/isa/decoder.isa Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/mips/isa/decoder.isa Mon May 28 00:49:27 2012 -0700 @@ -163,7 +163,7 @@ format BasicOp { 0x2: movz({{ Rd = (Rt == 0) ? Rs : Rd; }}); 0x3: movn({{ Rd = (Rt != 0) ? Rs : Rd; }}); - 0x4: decode FullSystemInt { + 0x4: decode fullSystem { 0: syscall_se({{ xc->syscall(R2); }}, IsSerializeAfter, IsNonSpeculative); default: syscall({{ fault = new SystemCallFault(); }}); @@ -2431,7 +2431,7 @@ } } 0x3: decode OP default FailUnimpl::rdhwr() { - 0x0: decode FullSystemInt { + 0x0: decode fullSystem { 0: decode RD { 29: BasicOp::rdhwr_se({{ Rt = TpValue; }}); } diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/x86/decoder.hh --- a/src/arch/x86/decoder.hh Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/x86/decoder.hh Mon May 28 00:49:27 2012 -0700 @@ -95,6 +95,8 @@ uint8_t defAddr; uint8_t stack; + int fullSystem; + uint8_t getNextByte() { return ((uint8_t *)&fetchChunk)[offset]; @@ -191,24 +193,48 @@ State doDisplacementState(); State doImmediateState(); - protected: /// Caching for decoded instruction objects. - typedef MiscReg CacheKey; + public: + struct CacheKey + { + MiscReg m5Reg; + int fs; + CacheKey(const CacheKey &other) : m5Reg(other.m5Reg), fs(other.fs) + {} + CacheKey(MiscReg _m5Reg, bool _fs) : m5Reg(_m5Reg), fs(_fs ? 1 : 0) + {} + bool + operator == (const CacheKey &other) const + { + return m5Reg == other.m5Reg && fs == other.fs; + } + }; + + struct CacheKeyHasher + { + size_t operator()(const CacheKey &key) const + { + return key.m5Reg ^ key.fs; + } + }; + + protected: typedef DecodeCache::AddrMap DecodePages; DecodePages *decodePages; - typedef m5::hash_map AddrCacheMap; + typedef m5::hash_map AddrCacheMap; AddrCacheMap addrCacheMap; DecodeCache::InstMap *instMap; - typedef m5::hash_map InstCacheMap; + typedef m5::hash_map InstCacheMap; static InstCacheMap instCacheMap; public: Decoder(ThreadContext * _tc) : tc(_tc), basePC(0), origPC(0), offset(0), - outOfBytes(true), instDone(false), + fullSystem(false), outOfBytes(true), instDone(false), state(ResetState) { mode = LongMode; @@ -225,7 +251,7 @@ instMap = NULL; } - void setM5Reg(HandyM5Reg m5Reg) + void setContext(HandyM5Reg m5Reg, bool fs) { mode = (X86Mode)(uint64_t)m5Reg.mode; submode = (X86SubMode)(uint64_t)m5Reg.submode; @@ -237,20 +263,24 @@ defAddr = m5Reg.defAddr; stack = m5Reg.stack; - AddrCacheMap::iterator amIter = addrCacheMap.find(m5Reg); + fullSystem = fs ? 1 : 0; + + CacheKey key(m5Reg, fs); + + AddrCacheMap::iterator amIter = addrCacheMap.find(key); if (amIter != addrCacheMap.end()) { decodePages = amIter->second; } else { decodePages = new DecodePages; - addrCacheMap[m5Reg] = decodePages; + addrCacheMap[key] = decodePages; } - InstCacheMap::iterator imIter = instCacheMap.find(m5Reg); + InstCacheMap::iterator imIter = instCacheMap.find(key); if (imIter != instCacheMap.end()) { instMap = imIter->second; } else { instMap = new DecodeCache::InstMap; - instCacheMap[m5Reg] = instMap; + instCacheMap[key] = instMap; } } diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/x86/isa.cc --- a/src/arch/x86/isa.cc Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/x86/isa.cc Mon May 28 00:49:27 2012 -0700 @@ -33,6 +33,7 @@ #include "arch/x86/tlb.hh" #include "cpu/base.hh" #include "cpu/thread_context.hh" +#include "sim/full_system.hh" #include "sim/serialize.hh" namespace X86ISA @@ -97,7 +98,7 @@ regVal[MISCREG_M5_REG] = m5reg; if (tc) - tc->getDecoderPtr()->setM5Reg(m5reg); + tc->getDecoderPtr()->setContext(m5reg, FullSystem); } void diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/x86/isa/decoder/one_byte_opcodes.isa --- a/src/arch/x86/isa/decoder/one_byte_opcodes.isa Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/x86/isa/decoder/one_byte_opcodes.isa Mon May 28 00:49:27 2012 -0700 @@ -394,7 +394,7 @@ default: Inst::RET_FAR(); } 0x4: int3(); - 0x5: decode FullSystemInt default int_Ib() { + 0x5: decode fullSystem default int_Ib() { 0: decode IMMEDIATE { // Really only the LSB matters, but the decoder // will sign extend it, and there's no easy way to diff -r 8327d2fbfc37 -r 674d25baca5e src/arch/x86/isa/decoder/two_byte_opcodes.isa --- a/src/arch/x86/isa/decoder/two_byte_opcodes.isa Sun May 27 20:56:25 2012 -0700 +++ b/src/arch/x86/isa/decoder/two_byte_opcodes.isa Mon May 28 00:49:27 2012 -0700 @@ -216,7 +216,7 @@ default: Inst::UD2(); } } - 0x05: decode FullSystemInt { + 0x05: decode fullSystem { 0: SyscallInst::syscall('xc->syscall(Rax)', IsSyscall, IsNonSpeculative, IsSerializeAfter); default: decode MODE_MODE { @@ -398,7 +398,7 @@ 0x1: Inst::RDTSC(); 0x2: Inst::RDMSR(); 0x3: rdpmc(); - 0x4: decode FullSystemInt { + 0x4: decode fullSystem { 0: SyscallInst::sysenter('xc->syscall(Rax)', IsSyscall, IsNonSpeculative, IsSerializeAfter); default: sysenter(); diff -r 8327d2fbfc37 -r 674d25baca5e src/sim/full_system.hh --- a/src/sim/full_system.hh Sun May 27 20:56:25 2012 -0700 +++ b/src/sim/full_system.hh Mon May 28 00:49:27 2012 -0700 @@ -37,12 +37,4 @@ */ extern bool FullSystem; -/** - * In addition to the boolean flag we make use of an unsigned int - * since the CPU instruction decoder makes use of the variable in - * switch statements. A value of 0 signifies syscall emulation, and - * any other value full system. - */ -extern unsigned int FullSystemInt; - #endif // __SIM_FULL_SYSTEM_HH__ diff -r 8327d2fbfc37 -r 674d25baca5e src/sim/root.cc --- a/src/sim/root.cc Sun May 27 20:56:25 2012 -0700 +++ b/src/sim/root.cc Mon May 28 00:49:27 2012 -0700 @@ -125,7 +125,6 @@ } bool FullSystem; -unsigned int FullSystemInt; Root * RootParams::create() @@ -137,7 +136,6 @@ created = true; FullSystem = full_system; - FullSystemInt = full_system ? 1 : 0; return new Root(this); }