diff -r 7952cc909c71 -r 32e79a6e194b src/arch/sparc/decoder.hh
--- a/src/arch/sparc/decoder.hh	Mon May 28 00:52:42 2012 -0700
+++ b/src/arch/sparc/decoder.hh	Mon May 28 01:38:45 2012 -0700
@@ -50,8 +50,10 @@
     ExtMachInst emi;
     bool instDone;
 
+    MiscReg asi;
+
   public:
-    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false)
+    Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0)
     {}
 
     ThreadContext *
@@ -86,8 +88,7 @@
         // into all the execute functions
         if (inst & (1 << 13)) {
             emi |= (static_cast<ExtMachInst>(
-                        tc->readMiscRegNoEffect(MISCREG_ASI))
-                    << (sizeof(MachInst) * 8));
+                        asi << (sizeof(MachInst) * 8)));
         } else {
             emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
                     << (sizeof(MachInst) * 8));
@@ -107,6 +108,12 @@
         return instDone;
     }
 
+    void
+    setContext(MiscReg _asi)
+    {
+        asi = _asi;
+    }
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;
diff -r 7952cc909c71 -r 32e79a6e194b src/arch/sparc/isa.cc
--- a/src/arch/sparc/isa.cc	Mon May 28 00:52:42 2012 -0700
+++ b/src/arch/sparc/isa.cc	Mon May 28 01:38:45 2012 -0700
@@ -549,6 +549,9 @@
     MiscReg new_val = val;
 
     switch (miscReg) {
+      case MISCREG_ASI:
+        tc->getDecodePtr()->setContext(val);
+        break;
       case MISCREG_STICK:
       case MISCREG_TICK:
         // stick and tick are same thing on niagra
diff -r 7952cc909c71 -r 32e79a6e194b src/arch/sparc/process.cc
--- a/src/arch/sparc/process.cc	Mon May 28 00:52:42 2012 -0700
+++ b/src/arch/sparc/process.cc	Mon May 28 01:38:45 2012 -0700
@@ -145,7 +145,7 @@
     // Set the trap level to 0
     tc->setMiscRegNoEffect(MISCREG_TL, 0);
     // Set the ASI register to something fixed
-    tc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+    tc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
 
     /*
      * T1 specific registers
diff -r 7952cc909c71 -r 32e79a6e194b src/arch/sparc/utility.cc
--- a/src/arch/sparc/utility.cc	Mon May 28 00:52:42 2012 -0700
+++ b/src/arch/sparc/utility.cc	Mon May 28 01:38:45 2012 -0700
@@ -94,7 +94,7 @@
 //            src->readMiscRegNoEffect(MISCREG_Y));
 //    dest->setMiscRegNoEffect(MISCREG_CCR,
 //            src->readMiscRegNoEffect(MISCREG_CCR));
-    dest->setMiscRegNoEffect(MISCREG_ASI,
+    dest->setMiscReg(MISCREG_ASI,
             src->readMiscRegNoEffect(MISCREG_ASI));
     dest->setMiscRegNoEffect(MISCREG_TICK,
             src->readMiscRegNoEffect(MISCREG_TICK));
diff -r 7952cc909c71 -r 32e79a6e194b src/sim/syscall_emul.cc
--- a/src/sim/syscall_emul.cc	Mon May 28 00:52:42 2012 -0700
+++ b/src/sim/syscall_emul.cc	Mon May 28 01:38:45 2012 -0700
@@ -810,7 +810,7 @@
             ctc->setMiscReg(MISCREG_CWP, 0);
             ctc->setIntReg(NumIntArchRegs + 7, 0);
             ctc->setMiscRegNoEffect(MISCREG_TL, 0);
-            ctc->setMiscRegNoEffect(MISCREG_ASI, ASI_PRIMARY);
+            ctc->setMiscReg(MISCREG_ASI, ASI_PRIMARY);
 
             for (int y = 8; y < 32; y++)
                 ctc->setIntReg(y, tc->readIntReg(y));