diff -r 32e79a6e194b -r a43d6b23beec src/arch/arm/decoder.hh
--- a/src/arch/arm/decoder.hh	Mon May 28 01:38:45 2012 -0700
+++ b/src/arch/arm/decoder.hh	Mon May 28 02:55:47 2012 -0700
@@ -58,6 +58,9 @@
     bool foundIt;
     ITSTATE itBits;
 
+    int fpscrLen;
+    int fpscrStride;
+
   public:
     void reset()
     {
@@ -69,7 +72,8 @@
         foundIt = false;
     }
 
-    Decoder(ThreadContext * _tc) : tc(_tc), data(0)
+    Decoder(ThreadContext * _tc) : tc(_tc), data(0),
+        fpscrLen(0), fpscrStride(0)
     {
         reset();
     }
@@ -121,6 +125,12 @@
         return (!emi.thumb || emi.bigThumb) ? 4 : 2;
     }
 
+    void setContext(FPSCR fpscr)
+    {
+        fpscrLen = fpscr.len;
+        fpscrStride = fpscr.stride;
+    }
+
   protected:
     /// A cache of decoded instruction objects.
     static GenericISA::BasicDecodeCache defaultCache;
diff -r 32e79a6e194b -r a43d6b23beec src/arch/arm/decoder.cc
--- a/src/arch/arm/decoder.cc	Mon May 28 01:38:45 2012 -0700
+++ b/src/arch/arm/decoder.cc	Mon May 28 02:55:47 2012 -0700
@@ -113,9 +113,8 @@
     data = inst;
     offset = (fetchPC >= pc.instAddr()) ? 0 : pc.instAddr() - fetchPC;
     emi.thumb = pc.thumb();
-    FPSCR fpscr = tc->readMiscReg(MISCREG_FPSCR);
-    emi.fpscrLen = fpscr.len;
-    emi.fpscrStride = fpscr.stride;
+    emi.fpscrLen = fpscrLen;
+    emi.fpscrStride = fpscrStride;
 
     outOfBytes = false;
     process();
diff -r 32e79a6e194b -r a43d6b23beec src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc	Mon May 28 01:38:45 2012 -0700
+++ b/src/arch/arm/isa.cc	Mon May 28 02:55:47 2012 -0700
@@ -346,6 +346,7 @@
                 fpscrMask.n = ones;
                 newVal = (newVal & (uint32_t)fpscrMask) |
                          (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask);
+                tc->getDecodePtr()->setContext(newVal);
             }
             break;
           case MISCREG_CPSR_Q:
diff -r 32e79a6e194b -r a43d6b23beec src/arch/arm/remote_gdb.cc
--- a/src/arch/arm/remote_gdb.cc	Mon May 28 01:38:45 2012 -0700
+++ b/src/arch/arm/remote_gdb.cc	Mon May 28 02:55:47 2012 -0700
@@ -293,7 +293,7 @@
     }
 
     //FPSCR
-    context->setMiscRegNoEffect(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
+    context->setMiscReg(MISCREG_FPSCR, gdbregs.regs[REG_FPSCR]>>32);
 }
 
 void