diff -r 09f89794d79f -r d8e7ce211541 src/arch/alpha/decoder.hh --- a/src/arch/alpha/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/alpha/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -36,16 +36,12 @@ #include "cpu/static_inst.hh" #include "sim/full_system.hh" -class ThreadContext; - namespace AlphaISA { class Decoder { protected: - ThreadContext *tc; - // The extended machine instruction being generated ExtMachInst ext_inst; bool instDone; @@ -53,22 +49,9 @@ int fullSystem; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), - fullSystem(FullSystem ? 1 : 0) + Decoder() : instDone(false), fullSystem(FullSystem ? 1 : 0) {} - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process() { } diff -r 09f89794d79f -r d8e7ce211541 src/arch/arm/decoder.hh --- a/src/arch/arm/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/arm/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -39,15 +39,12 @@ #include "base/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace ArmISA { class Decoder { protected: - ThreadContext * tc; //The extended machine instruction being generated ExtMachInst emi; MachInst data; @@ -72,23 +69,11 @@ foundIt = false; } - Decoder(ThreadContext * _tc) : tc(_tc), data(0), - fpscrLen(0), fpscrStride(0) + Decoder() : data(0), fpscrLen(0), fpscrStride(0) { reset(); } - ThreadContext * getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process(); //Use this to give data to the decoder. This should be used diff -r 09f89794d79f -r d8e7ce211541 src/arch/arm/decoder.cc --- a/src/arch/arm/decoder.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/arm/decoder.cc Mon May 28 14:20:21 2012 -0700 @@ -32,7 +32,6 @@ #include "arch/arm/isa_traits.hh" #include "arch/arm/utility.hh" #include "base/trace.hh" -#include "cpu/thread_context.hh" #include "debug/Decoder.hh" namespace ArmISA diff -r 09f89794d79f -r d8e7ce211541 src/arch/arm/isa.cc --- a/src/arch/arm/isa.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/arm/isa.cc Mon May 28 14:20:21 2012 -0700 @@ -346,7 +346,7 @@ fpscrMask.n = ones; newVal = (newVal & (uint32_t)fpscrMask) | (miscRegs[MISCREG_FPSCR] & ~(uint32_t)fpscrMask); - tc->getDecodePtr()->setContext(newVal); + tc->getDecoderPtr()->setContext(newVal); } break; case MISCREG_CPSR_Q: diff -r 09f89794d79f -r d8e7ce211541 src/arch/mips/decoder.hh --- a/src/arch/mips/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/mips/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -38,15 +38,12 @@ #include "cpu/static_inst.hh" #include "sim/full_system.hh" -class ThreadContext; - namespace MipsISA { class Decoder { protected: - ThreadContext * tc; //The extended machine instruction being generated ExtMachInst emi; bool instDone; @@ -54,21 +51,9 @@ int fullSystem; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), - fullSystem(FullSystem ? 1 : 0) + Decoder() : instDone(false), fullSystem(FullSystem ? 1 : 0) {} - ThreadContext *getTC() - { - return tc; - } - - void - setTC(ThreadContext *_tc) - { - tc = _tc; - } - void process() { diff -r 09f89794d79f -r d8e7ce211541 src/arch/power/decoder.hh --- a/src/arch/power/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/power/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -35,36 +35,19 @@ #include "arch/types.hh" #include "cpu/static_inst.hh" -class ThreadContext; - namespace PowerISA { class Decoder { protected: - ThreadContext * tc; - // The extended machine instruction being generated ExtMachInst emi; bool instDone; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false) - { - } - - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } + Decoder() : instDone(false) + {} void process() diff -r 09f89794d79f -r d8e7ce211541 src/arch/sparc/decoder.hh --- a/src/arch/sparc/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/sparc/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -35,9 +35,6 @@ #include "arch/sparc/registers.hh" #include "arch/types.hh" #include "cpu/static_inst.hh" -#include "cpu/thread_context.hh" - -class ThreadContext; namespace SparcISA { @@ -45,7 +42,6 @@ class Decoder { protected: - ThreadContext * tc; // The extended machine instruction being generated ExtMachInst emi; bool instDone; @@ -53,21 +49,9 @@ MiscReg asi; public: - Decoder(ThreadContext * _tc) : tc(_tc), instDone(false), asi(0) + Decoder() : instDone(false), asi(0) {} - ThreadContext * - getTC() - { - return tc; - } - - void - setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process() {} void diff -r 09f89794d79f -r d8e7ce211541 src/arch/sparc/isa.cc --- a/src/arch/sparc/isa.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/sparc/isa.cc Mon May 28 14:20:21 2012 -0700 @@ -29,6 +29,7 @@ */ #include "arch/sparc/asi.hh" +#include "arch/sparc/decoder.hh" #include "arch/sparc/isa.hh" #include "base/bitfield.hh" #include "base/trace.hh" @@ -550,7 +551,7 @@ switch (miscReg) { case MISCREG_ASI: - tc->getDecodePtr()->setContext(val); + tc->getDecoderPtr()->setContext(val); break; case MISCREG_STICK: case MISCREG_TICK: diff -r 09f89794d79f -r d8e7ce211541 src/arch/x86/decoder.hh --- a/src/arch/x86/decoder.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/x86/decoder.hh Mon May 28 14:20:21 2012 -0700 @@ -44,8 +44,6 @@ #include "cpu/static_inst.hh" #include "debug/Decoder.hh" -class ThreadContext; - namespace X86ISA { @@ -73,7 +71,6 @@ static InstBytes dummy; - ThreadContext * tc; //The bytes to be predecoded MachInst fetchChunk; InstBytes *instBytes; @@ -232,8 +229,7 @@ static InstCacheMap instCacheMap; public: - Decoder(ThreadContext * _tc) : - tc(_tc), basePC(0), origPC(0), offset(0), + Decoder() : basePC(0), origPC(0), offset(0), fullSystem(false), outOfBytes(true), instDone(false), state(ResetState) { @@ -289,16 +285,6 @@ state = ResetState; } - ThreadContext * getTC() - { - return tc; - } - - void setTC(ThreadContext * _tc) - { - tc = _tc; - } - void process(); //Use this to give data to the decoder. This should be used diff -r 09f89794d79f -r d8e7ce211541 src/arch/x86/decoder.cc --- a/src/arch/x86/decoder.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/arch/x86/decoder.cc Mon May 28 14:20:21 2012 -0700 @@ -33,7 +33,6 @@ #include "base/misc.hh" #include "base/trace.hh" #include "base/types.hh" -#include "cpu/thread_context.hh" #include "debug/Decoder.hh" namespace X86ISA diff -r 09f89794d79f -r d8e7ce211541 src/cpu/checker/cpu_impl.hh --- a/src/cpu/checker/cpu_impl.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/checker/cpu_impl.hh Mon May 28 14:20:21 2012 -0700 @@ -306,7 +306,6 @@ StaticInstPtr instPtr = NULL; //Predecode, ie bundle up an ExtMachInst - thread->decoder.setTC(thread->getTC()); //If more fetch data is needed, pass it in. Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; thread->decoder.moreBytes(pcState, fetchPC, machInst); diff -r 09f89794d79f -r d8e7ce211541 src/cpu/inorder/resources/fetch_unit.cc --- a/src/cpu/inorder/resources/fetch_unit.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/inorder/resources/fetch_unit.cc Mon May 28 14:20:21 2012 -0700 @@ -59,7 +59,7 @@ instSize(sizeof(TheISA::MachInst)), fetchBuffSize(params->fetchBuffSize) { for (int tid = 0; tid < MaxThreads; tid++) - decoder[tid] = new Decoder(NULL); + decoder[tid] = new Decoder; } FetchUnit::~FetchUnit() @@ -109,7 +109,6 @@ MachInst mach_inst = TheISA::gtoh(fetchInsts[fetch_offset]); - decoder[tid]->setTC(cpu->thread[tid]->getTC()); decoder[tid]->moreBytes(instPC, inst->instAddr(), mach_inst); assert(decoder[tid]->instReady()); inst->setStaticInst(decoder[tid]->decode(instPC)); diff -r 09f89794d79f -r d8e7ce211541 src/cpu/legiontrace.cc --- a/src/cpu/legiontrace.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/legiontrace.cc Mon May 28 14:20:21 2012 -0700 @@ -422,7 +422,6 @@ << endl; TheISA::Decoder *decoder = thread->getDecoderPtr(); - decoder->setTC(thread); decoder->moreBytes(m5Pc, m5Pc, shared_data->instruction); assert(decoder->instReady()); diff -r 09f89794d79f -r d8e7ce211541 src/cpu/o3/fetch_impl.hh --- a/src/cpu/o3/fetch_impl.hh Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/o3/fetch_impl.hh Mon May 28 14:20:21 2012 -0700 @@ -133,7 +133,7 @@ instSize = sizeof(TheISA::MachInst); for (int i = 0; i < Impl::MaxThreads; i++) - decoder[i] = new TheISA::Decoder(NULL); + decoder[i] = new TheISA::Decoder; } template @@ -1225,7 +1225,6 @@ } MachInst inst = TheISA::gtoh(cacheInsts[blkOffset]); - decoder[tid]->setTC(cpu->thread[tid]->getTC()); decoder[tid]->moreBytes(thisPC, fetchAddr, inst); if (decoder[tid]->needMoreBytes()) { diff -r 09f89794d79f -r d8e7ce211541 src/cpu/simple/base.cc --- a/src/cpu/simple/base.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/simple/base.cc Mon May 28 14:20:21 2012 -0700 @@ -381,8 +381,6 @@ TheISA::Decoder *decoder = &(thread->decoder); //Predecode, ie bundle up an ExtMachInst - //This should go away once the constructor can be set up properly - decoder->setTC(thread->getTC()); //If more fetch data is needed, pass it in. Addr fetchPC = (pcState.instAddr() & PCMask) + fetchOffset; //if(decoder->needMoreBytes()) diff -r 09f89794d79f -r d8e7ce211541 src/cpu/simple_thread.cc --- a/src/cpu/simple_thread.cc Mon May 28 13:27:38 2012 -0700 +++ b/src/cpu/simple_thread.cc Mon May 28 14:20:21 2012 -0700 @@ -63,7 +63,7 @@ Process *_process, TheISA::TLB *_itb, TheISA::TLB *_dtb) : ThreadState(_cpu, _thread_num, _process), system(_sys), itb(_itb), - dtb(_dtb), decoder(NULL) + dtb(_dtb) { clearArchRegs(); tc = new ProxyThreadContext(this); @@ -71,8 +71,7 @@ SimpleThread::SimpleThread(BaseCPU *_cpu, int _thread_num, System *_sys, TheISA::TLB *_itb, TheISA::TLB *_dtb, bool use_kernel_stats) - : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb), - decoder(NULL) + : ThreadState(_cpu, _thread_num, NULL), system(_sys), itb(_itb), dtb(_dtb) { tc = new ProxyThreadContext(this); @@ -99,7 +98,7 @@ } SimpleThread::SimpleThread() - : ThreadState(NULL, -1, NULL), decoder(NULL) + : ThreadState(NULL, -1, NULL) { tc = new ProxyThreadContext(this); }