diff -r 8b9f227b64d8 -r 2c4b1b348599 src/cpu/inorder/pipeline_stage.cc
--- a/src/cpu/inorder/pipeline_stage.cc	Wed May 30 05:31:48 2012 -0400
+++ b/src/cpu/inorder/pipeline_stage.cc	Thu May 31 01:22:38 2012 -0400
@@ -954,6 +954,14 @@
 
             ResReqPtr req = cpu->resPool->request(res_num, inst);
             assert(req->valid);
+            //Need to check if the last request was a macro-op *creating* micro-ops.
+            //If so...
+            //   We need to break out of processing this instruction schedule
+            //   and instead start handling micro-ops that have been created
+            //@note: maybe add a field to the request structure that indicates
+            //       a micro-op has been created *or* maybe created a return
+            //       enum type for the request unction and then have the ResReqPtr
+            //       be a argument to the request function.
 
             bool req_completed = req->isCompleted();
             bool done_in_pipeline = false;
diff -r 8b9f227b64d8 -r 2c4b1b348599 src/cpu/inorder/resources/decode_unit.hh
--- a/src/cpu/inorder/resources/decode_unit.hh	Wed May 30 05:31:48 2012 -0400
+++ b/src/cpu/inorder/resources/decode_unit.hh	Thu May 31 01:22:38 2012 -0400
@@ -60,6 +60,9 @@
 
   protected:
     /** @todo: Add Resource Stats Here */
+
+    // Add a pointer to the predecoder here:
+    // needs to be per-hardware thread
 };
 
 #endif //__CPU_INORDER_DECODE_UNIT_HH__
diff -r 8b9f227b64d8 -r 2c4b1b348599 src/cpu/inorder/resources/decode_unit.cc
--- a/src/cpu/inorder/resources/decode_unit.cc	Wed May 30 05:31:48 2012 -0400
+++ b/src/cpu/inorder/resources/decode_unit.cc	Thu May 31 01:22:38 2012 -0400
@@ -65,7 +65,17 @@
                 DPRINTF(InOrderDecode,"[tid:%i]: Fault found for instruction [sn:%i]\n",
                         inst->readTid(), inst->seqNum);
             } else {
-                assert(!inst->staticInst->isMacroop());
+              assert(!inst->staticInst->isMacroop());
+              /* 1. Remove above assert
+               * 2. if macro-op, use predecoder object to decode micro-ops
+               * --->(a) decode as many micro-ops as the current stage-width will accept. alternatively,
+               *          could decode all possible micro-ops if that's realistic for your design.
+               * --->(b) place micro-ops into pipeline stage buffer of macro-op
+               * --->(c) make sure to place the micro-ops before the macro-ops
+               *         in the stage buffer (micro-ops need to process before
+               *         the macro-op).
+               */
+
                 inst->setBackSked(cpu->createBackEndSked(inst));
                 DPRINTF(InOrderDecode,"Decoded instruction [sn:%i]: %s : 0x%x\n",
                         inst->seqNum, inst->instName(),
diff -r 8b9f227b64d8 -r 2c4b1b348599 src/cpu/inorder/resources/fetch_seq_unit.cc
--- a/src/cpu/inorder/resources/fetch_seq_unit.cc	Wed May 30 05:31:48 2012 -0400
+++ b/src/cpu/inorder/resources/fetch_seq_unit.cc	Thu May 31 01:22:38 2012 -0400
@@ -104,6 +104,18 @@
                 // Advance to next PC (typically PC + 4)
                 pc[tid].advance();
 
+                /* The current seqNum system will not work
+                 * with microcoded ops because the number is given out before
+                 * we decode things. Thus by the time we decode macro-op w/sn:100
+                 * we've already given out sn:101, sn:102, etc. when we really
+                 * wanted the micro-ops to be sn:101, sn:102 and the macro-op to be
+                 * sn:(100+n).
+                 * One solution to this might be to create two sequence numbers. One
+                 * predecode and one post-decode that's managed beneath the inst->seqNum
+                 * references in the model. The reason for concern here is that all
+                 * the pipeline squash functions need to check sequence numbers to figure out
+                 * what instructions are older.
+                 */
                 inst->setSeqNum(cpu->getAndIncrementInstSeq(tid));
 
                 DPRINTF(InOrderFetchSeq, "[tid:%i]: Assigning [sn:%i] to "