diff -r 2316c982b654 -r 071785686b37 src/mem/protocol/MOESI_CMP_directory-L1cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L1cache.sm	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L1cache.sm	Fri Jun 15 02:55:35 2012 -0500
@@ -187,7 +187,6 @@
          ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
 
         cache_entry.CacheState := state;
-        sequencer.checkCoherence(addr);
       }
       else {
         cache_entry.CacheState := state;
diff -r 2316c982b654 -r 071785686b37 src/mem/protocol/MOESI_CMP_directory-L2cache.sm
--- a/src/mem/protocol/MOESI_CMP_directory-L2cache.sm	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-L2cache.sm	Fri Jun 15 02:55:35 2012 -0500
@@ -487,8 +487,6 @@
            ((cache_entry.CacheState != State:S) && (state == State:S)) ||
            ((cache_entry.CacheState != State:O) && (state == State:O)) ) {
         cache_entry.CacheState := state;
-        // disable Coherence Checker for now
-        // sequencer.checkCoherence(addr);
       }
       else {
         cache_entry.CacheState := state;
diff -r 2316c982b654 -r 071785686b37 src/mem/protocol/MOESI_CMP_directory-dir.sm
--- a/src/mem/protocol/MOESI_CMP_directory-dir.sm	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/protocol/MOESI_CMP_directory-dir.sm	Fri Jun 15 02:55:35 2012 -0500
@@ -170,8 +170,6 @@
 
       if ( (getDirectoryEntry(addr).DirectoryState != State:I) && (state == State:I) ) {
         getDirectoryEntry(addr).DirectoryState := state;
-         // disable coherence checker
-        // sequencer.checkCoherence(addr);
       }
       else {
         getDirectoryEntry(addr).DirectoryState := state;
diff -r 2316c982b654 -r 071785686b37 src/mem/protocol/RubySlicc_Types.sm
--- a/src/mem/protocol/RubySlicc_Types.sm	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/protocol/RubySlicc_Types.sm	Fri Jun 15 02:55:35 2012 -0500
@@ -105,7 +105,6 @@
   void writeCallback(Address, DataBlock);
   void writeCallback(Address, GenericMachineType, DataBlock);
   void writeCallback(Address, GenericMachineType, DataBlock, Time, Time, Time);
-  void checkCoherence(Address);
   void profileNack(Address, int, int, uint64);
   void evictionCallback(Address);
 }
diff -r 2316c982b654 -r 071785686b37 src/mem/ruby/system/Sequencer.hh
--- a/src/mem/ruby/system/Sequencer.hh	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/ruby/system/Sequencer.hh	Fri Jun 15 02:55:35 2012 -0500
@@ -111,7 +111,6 @@
 
     void print(std::ostream& out) const;
     void printStats(std::ostream& out) const;
-    void checkCoherence(const Address& address);
 
     void markRemoved();
     void removeRequest(SequencerRequest* request);
diff -r 2316c982b654 -r 071785686b37 src/mem/ruby/system/Sequencer.cc
--- a/src/mem/ruby/system/Sequencer.cc	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/ruby/system/Sequencer.cc	Fri Jun 15 02:55:35 2012 -0500
@@ -709,17 +709,6 @@
         << "]";
 }
 
-// this can be called from setState whenever coherence permissions are
-// upgraded when invoked, coherence violations will be checked for the
-// given block
-void
-Sequencer::checkCoherence(const Address& addr)
-{
-#ifdef CHECK_COHERENCE
-    g_system_ptr->checkGlobalCoherenceInvariant(addr);
-#endif
-}
-
 void
 Sequencer::evictionCallback(const Address& address)
 {
diff -r 2316c982b654 -r 071785686b37 src/mem/ruby/system/System.cc
--- a/src/mem/ruby/system/System.cc	Fri Jun 15 02:53:24 2012 -0500
+++ b/src/mem/ruby/system/System.cc	Fri Jun 15 02:55:35 2012 -0500
@@ -391,58 +391,6 @@
     m_network_ptr->clearStats();
 }
 
-#ifdef CHECK_COHERENCE
-// This code will check for cases if the given cache block is exclusive in
-// one node and shared in another-- a coherence violation
-//
-// To use, the SLICC specification must call sequencer.checkCoherence(address)
-// when the controller changes to a state with new permissions.  Do this
-// in setState.  The SLICC spec must also define methods "isBlockShared"
-// and "isBlockExclusive" that are specific to that protocol
-//
-void
-RubySystem::checkGlobalCoherenceInvariant(const Address& addr)
-{
-#if 0
-    NodeID exclusive = -1;
-    bool sharedDetected = false;
-    NodeID lastShared = -1;
-
-    for (int i = 0; i < m_chip_vector.size(); i++) {
-        if (m_chip_vector[i]->isBlockExclusive(addr)) {
-            if (exclusive != -1) {
-                // coherence violation
-                WARN_EXPR(exclusive);
-                WARN_EXPR(m_chip_vector[i]->getID());
-                WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
-                ERROR_MSG("Coherence Violation Detected -- 2 exclusive chips");
-            } else if (sharedDetected) {
-                WARN_EXPR(lastShared);
-                WARN_EXPR(m_chip_vector[i]->getID());
-                WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
-                ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
-            } else {
-                exclusive = m_chip_vector[i]->getID();
-            }
-        } else if (m_chip_vector[i]->isBlockShared(addr)) {
-            sharedDetected = true;
-            lastShared = m_chip_vector[i]->getID();
-
-            if (exclusive != -1) {
-                WARN_EXPR(lastShared);
-                WARN_EXPR(exclusive);
-                WARN_EXPR(addr);
-                WARN_EXPR(g_eventQueue_ptr->getTime());
-                ERROR_MSG("Coherence Violation Detected -- exclusive chip with >=1 shared");
-            }
-        }
-    }
-#endif
-}
-#endif
-
 RubySystem *
 RubySystemParams::create()
 {