diff -r a9867d001c3c -r c14aa7de9462 src/arch/arm/table_walker.hh --- a/src/arch/arm/table_walker.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/arm/table_walker.hh Sat Jul 21 13:15:50 2012 +0100 @@ -391,8 +391,8 @@ virtual unsigned int drain(Event *de); virtual void resume(); - virtual MasterPort& getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); Fault walk(RequestPtr req, ThreadContext *tc, uint8_t cid, TLB::Mode mode, TLB::Translation *_trans, bool timing, bool functional = false); diff -r a9867d001c3c -r c14aa7de9462 src/arch/arm/table_walker.cc --- a/src/arch/arm/table_walker.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/arm/table_walker.cc Sat Jul 21 13:15:50 2012 +0100 @@ -91,8 +91,8 @@ } } -MasterPort& -TableWalker::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort& +TableWalker::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "port") { return port; diff -r a9867d001c3c -r c14aa7de9462 src/arch/arm/tlb.hh --- a/src/arch/arm/tlb.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/arm/tlb.hh Sat Jul 21 13:15:50 2012 +0100 @@ -224,7 +224,7 @@ * * @return A pointer to the walker master port */ - virtual MasterPort* getMasterPort(); + virtual BaseMasterPort* getMasterPort(); // Caching misc register values here. // Writing to misc registers needs to invalidate them. diff -r a9867d001c3c -r c14aa7de9462 src/arch/arm/tlb.cc --- a/src/arch/arm/tlb.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/arm/tlb.cc Sat Jul 21 13:15:50 2012 +0100 @@ -722,7 +722,7 @@ return fault; } -MasterPort* +BaseMasterPort* TLB::getMasterPort() { return &tableWalker->getMasterPort("port"); diff -r a9867d001c3c -r c14aa7de9462 src/arch/x86/interrupts.hh --- a/src/arch/x86/interrupts.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/x86/interrupts.hh Sat Jul 21 13:15:50 2012 +0100 @@ -239,7 +239,8 @@ AddrRangeList getAddrRanges() const; AddrRangeList getIntAddrRange() const; - MasterPort &getMasterPort(const std::string &if_name, int idx = -1) + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) { if (if_name == "int_master") { return intMasterPort; @@ -247,7 +248,8 @@ return BasicPioDevice::getMasterPort(if_name, idx); } - SlavePort &getSlavePort(const std::string &if_name, int idx = -1) + BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID) { if (if_name == "int_slave") { return intSlavePort; diff -r a9867d001c3c -r c14aa7de9462 src/arch/x86/pagetable_walker.hh --- a/src/arch/x86/pagetable_walker.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/x86/pagetable_walker.hh Sat Jul 21 13:15:50 2012 +0100 @@ -169,7 +169,8 @@ RequestPtr req, BaseTLB::Mode mode); Fault startFunctional(ThreadContext * _tc, Addr &addr, unsigned &logBytes, BaseTLB::Mode mode); - MasterPort &getMasterPort(const std::string &if_name, int idx = -1); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); protected: // The TLB we're supposed to load. diff -r a9867d001c3c -r c14aa7de9462 src/arch/x86/pagetable_walker.cc --- a/src/arch/x86/pagetable_walker.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/x86/pagetable_walker.cc Sat Jul 21 13:15:50 2012 +0100 @@ -173,8 +173,8 @@ return port.sendTimingReq(pkt); } -MasterPort & -Walker::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +Walker::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "port") return port; diff -r a9867d001c3c -r c14aa7de9462 src/arch/x86/tlb.hh --- a/src/arch/x86/tlb.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/x86/tlb.hh Sat Jul 21 13:15:50 2012 +0100 @@ -147,7 +147,7 @@ * * @return A pointer to the walker master port */ - virtual MasterPort *getMasterPort(); + virtual BaseMasterPort *getMasterPort(); }; } diff -r a9867d001c3c -r c14aa7de9462 src/arch/x86/tlb.cc --- a/src/arch/x86/tlb.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/arch/x86/tlb.cc Sat Jul 21 13:15:50 2012 +0100 @@ -435,7 +435,7 @@ { } -MasterPort * +BaseMasterPort * TLB::getMasterPort() { return &walker->getMasterPort("port"); diff -r a9867d001c3c -r c14aa7de9462 src/cpu/base.hh --- a/src/cpu/base.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/base.hh Sat Jul 21 13:15:50 2012 +0100 @@ -172,7 +172,8 @@ * * @return a reference to the port with the given name */ - MasterPort &getMasterPort(const std::string &if_name, int idx = -1); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); // Tick currentTick; inline Tick frequency() const { return SimClock::Frequency / clock; } diff -r a9867d001c3c -r c14aa7de9462 src/cpu/base.cc --- a/src/cpu/base.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/base.cc Sat Jul 21 13:15:50 2012 +0100 @@ -302,8 +302,8 @@ threadContexts[0]->regStats(name()); } -MasterPort & -BaseCPU::getMasterPort(const string &if_name, int idx) +BaseMasterPort & +BaseCPU::getMasterPort(const string &if_name, PortID idx) { // Get the right port based on name. This applies to all the // subclasses of the base CPU and relies on their implementation @@ -408,20 +408,20 @@ ThreadContext::compare(oldTC, newTC); */ - MasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); - MasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); - MasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); - MasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); + BaseMasterPort *old_itb_port = oldTC->getITBPtr()->getMasterPort(); + BaseMasterPort *old_dtb_port = oldTC->getDTBPtr()->getMasterPort(); + BaseMasterPort *new_itb_port = newTC->getITBPtr()->getMasterPort(); + BaseMasterPort *new_dtb_port = newTC->getDTBPtr()->getMasterPort(); // Move over any table walker ports if they exist if (new_itb_port && !new_itb_port->isConnected()) { assert(old_itb_port); - SlavePort &slavePort = old_itb_port->getSlavePort(); + BaseSlavePort &slavePort = old_itb_port->getSlavePort(); new_itb_port->bind(slavePort); } if (new_dtb_port && !new_dtb_port->isConnected()) { assert(old_dtb_port); - SlavePort &slavePort = old_dtb_port->getSlavePort(); + BaseSlavePort &slavePort = old_dtb_port->getSlavePort(); new_dtb_port->bind(slavePort); } @@ -430,24 +430,26 @@ CheckerCPU *oldChecker = oldTC->getCheckerCpuPtr(); CheckerCPU *newChecker = newTC->getCheckerCpuPtr(); if (oldChecker && newChecker) { - MasterPort *old_checker_itb_port = + BaseMasterPort *old_checker_itb_port = oldChecker->getITBPtr()->getMasterPort(); - MasterPort *old_checker_dtb_port = + BaseMasterPort *old_checker_dtb_port = oldChecker->getDTBPtr()->getMasterPort(); - MasterPort *new_checker_itb_port = + BaseMasterPort *new_checker_itb_port = newChecker->getITBPtr()->getMasterPort(); - MasterPort *new_checker_dtb_port = + BaseMasterPort *new_checker_dtb_port = newChecker->getDTBPtr()->getMasterPort(); // Move over any table walker ports if they exist for checker if (new_checker_itb_port && !new_checker_itb_port->isConnected()) { assert(old_checker_itb_port); - SlavePort &slavePort = old_checker_itb_port->getSlavePort();; + BaseSlavePort &slavePort = + old_checker_itb_port->getSlavePort();; new_checker_itb_port->bind(slavePort); } if (new_checker_dtb_port && !new_checker_dtb_port->isConnected()) { assert(old_checker_dtb_port); - SlavePort &slavePort = old_checker_dtb_port->getSlavePort();; + BaseSlavePort &slavePort = + old_checker_dtb_port->getSlavePort();; new_checker_dtb_port->bind(slavePort); } } diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/directedtest/RubyDirectedTester.hh --- a/src/cpu/testers/directedtest/RubyDirectedTester.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/directedtest/RubyDirectedTester.hh Sat Jul 21 13:15:50 2012 +0100 @@ -68,8 +68,8 @@ RubyDirectedTester(const Params *p); ~RubyDirectedTester(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); MasterPort* getCpuPort(int idx); diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/directedtest/RubyDirectedTester.cc --- a/src/cpu/testers/directedtest/RubyDirectedTester.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/directedtest/RubyDirectedTester.cc Sat Jul 21 13:15:50 2012 +0100 @@ -75,8 +75,8 @@ generator->setDirectedTester(this); } -MasterPort & -RubyDirectedTester::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyDirectedTester::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "cpuPort") { // pass it along to our super class diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/memtest/memtest.hh --- a/src/cpu/testers/memtest/memtest.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/memtest/memtest.hh Sat Jul 21 13:15:50 2012 +0100 @@ -61,8 +61,8 @@ // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/memtest/memtest.cc --- a/src/cpu/testers/memtest/memtest.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/memtest/memtest.cc Sat Jul 21 13:15:50 2012 +0100 @@ -131,8 +131,8 @@ dmaOutstanding = false; } -MasterPort & -MemTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +MemTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "functional") return funcPort; diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/networktest/networktest.hh --- a/src/cpu/testers/networktest/networktest.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/networktest/networktest.hh Sat Jul 21 13:15:50 2012 +0100 @@ -56,8 +56,8 @@ // main simulation loop (one cycle) void tick(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Print state of address in memory system via PrintReq (for diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/networktest/networktest.cc --- a/src/cpu/testers/networktest/networktest.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/networktest/networktest.cc Sat Jul 21 13:15:50 2012 +0100 @@ -97,8 +97,8 @@ name(), id); } -MasterPort & -NetworkTest::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +NetworkTest::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "test") return cachePort; diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/rubytest/RubyTester.hh --- a/src/cpu/testers/rubytest/RubyTester.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/rubytest/RubyTester.hh Sat Jul 21 13:15:50 2012 +0100 @@ -89,8 +89,8 @@ RubyTester(const Params *p); ~RubyTester(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); bool isInstReadableCpuPort(int idx); diff -r a9867d001c3c -r c14aa7de9462 src/cpu/testers/rubytest/RubyTester.cc --- a/src/cpu/testers/rubytest/RubyTester.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/cpu/testers/rubytest/RubyTester.cc Sat Jul 21 13:15:50 2012 +0100 @@ -112,8 +112,8 @@ m_checkTable_ptr = new CheckTable(m_num_writers, m_num_readers, this); } -MasterPort & -RubyTester::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyTester::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "cpuInstPort" && if_name != "cpuDataPort") { // pass it along to our super class @@ -135,7 +135,7 @@ // index // int read_idx = idx + m_num_inst_ports; - if (read_idx >= static_cast(readPorts.size())) { + if (read_idx >= static_cast(readPorts.size())) { panic("RubyTester::getMasterPort: unknown data port idx %d\n", idx); } diff -r a9867d001c3c -r c14aa7de9462 src/dev/copy_engine.hh --- a/src/dev/copy_engine.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/copy_engine.hh Sat Jul 21 13:15:50 2012 +0100 @@ -94,7 +94,7 @@ public: CopyEngineChannel(CopyEngine *_ce, int cid); virtual ~CopyEngineChannel(); - MasterPort &getMasterPort(); + BaseMasterPort &getMasterPort(); std::string name() { assert(ce); return ce->name() + csprintf("-chan%d", channelId); } virtual Tick read(PacketPtr pkt) @@ -196,8 +196,8 @@ void regStats(); - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); virtual Tick read(PacketPtr pkt); virtual Tick write(PacketPtr pkt); diff -r a9867d001c3c -r c14aa7de9462 src/dev/copy_engine.cc --- a/src/dev/copy_engine.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/copy_engine.cc Sat Jul 21 13:15:50 2012 +0100 @@ -110,8 +110,8 @@ delete [] copyBuffer; } -MasterPort & -CopyEngine::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +CopyEngine::getMasterPort(const std::string &if_name, PortID idx) { if (if_name != "dma") { // pass it along to our super class @@ -126,7 +126,7 @@ } -MasterPort & +BaseMasterPort & CopyEngine::CopyEngineChannel::getMasterPort() { return cePort; diff -r a9867d001c3c -r c14aa7de9462 src/dev/dma_device.hh --- a/src/dev/dma_device.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/dma_device.hh Sat Jul 21 13:15:50 2012 +0100 @@ -162,8 +162,8 @@ unsigned cacheBlockSize() const { return dmaPort.cacheBlockSize(); } - virtual MasterPort &getMasterPort(const std::string &if_name, - int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); friend class DmaPort; }; diff -r a9867d001c3c -r c14aa7de9462 src/dev/dma_device.cc --- a/src/dev/dma_device.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/dma_device.cc Sat Jul 21 13:15:50 2012 +0100 @@ -300,8 +300,8 @@ { } -MasterPort & -DmaDevice::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +DmaDevice::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "dma") { return dmaPort; diff -r a9867d001c3c -r c14aa7de9462 src/dev/io_device.hh --- a/src/dev/io_device.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/io_device.hh Sat Jul 21 13:15:50 2012 +0100 @@ -127,7 +127,8 @@ virtual unsigned int drain(Event *de); - virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1); + virtual BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID); friend class PioPort; diff -r a9867d001c3c -r c14aa7de9462 src/dev/io_device.cc --- a/src/dev/io_device.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/io_device.cc Sat Jul 21 13:15:50 2012 +0100 @@ -79,8 +79,8 @@ pioPort.sendRangeChange(); } -SlavePort & -PioDevice::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +PioDevice::getSlavePort(const std::string &if_name, PortID idx) { if (if_name == "pio") { return pioPort; diff -r a9867d001c3c -r c14aa7de9462 src/dev/pcidev.hh --- a/src/dev/pcidev.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/pcidev.hh Sat Jul 21 13:15:50 2012 +0100 @@ -218,7 +218,8 @@ virtual unsigned int drain(Event *de); - virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1) + virtual BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID) { if (if_name == "config") { return configPort; diff -r a9867d001c3c -r c14aa7de9462 src/dev/x86/i82094aa.hh --- a/src/dev/x86/i82094aa.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/dev/x86/i82094aa.hh Sat Jul 21 13:15:50 2012 +0100 @@ -121,7 +121,8 @@ void writeReg(uint8_t offset, uint32_t value); uint32_t readReg(uint8_t offset); - MasterPort &getMasterPort(const std::string &if_name, int idx = -1) + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID) { if (if_name == "int_master") return intMasterPort; diff -r a9867d001c3c -r c14aa7de9462 src/mem/bridge.hh --- a/src/mem/bridge.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/bridge.hh Sat Jul 21 13:15:50 2012 +0100 @@ -380,9 +380,10 @@ public: const Params *params() const { return _params; } - virtual MasterPort& getMasterPort(const std::string& if_name, - int idx = -1); - virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1); + virtual BaseMasterPort& getMasterPort(const std::string& if_name, + PortID idx = InvalidPortID); + virtual BaseSlavePort& getSlavePort(const std::string& if_name, + PortID idx = InvalidPortID); virtual void init(); diff -r a9867d001c3c -r c14aa7de9462 src/mem/bridge.cc --- a/src/mem/bridge.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/bridge.cc Sat Jul 21 13:15:50 2012 +0100 @@ -88,8 +88,8 @@ panic("No support for acknowledging writes\n"); } -MasterPort& -Bridge::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort& +Bridge::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "master") return masterPort; @@ -98,8 +98,8 @@ return MemObject::getMasterPort(if_name, idx); } -SlavePort& -Bridge::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort& +Bridge::getSlavePort(const std::string &if_name, PortID idx) { if (if_name == "slave") return slavePort; diff -r a9867d001c3c -r c14aa7de9462 src/mem/bus.hh --- a/src/mem/bus.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/bus.hh Sat Jul 21 13:15:50 2012 +0100 @@ -362,8 +362,10 @@ public: /** A function used to return the port associated with this bus object. */ - virtual MasterPort& getMasterPort(const std::string& if_name, int idx = -1); - virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1); + BaseMasterPort& getMasterPort(const std::string& if_name, + PortID idx = InvalidPortID); + BaseSlavePort& getSlavePort(const std::string& if_name, + PortID idx = InvalidPortID); virtual unsigned int drain(Event *de) = 0; diff -r a9867d001c3c -r c14aa7de9462 src/mem/bus.cc --- a/src/mem/bus.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/bus.cc Sat Jul 21 13:15:50 2012 +0100 @@ -84,8 +84,8 @@ } } -MasterPort & -BaseBus::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +BaseBus::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "master" && idx < masterPorts.size()) { // the master port index translates directly to the vector position @@ -97,8 +97,8 @@ } } -SlavePort & -BaseBus::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +BaseBus::getSlavePort(const std::string &if_name, PortID idx) { if (if_name == "slave" && idx < slavePorts.size()) { // the slave port index translates directly to the vector position diff -r a9867d001c3c -r c14aa7de9462 src/mem/cache/base.hh --- a/src/mem/cache/base.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/cache/base.hh Sat Jul 21 13:15:50 2012 +0100 @@ -444,8 +444,10 @@ virtual void init(); - virtual MasterPort &getMasterPort(const std::string &if_name, int idx = -1); - virtual SlavePort &getSlavePort(const std::string &if_name, int idx = -1); + virtual BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); + virtual BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID); /** * Query block size of a cache. diff -r a9867d001c3c -r c14aa7de9462 src/mem/cache/base.cc --- a/src/mem/cache/base.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/cache/base.cc Sat Jul 21 13:15:50 2012 +0100 @@ -112,8 +112,8 @@ cpuSidePort->sendRangeChange(); } -MasterPort & -BaseCache::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +BaseCache::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "mem_side") { return *memSidePort; @@ -122,8 +122,8 @@ } } -SlavePort & -BaseCache::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +BaseCache::getSlavePort(const std::string &if_name, PortID idx) { if (if_name == "cpu_side") { return *cpuSidePort; diff -r a9867d001c3c -r c14aa7de9462 src/mem/comm_monitor.hh --- a/src/mem/comm_monitor.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/comm_monitor.hh Sat Jul 21 13:15:50 2012 +0100 @@ -77,11 +77,11 @@ /** Destructor */ ~CommMonitor() { } - virtual MasterPort& getMasterPort(const std::string& if_name, - int idx = -1); + virtual BaseMasterPort& getMasterPort(const std::string& if_name, + PortID idx = InvalidPortID); - virtual SlavePort& getSlavePort(const std::string& if_name, - int idx = -1); + virtual BaseSlavePort& getSlavePort(const std::string& if_name, + PortID idx = InvalidPortID); virtual void init(); diff -r a9867d001c3c -r c14aa7de9462 src/mem/comm_monitor.cc --- a/src/mem/comm_monitor.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/comm_monitor.cc Sat Jul 21 13:15:50 2012 +0100 @@ -74,8 +74,8 @@ fatal("Communication monitor is not connected on both sides.\n"); } -MasterPort& -CommMonitor::getMasterPort(const std::string& if_name, int idx) +BaseMasterPort& +CommMonitor::getMasterPort(const std::string& if_name, PortID idx) { if (if_name == "master") { return masterPort; @@ -84,8 +84,8 @@ } } -SlavePort& -CommMonitor::getSlavePort(const std::string& if_name, int idx) +BaseSlavePort& +CommMonitor::getSlavePort(const std::string& if_name, PortID idx) { if (if_name == "slave") { return slavePort; diff -r a9867d001c3c -r c14aa7de9462 src/mem/mem_object.hh --- a/src/mem/mem_object.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/mem_object.hh Sat Jul 21 13:15:50 2012 +0100 @@ -67,26 +67,30 @@ MemObject(const Params *params); /** - * Get a master port with a given name and index. + * Get a master port with a given name and index. This is used at + * binding time and returns a reference to a protocol-agnostic + * base master port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - virtual MasterPort& getMasterPort(const std::string& if_name, - int idx = -1); + virtual BaseMasterPort& getMasterPort(const std::string& if_name, + PortID idx = InvalidPortID); /** - * Get a slave port with a given name and index. + * Get a slave port with a given name and index. This is used at + * binding time and returns a reference to a protocol-agnostic + * base master port. * * @param if_name Port name * @param idx Index in the case of a VectorPort * * @return A reference to the given port */ - virtual SlavePort& getSlavePort(const std::string& if_name, - int idx = -1); + virtual BaseSlavePort& getSlavePort(const std::string& if_name, + PortID idx = InvalidPortID); }; #endif //__MEM_MEM_OBJECT_HH__ diff -r a9867d001c3c -r c14aa7de9462 src/mem/mem_object.cc --- a/src/mem/mem_object.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/mem_object.cc Sat Jul 21 13:15:50 2012 +0100 @@ -48,14 +48,14 @@ { } -MasterPort& -MemObject::getMasterPort(const std::string& if_name, int idx) +BaseMasterPort& +MemObject::getMasterPort(const std::string& if_name, PortID idx) { fatal("%s does not have any master port named %s\n", name(), if_name); } -SlavePort& -MemObject::getSlavePort(const std::string& if_name, int idx) +BaseSlavePort& +MemObject::getSlavePort(const std::string& if_name, PortID idx) { fatal("%s does not have any slave port named %s\n", name(), if_name); } diff -r a9867d001c3c -r c14aa7de9462 src/mem/port.hh --- a/src/mem/port.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/port.hh Sat Jul 21 13:15:50 2012 +0100 @@ -117,15 +117,66 @@ }; /** Forward declaration */ +class BaseSlavePort; + +/** + * A BaseMasterPort is a protocol-agnostic master port, responsible + * only for the structural connection to a slave port. The final + * master port that inherits from the base class must override the + * bind member function for the specific slave port class. + */ +class BaseMasterPort : public Port +{ + + protected: + + BaseSlavePort* _baseSlavePort; + + BaseMasterPort(const std::string& name, MemObject* owner, + PortID id = InvalidPortID); + virtual ~BaseMasterPort(); + + public: + + virtual void bind(BaseSlavePort& slave_port) = 0; + BaseSlavePort& getSlavePort() const; + bool isConnected() const; + +}; + +/** + * A BaseSlavePort is a protocol-agnostic slave port, responsible + * only for the structural connection to a master port. + */ +class BaseSlavePort : public Port +{ + + protected: + + BaseMasterPort* _baseMasterPort; + + BaseSlavePort(const std::string& name, MemObject* owner, + PortID id = InvalidPortID); + virtual ~BaseSlavePort(); + + public: + + BaseMasterPort& getMasterPort() const; + bool isConnected() const; + +}; + +/** Forward declaration */ class SlavePort; /** - * A MasterPort is a specialisation of a port. In addition to the - * basic functionality of sending packets to its slave peer, it also - * has functions specific to a master, e.g. to receive range changes - * or determine if the port is snooping or not. + * A MasterPort is a specialisation of a BaseMasterPort, which + * implements the default protocol for the three different level of + * transport functions. In addition to the basic functionality of + * sending packets, it also has functions to receive range changes or + * determine if the port is snooping or not. */ -class MasterPort : public Port +class MasterPort : public BaseMasterPort { friend class SlavePort; @@ -140,9 +191,7 @@ PortID id = InvalidPortID); virtual ~MasterPort(); - void bind(SlavePort& slave_port); - SlavePort& getSlavePort() const; - bool isConnected() const; + void bind(BaseSlavePort& slave_port); /** * Send an atomic request packet, where the data is moved and the @@ -282,7 +331,7 @@ * has functions specific to a slave, e.g. to send range changes * and get the address ranges that the port responds to. */ -class SlavePort : public Port +class SlavePort : public BaseSlavePort { friend class MasterPort; @@ -298,8 +347,6 @@ virtual ~SlavePort(); void bind(MasterPort& master_port); - MasterPort& getMasterPort() const; - bool isConnected() const; /** * Send an atomic snoop request packet, where the data is moved diff -r a9867d001c3c -r c14aa7de9462 src/mem/port.cc --- a/src/mem/port.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/port.cc Sat Jul 21 13:15:50 2012 +0100 @@ -59,11 +59,63 @@ { } +BaseMasterPort::BaseMasterPort(const std::string& name, MemObject* owner, + PortID _id) + : Port(name, *owner, _id), _baseSlavePort(NULL) +{ +} + +BaseMasterPort::~BaseMasterPort() +{ +} + +BaseSlavePort& +BaseMasterPort::getSlavePort() const +{ + if(_baseSlavePort == NULL) + panic("Cannot getSlavePort on master port %s that is not connected\n", + name()); + + return *_baseSlavePort; +} + +bool +BaseMasterPort::isConnected() const +{ + return _baseSlavePort != NULL; +} + +BaseSlavePort::BaseSlavePort(const std::string& name, MemObject* owner, + PortID _id) + : Port(name, *owner, _id), _baseMasterPort(NULL) +{ +} + +BaseSlavePort::~BaseSlavePort() +{ +} + +BaseMasterPort& +BaseSlavePort::getMasterPort() const +{ + if(_baseMasterPort == NULL) + panic("Cannot getMasterPort on slave port %s that is not connected\n", + name()); + + return *_baseMasterPort; +} + +bool +BaseSlavePort::isConnected() const +{ + return _baseMasterPort != NULL; +} + /** * Master port */ MasterPort::MasterPort(const std::string& name, MemObject* owner, PortID _id) - : Port(name, *owner, _id), _slavePort(NULL) + : BaseMasterPort(name, owner, _id), _slavePort(NULL) { } @@ -71,30 +123,26 @@ { } -SlavePort& -MasterPort::getSlavePort() const +void +MasterPort::bind(BaseSlavePort& slave_port) { - if(_slavePort == NULL) - panic("Cannot getSlavePort on master port %s that is not connected\n", - name()); + // bind on the level of the base ports + _baseSlavePort = &slave_port; - return *_slavePort; -} + // also attempt to base the slave to the appropriate type + SlavePort* cast_slave_port = dynamic_cast(&slave_port); -void -MasterPort::bind(SlavePort& slave_port) -{ - // master port keeps track of the slave port - _slavePort = &slave_port; + // if this port is compatible, then proceed with the binding + if (cast_slave_port != NULL) { + // master port keeps track of the slave port + _slavePort = cast_slave_port; - // slave port also keeps track of master port - _slavePort->bind(*this); -} - -bool -MasterPort::isConnected() const -{ - return _slavePort != NULL; + // slave port also keeps track of master port + _slavePort->bind(*this); + } else { + fatal("Master port %s cannot bind to %s\n", name(), + slave_port.name()); + } } unsigned @@ -158,7 +206,7 @@ * Slave port */ SlavePort::SlavePort(const std::string& name, MemObject* owner, PortID id) - : Port(name, *owner, id), _masterPort(NULL) + : BaseSlavePort(name, owner, id), _masterPort(NULL) { } @@ -169,31 +217,16 @@ void SlavePort::bind(MasterPort& master_port) { + _baseMasterPort = &master_port; _masterPort = &master_port; } -MasterPort& -SlavePort::getMasterPort() const -{ - if (_masterPort == NULL) - panic("Cannot getMasterPort on slave port %s that is not connected\n", - name()); - - return *_masterPort; -} - unsigned SlavePort::peerBlockSize() const { return _masterPort->deviceBlockSize(); } -bool -SlavePort::isConnected() const -{ - return _masterPort != NULL; -} - Tick SlavePort::sendAtomicSnoop(PacketPtr pkt) { diff -r a9867d001c3c -r c14aa7de9462 src/mem/ruby/system/RubyPort.hh --- a/src/mem/ruby/system/RubyPort.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/ruby/system/RubyPort.hh Sat Jul 21 13:15:50 2012 +0100 @@ -130,8 +130,10 @@ void init(); - MasterPort &getMasterPort(const std::string &if_name, int idx); - SlavePort &getSlavePort(const std::string &if_name, int idx); + BaseMasterPort &getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); + BaseSlavePort &getSlavePort(const std::string &if_name, + PortID idx = InvalidPortID); virtual RequestStatus makeRequest(PacketPtr pkt) = 0; virtual int outstandingCount() const = 0; diff -r a9867d001c3c -r c14aa7de9462 src/mem/ruby/system/RubyPort.cc --- a/src/mem/ruby/system/RubyPort.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/ruby/system/RubyPort.cc Sat Jul 21 13:15:50 2012 +0100 @@ -77,8 +77,8 @@ m_mandatory_q_ptr = m_controller->getMandatoryQueue(); } -MasterPort & -RubyPort::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort & +RubyPort::getMasterPort(const std::string &if_name, PortID idx) { if (if_name == "pio_port") { return pio_port; @@ -90,7 +90,7 @@ // pass it along to our super class return MemObject::getMasterPort(if_name, idx); } else { - if (idx >= static_cast(master_ports.size())) { + if (idx >= static_cast(master_ports.size())) { panic("RubyPort::getMasterPort: unknown index %d\n", idx); } @@ -98,8 +98,8 @@ } } -SlavePort & -RubyPort::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +RubyPort::getSlavePort(const std::string &if_name, PortID idx) { // used by the CPUs to connect the caches to the interconnect, and // for the x86 case also the interrupt master @@ -107,7 +107,7 @@ // pass it along to our super class return MemObject::getSlavePort(if_name, idx); } else { - if (idx >= static_cast(slave_ports.size())) { + if (idx >= static_cast(slave_ports.size())) { panic("RubyPort::getSlavePort: unknown index %d\n", idx); } diff -r a9867d001c3c -r c14aa7de9462 src/mem/simple_mem.hh --- a/src/mem/simple_mem.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/simple_mem.hh Sat Jul 21 13:15:50 2012 +0100 @@ -95,7 +95,8 @@ unsigned int drain(Event* de); - virtual SlavePort& getSlavePort(const std::string& if_name, int idx = -1); + virtual BaseSlavePort& getSlavePort(const std::string& if_name, + PortID idx = InvalidPortID); virtual void init(); const Params * diff -r a9867d001c3c -r c14aa7de9462 src/mem/simple_mem.cc --- a/src/mem/simple_mem.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/mem/simple_mem.cc Sat Jul 21 13:15:50 2012 +0100 @@ -89,8 +89,8 @@ functionalAccess(pkt); } -SlavePort & -SimpleMemory::getSlavePort(const std::string &if_name, int idx) +BaseSlavePort & +SimpleMemory::getSlavePort(const std::string &if_name, PortID idx) { if (if_name != "port") { return MemObject::getSlavePort(if_name, idx); diff -r a9867d001c3c -r c14aa7de9462 src/python/swig/pyobject.cc --- a/src/python/swig/pyobject.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/python/swig/pyobject.cc Sat Jul 21 13:15:50 2012 +0100 @@ -102,8 +102,8 @@ } // generic master/slave port connection - MasterPort& masterPort = mo1->getMasterPort(name1, i1); - SlavePort& slavePort = mo2->getSlavePort(name2, i2); + BaseMasterPort& masterPort = mo1->getMasterPort(name1, i1); + BaseSlavePort& slavePort = mo2->getSlavePort(name2, i2); masterPort.bind(slavePort); diff -r a9867d001c3c -r c14aa7de9462 src/sim/system.hh --- a/src/sim/system.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/sim/system.hh Sat Jul 21 13:15:50 2012 +0100 @@ -117,7 +117,8 @@ /** * Additional function to return the Port of a memory object. */ - MasterPort& getMasterPort(const std::string &if_name, int idx = -1); + BaseMasterPort& getMasterPort(const std::string &if_name, + PortID idx = InvalidPortID); static const char *MemoryModeStrings[3]; diff -r a9867d001c3c -r c14aa7de9462 src/sim/system.cc --- a/src/sim/system.cc Sat Jul 21 12:16:40 2012 +0100 +++ b/src/sim/system.cc Sat Jul 21 13:15:50 2012 +0100 @@ -167,8 +167,8 @@ panic("System port on %s is not connected.\n", name()); } -MasterPort& -System::getMasterPort(const std::string &if_name, int idx) +BaseMasterPort& +System::getMasterPort(const std::string &if_name, PortID idx) { // no need to distinguish at the moment (besides checking) return _systemPort; diff -r a9867d001c3c -r c14aa7de9462 src/sim/tlb.hh --- a/src/sim/tlb.hh Sat Jul 21 12:16:40 2012 +0100 +++ b/src/sim/tlb.hh Sat Jul 21 13:15:50 2012 +0100 @@ -49,7 +49,7 @@ #include "sim/sim_object.hh" class ThreadContext; -class MasterPort; +class BaseMasterPort; class BaseTLB : public SimObject { @@ -73,7 +73,7 @@ * * @return A pointer to the walker master port or NULL if not present */ - virtual MasterPort* getMasterPort() { return NULL; } + virtual BaseMasterPort* getMasterPort() { return NULL; } class Translation {