diff -r e2b2f3fc9a28 -r 549249e14364 configs/example/memtest.py
--- a/configs/example/memtest.py	Mon Jun 18 16:29:30 2012 +0100
+++ b/configs/example/memtest.py	Mon Jun 18 17:09:32 2012 +0100
@@ -141,6 +141,7 @@
 
 # system simulated
 system = System(funcmem = SimpleMemory(in_addr_map = False),
+                funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(latency = "100ns"))
 
 def make_level(spec, prototypes, attach_obj, attach_port):
@@ -169,10 +170,13 @@
           parent.cpu = objs
           for t in objs:
                t.test = getattr(attach_obj, attach_port)
-               t.functional = system.funcmem.port
+               t.functional = system.funcbus.slave
 
 make_level(treespec, prototypes, system.physmem, "port")
 
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
+
 # -----------------------
 # run simulation
 # -----------------------
diff -r e2b2f3fc9a28 -r 549249e14364 configs/example/ruby_mem_test.py
--- a/configs/example/ruby_mem_test.py	Mon Jun 18 16:29:30 2012 +0100
+++ b/configs/example/ruby_mem_test.py	Mon Jun 18 17:09:32 2012 +0100
@@ -106,6 +106,7 @@
 
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
+                funcbus = NoncoherentBus(),
                 physmem = SimpleMemory())
 
 if options.num_dmas > 0:
@@ -140,7 +141,7 @@
     # Tie the cpu memtester ports to the correct system ports
     #
     cpu.test = system.ruby._cpu_ruby_ports[i].slave
-    cpu.functional = system.funcmem.port
+    cpu.functional = system.funcbus.slave
 
     #
     # Since the memtester is incredibly bursty, increase the deadlock
@@ -159,7 +160,10 @@
     # Tie the dma memtester ports to the correct functional port
     # Note that the test port has already been connected to the dma_sequencer
     #
-    dma.functional = system.funcmem.port
+    dma.functional = system.funcbus.slave
+
+# connect reference memory to funcbus
+system.funcbus.master = system.funcmem.port
 
 # -----------------------
 # run simulation
diff -r e2b2f3fc9a28 -r 549249e14364 src/mem/SimpleMemory.py
--- a/src/mem/SimpleMemory.py	Mon Jun 18 16:29:30 2012 +0100
+++ b/src/mem/SimpleMemory.py	Mon Jun 18 17:09:32 2012 +0100
@@ -44,6 +44,6 @@
 
 class SimpleMemory(AbstractMemory):
     type = 'SimpleMemory'
-    port = VectorSlavePort("Slave ports")
+    port = SlavePort("Slave ports")
     latency = Param.Latency('30ns', "Request to response latency")
     latency_var = Param.Latency('0ns', "Request to response latency variance")
diff -r e2b2f3fc9a28 -r 549249e14364 src/mem/simple_mem.hh
--- a/src/mem/simple_mem.hh	Mon Jun 18 16:29:30 2012 +0100
+++ b/src/mem/simple_mem.hh	Mon Jun 18 17:09:32 2012 +0100
@@ -81,7 +81,7 @@
 
     };
 
-    std::vector<MemoryPort*> ports;
+    MemoryPort port;
 
     Tick lat;
     Tick lat_var;
diff -r e2b2f3fc9a28 -r 549249e14364 src/mem/simple_mem.cc
--- a/src/mem/simple_mem.cc	Mon Jun 18 16:29:30 2012 +0100
+++ b/src/mem/simple_mem.cc	Mon Jun 18 17:09:32 2012 +0100
@@ -49,24 +49,17 @@
 
 SimpleMemory::SimpleMemory(const Params* p) :
     AbstractMemory(p),
-    lat(p->latency), lat_var(p->latency_var)
+    port(name() + ".port", *this), lat(p->latency), lat_var(p->latency_var)
 {
-    for (size_t i = 0; i < p->port_port_connection_count; ++i) {
-        ports.push_back(new MemoryPort(csprintf("%s-port-%d", name(), i),
-                                       *this));
-    }
 }
 
 void
 SimpleMemory::init()
 {
-    for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
-         ++p) {
-        if (!(*p)->isConnected()) {
-            fatal("SimpleMemory port %s is unconnected!\n", (*p)->name());
-        } else {
-            (*p)->sendRangeChange();
-        }
+    // allow unconnected memories as this is used in several ruby
+    // systems at the moment
+    if (port.isConnected()) {
+        port.sendRangeChange();
     }
 }
 
@@ -102,22 +95,14 @@
     if (if_name != "port") {
         return MemObject::getSlavePort(if_name, idx);
     } else {
-        if (idx >= static_cast<PortID>(ports.size())) {
-            fatal("SimpleMemory::getSlavePort: unknown index %d\n", idx);
-        }
-
-        return *ports[idx];
+        return port;
     }
 }
 
 unsigned int
 SimpleMemory::drain(Event *de)
 {
-    int count = 0;
-    for (vector<MemoryPort*>::iterator p = ports.begin(); p != ports.end();
-         ++p) {
-        count += (*p)->drain(de);
-    }
+    int count = port.drain(de);
 
     if (count)
         changeState(Draining);
diff -r e2b2f3fc9a28 -r 549249e14364 tests/configs/memtest-ruby.py
--- a/tests/configs/memtest-ruby.py	Mon Jun 18 16:29:30 2012 +0100
+++ b/tests/configs/memtest-ruby.py	Mon Jun 18 17:09:32 2012 +0100
@@ -78,6 +78,7 @@
 # system simulated
 system = System(cpu = cpus,
                 funcmem = SimpleMemory(in_addr_map = False),
+                funcbus = NoncoherentBus(),
                 physmem = SimpleMemory())
 
 Ruby.create_system(options, system)
@@ -90,7 +91,7 @@
      # physmem, respectively
      #
      cpus[i].test = ruby_port.slave
-     cpus[i].functional = system.funcmem.port
+     cpus[i].functional = system.funcbus.slave
      
      #
      # Since the memtester is incredibly bursty, increase the deadlock
@@ -104,6 +105,9 @@
      #
      ruby_port.access_phys_mem = False
 
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
 # -----------------------
 # run simulation
 # -----------------------
diff -r e2b2f3fc9a28 -r 549249e14364 tests/configs/memtest.py
--- a/tests/configs/memtest.py	Mon Jun 18 16:29:30 2012 +0100
+++ b/tests/configs/memtest.py	Mon Jun 18 17:09:32 2012 +0100
@@ -57,6 +57,7 @@
 
 # system simulated
 system = System(cpu = cpus, funcmem = SimpleMemory(in_addr_map = False),
+                funcbus = NoncoherentBus(),
                 physmem = SimpleMemory(),
                 membus = CoherentBus(clock="500GHz", width=16))
 
@@ -73,10 +74,13 @@
     cpu.l1c = L1(size = '32kB', assoc = 4)
     cpu.l1c.cpu_side = cpu.test
     cpu.l1c.mem_side = system.toL2Bus.slave
-    system.funcmem.port = cpu.functional
+    system.funcbus.slave = cpu.functional
 
 system.system_port = system.membus.slave
 
+# connect reference memory to funcbus
+system.funcmem.port = system.funcbus.master
+
 # connect memory to membus
 system.physmem.port = system.membus.master