diff -r d787467ae796 -r dd6c331371c1 src/mem/ruby/profiler/CacheProfiler.hh
--- a/src/mem/ruby/profiler/CacheProfiler.hh	Thu Jul 05 10:12:41 2012 -0500
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,88 +0,0 @@
-/*
- * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __MEM_RUBY_PROFILER_CACHEPROFILER_HH__
-#define __MEM_RUBY_PROFILER_CACHEPROFILER_HH__
-
-#include <iostream>
-#include <string>
-#include <vector>
-
-#include "mem/protocol/GenericRequestType.hh"
-#include "mem/protocol/PrefetchBit.hh"
-#include "mem/protocol/RubyAccessMode.hh"
-#include "mem/protocol/RubyRequestType.hh"
-#include "mem/ruby/common/Global.hh"
-#include "mem/ruby/common/Histogram.hh"
-
-class CacheProfiler
-{
-  public:
-    CacheProfiler(const std::string& description);
-    ~CacheProfiler();
-
-    void printStats(std::ostream& out) const;
-    void clearStats();
-
-    void addCacheStatSample(RubyRequestType requestType,
-                            RubyAccessMode type,
-                            PrefetchBit pfBit);
-
-    void addGenericStatSample(GenericRequestType requestType, 
-                              RubyAccessMode type,
-                              PrefetchBit pfBit);
-
-    void print(std::ostream& out) const;
-
-  private:
-    // Private copy constructor and assignment operator
-    CacheProfiler(const CacheProfiler& obj);
-    CacheProfiler& operator=(const CacheProfiler& obj);
-    void addStatSample(RubyAccessMode type, PrefetchBit pfBit);
-
-    std::string m_description;
-    int64 m_misses;
-    int64 m_demand_misses;
-    int64 m_prefetches;
-    int64 m_sw_prefetches;
-    int64 m_hw_prefetches;
-    int64 m_accessModeTypeHistogram[RubyAccessMode_NUM];
-
-    std::vector<int> m_cacheRequestType;
-    std::vector<int> m_genericRequestType;
-};
-
-inline std::ostream&
-operator<<(std::ostream& out, const CacheProfiler& obj)
-{
-    obj.print(out);
-    out << std::flush;
-    return out;
-}
-
-#endif // __MEM_RUBY_PROFILER_CACHEPROFILER_HH__
diff -r d787467ae796 -r dd6c331371c1 src/mem/ruby/profiler/CacheProfiler.cc
--- a/src/mem/ruby/profiler/CacheProfiler.cc	Thu Jul 05 10:12:41 2012 -0500
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,165 +0,0 @@
-/*
- * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "mem/ruby/profiler/CacheProfiler.hh"
-#include "mem/ruby/profiler/Profiler.hh"
-#include "mem/ruby/system/System.hh"
-
-using namespace std;
-
-CacheProfiler::CacheProfiler(const string& description)
-    : m_cacheRequestType(int(RubyRequestType_NUM)), m_genericRequestType(int(GenericRequestType_NUM))
-{
-    m_description = description;
-
-    clearStats();
-}
-
-CacheProfiler::~CacheProfiler()
-{
-}
-
-void
-CacheProfiler::printStats(ostream& out) const
-{
-    out << "Cache Stats: " << m_description << endl;
-    string description = "  " + m_description;
-
-    out << description << "_total_misses: " << m_misses << endl;
-    out << description << "_total_demand_misses: " << m_demand_misses << endl;
-    out << description << "_total_prefetches: " << m_prefetches << endl;
-    out << description << "_total_sw_prefetches: " << m_sw_prefetches << endl;
-    out << description << "_total_hw_prefetches: " << m_hw_prefetches << endl;
-    out << endl;
-
-    int requests = 0;
-
-    for (int i = 0; i < int(RubyRequestType_NUM); i++) {
-        requests += m_cacheRequestType[i];
-    }
-
-    for (int i = 0; i < int(GenericRequestType_NUM); i++) {
-        requests += m_genericRequestType[i];
-    }
-
-    assert(m_misses == requests);
-
-    if (requests > 0) {
-        for (int i = 0; i < int(RubyRequestType_NUM); i++) {
-            if (m_cacheRequestType[i] > 0) {
-                out << description << "_request_type_"
-                    << RubyRequestType_to_string(RubyRequestType(i))
-                    << ":   "
-                    << 100.0 * (double)m_cacheRequestType[i] /
-                    (double)requests
-                    << "%" << endl;
-            }
-        }
-
-        for (int i = 0; i < int(GenericRequestType_NUM); i++) {
-            if (m_genericRequestType[i] > 0) {
-                out << description << "_request_type_"
-                    << GenericRequestType_to_string(GenericRequestType(i))
-                    << ":   "
-                    << 100.0 * (double)m_genericRequestType[i] /
-                    (double)requests
-                    << "%" << endl;
-            }
-        }
-
-        out << endl;
-
-        for (int i = 0; i < RubyAccessMode_NUM; i++){
-            if (m_accessModeTypeHistogram[i] > 0) {
-                out << description << "_access_mode_type_"
-                    << (RubyAccessMode) i << ":   "
-                    << m_accessModeTypeHistogram[i] << "    "
-                    << 100.0 * m_accessModeTypeHistogram[i] / requests
-                    << "%" << endl;
-            }
-        }
-    }
-
-    out << endl;
-}
-
-void
-CacheProfiler::clearStats()
-{
-    for (int i = 0; i < int(RubyRequestType_NUM); i++) {
-        m_cacheRequestType[i] = 0;
-    }
-    for (int i = 0; i < int(GenericRequestType_NUM); i++) {
-        m_genericRequestType[i] = 0;
-    }
-    m_misses = 0;
-    m_demand_misses = 0;
-    m_prefetches = 0;
-    m_sw_prefetches = 0;
-    m_hw_prefetches = 0;
-    for (int i = 0; i < RubyAccessMode_NUM; i++) {
-        m_accessModeTypeHistogram[i] = 0;
-    }
-}
-
-void
-CacheProfiler::addCacheStatSample(RubyRequestType requestType,
-                                  RubyAccessMode accessType,
-                                  PrefetchBit pfBit)
-{
-    m_cacheRequestType[requestType]++;
-    addStatSample(accessType, pfBit);
-}
-
-void
-CacheProfiler::addGenericStatSample(GenericRequestType requestType,
-                                    RubyAccessMode accessType,
-                                    PrefetchBit pfBit)
-{
-    m_genericRequestType[requestType]++;
-    addStatSample(accessType, pfBit);
-}
-
-void
-CacheProfiler::addStatSample(RubyAccessMode accessType,
-                             PrefetchBit pfBit)
-{
-    m_misses++;
-
-    m_accessModeTypeHistogram[accessType]++;
-    if (pfBit == PrefetchBit_No) {
-        m_demand_misses++;
-    } else if (pfBit == PrefetchBit_Yes) {
-        m_prefetches++;
-        m_sw_prefetches++;
-    } else {
-        // must be L1_HW || L2_HW prefetch
-        m_prefetches++;
-        m_hw_prefetches++;
-    }
-}
diff -r d787467ae796 -r dd6c331371c1 src/mem/ruby/profiler/SConscript
--- a/src/mem/ruby/profiler/SConscript	Thu Jul 05 10:12:41 2012 -0500
+++ b/src/mem/ruby/profiler/SConscript	Thu Jul 05 10:14:31 2012 -0500
@@ -37,7 +37,6 @@
 
 Source('AccessTraceForAddress.cc')
 Source('AddressProfiler.cc')
-Source('CacheProfiler.cc')
 Source('MemCntrlProfiler.cc')
 Source('Profiler.cc')
 Source('StoreTrace.cc')
diff -r d787467ae796 -r dd6c331371c1 src/mem/ruby/system/CacheMemory.hh
--- a/src/mem/ruby/system/CacheMemory.hh	Thu Jul 05 10:12:41 2012 -0500
+++ b/src/mem/ruby/system/CacheMemory.hh	Thu Jul 05 10:14:31 2012 -0500
@@ -34,10 +34,10 @@
 #include <vector>
 
 #include "base/hashmap.hh"
+#include "base/statistics.hh"
 #include "mem/protocol/GenericRequestType.hh"
 #include "mem/protocol/RubyRequest.hh"
 #include "mem/ruby/common/DataBlock.hh"
-#include "mem/ruby/profiler/CacheProfiler.hh"
 #include "mem/ruby/recorder/CacheRecorder.hh"
 #include "mem/ruby/slicc_interface/AbstractCacheEntry.hh"
 #include "mem/ruby/slicc_interface/RubySlicc_ComponentMapping.hh"
@@ -110,8 +110,17 @@
     void print(std::ostream& out) const;
     void printData(std::ostream& out) const;
 
-    void clearStats() const;
-    void printStats(std::ostream& out) const;
+    void regStats();
+
+  public:
+    Stats::Scalar m_misses;
+    Stats::Scalar m_demand_misses;
+    Stats::Scalar m_prefetches;
+    Stats::Scalar m_sw_prefetches;
+    Stats::Scalar m_hw_prefetches;
+    Stats::Vector m_accessModeType;
+    Stats::Vector m_cacheRequestType;
+    Stats::Vector m_genericRequestType;
 
   private:
     // convert a Address to its location in the cache
@@ -126,6 +135,7 @@
     // Private copy constructor and assignment operator
     CacheMemory(const CacheMemory& obj);
     CacheMemory& operator=(const CacheMemory& obj);
+    void addStatSample(RubyAccessMode, PrefetchBit);
 
   private:
     const std::string m_cache_name;
@@ -141,8 +151,6 @@
 
     AbstractReplacementPolicy *m_replacementPolicy_ptr;
 
-    CacheProfiler* m_profiler_ptr;
-
     int m_cache_size;
     std::string m_policy;
     int m_cache_num_sets;
@@ -152,4 +160,3 @@
 };
 
 #endif // __MEM_RUBY_SYSTEM_CACHEMEMORY_HH__
-
diff -r d787467ae796 -r dd6c331371c1 src/mem/ruby/system/CacheMemory.cc
--- a/src/mem/ruby/system/CacheMemory.cc	Thu Jul 05 10:12:41 2012 -0500
+++ b/src/mem/ruby/system/CacheMemory.cc	Thu Jul 05 10:14:31 2012 -0500
@@ -56,7 +56,6 @@
     m_latency = p->latency;
     m_cache_assoc = p->assoc;
     m_policy = p->replacement_policy;
-    m_profiler_ptr = new CacheProfiler(name());
     m_start_index_bit = p->start_index_bit;
     m_is_instruction_only_cache = p->is_icache;
 }
@@ -92,7 +91,6 @@
 {
     if (m_replacementPolicy_ptr != NULL)
         delete m_replacementPolicy_ptr;
-    delete m_profiler_ptr;
     for (int i = 0; i < m_cache_num_sets; i++) {
         for (int j = 0; j < m_cache_assoc; j++) {
             delete m_cache[i][j];
@@ -326,9 +324,8 @@
 void
 CacheMemory::profileMiss(const RubyRequest& msg)
 {
-    m_profiler_ptr->addCacheStatSample(msg.getType(), 
-                                       msg.getAccessMode(),
-                                       msg.getPrefetch());
+    m_cacheRequestType[msg.getType()]++;
+    addStatSample(msg.getAccessMode(), msg.getPrefetch());
 }
 
 void
@@ -336,9 +333,26 @@
                                    RubyAccessMode accessType,
                                    PrefetchBit pfBit)
 {
-    m_profiler_ptr->addGenericStatSample(requestType, 
-                                         accessType, 
-                                         pfBit);
+    m_genericRequestType[requestType]++;
+    addStatSample(accessType, pfBit);
+}
+
+void
+CacheMemory::addStatSample(RubyAccessMode accessType, PrefetchBit pfBit)
+{
+    m_misses++;
+
+    m_accessModeType[accessType]++;
+    if (pfBit == PrefetchBit_No) {
+        m_demand_misses++;
+    } else if (pfBit == PrefetchBit_Yes) {
+        m_prefetches++;
+        m_sw_prefetches++;
+    } else {
+        // must be L1_HW || L2_HW prefetch
+        m_prefetches++;
+        m_hw_prefetches++;
+    }
 }
 
 void
@@ -406,18 +420,6 @@
 }
 
 void
-CacheMemory::clearStats() const
-{
-    m_profiler_ptr->clearStats();
-}
-
-void
-CacheMemory::printStats(ostream& out) const
-{
-    m_profiler_ptr->printStats(out);
-}
-
-void
 CacheMemory::setLocked(const Address& address, int context)
 {
     DPRINTF(RubyCache, "Setting Lock for addr: %x to %d\n", address, context);
@@ -451,3 +453,63 @@
     return m_cache[cacheSet][loc]->m_locked == context;
 }
 
+void
+CacheMemory::regStats()
+{
+    m_misses
+        .name(name() + ".total_misses")
+        .desc("Number of cache misses")
+        ;
+
+    m_demand_misses
+        .name(name() + ".total_demand_misses")
+        .desc("Number of demand misses")
+        ;
+
+    m_prefetches
+        .name(name() + ".total_prefetches")
+        .desc("Number of prefetches")
+        ;
+
+    m_sw_prefetches
+        .name(name() + ".total_sw_prefetches")
+        .desc("Number of software prefetches")
+        ;
+
+    m_hw_prefetches
+        .name(name() + ".total_hw_prefetches")
+        .desc("Number of hardware prefetches")
+        ;
+
+    m_accessModeType
+        .init(RubyRequestType_NUM)
+        .name(name() + ".access_mode")
+        .flags(Stats::pdf | Stats::total)
+        ;
+    for (int i = 0; i < RubyAccessMode_NUM; i++) {
+        m_accessModeType
+            .subname(i, RubyAccessMode_to_string(RubyAccessMode(i)));
+    }
+
+    m_cacheRequestType
+        .init(RubyRequestType_NUM)
+        .name(name() + ".request_type")
+        .flags(Stats::pdf | Stats::total)
+        ;
+
+    for (int i = 0; i < int(RubyRequestType_NUM); i++) {
+        m_cacheRequestType
+            .subname(i, RubyRequestType_to_string(RubyRequestType(i)));
+    }
+
+    m_genericRequestType
+        .init(GenericRequestType_NUM)
+        .name(name() + ".generic_request_type")
+        .flags(Stats::pdf | Stats::total)
+        ;
+
+    for (int i = 0; i < int(GenericRequestType_NUM); i++) {
+        m_genericRequestType
+            .subname(i, GenericRequestType_to_string(GenericRequestType(i)));
+    }
+}
diff -r d787467ae796 -r dd6c331371c1 src/mem/slicc/symbols/StateMachine.py
--- a/src/mem/slicc/symbols/StateMachine.py	Thu Jul 05 10:12:41 2012 -0500
+++ b/src/mem/slicc/symbols/StateMachine.py	Thu Jul 05 10:14:31 2012 -0500
@@ -834,8 +834,7 @@
         # them.  Print out these stats before dumping state transition stats.
         #
         for param in self.config_parameters:
-            if param.type_ast.type.ident == "CacheMemory" or \
-               param.type_ast.type.ident == "DirectoryMemory" or \
+            if param.type_ast.type.ident == "DirectoryMemory" or \
                    param.type_ast.type.ident == "MemoryControl":
                 assert(param.pointer)
                 code('    m_${{param.ident}}_ptr->printStats(out);')
@@ -853,8 +852,7 @@
         # them.  These stats must be cleared too.
         #
         for param in self.config_parameters:
-            if param.type_ast.type.ident == "CacheMemory" or \
-                   param.type_ast.type.ident == "MemoryControl":
+            if param.type_ast.type.ident == "MemoryControl":
                 assert(param.pointer)
                 code('    m_${{param.ident}}_ptr->clearStats();')