diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/arch/x86/interrupts.hh
--- a/src/arch/x86/interrupts.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/arch/x86/interrupts.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -89,7 +89,6 @@
      * Timing related stuff.
      */
     Tick latency;
-    Tick clock;
 
     class ApicTimerEvent : public Event
     {
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/arch/x86/interrupts.cc
--- a/src/arch/x86/interrupts.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/arch/x86/interrupts.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -619,7 +619,6 @@
 
 X86ISA::Interrupts::Interrupts(Params * p) :
     BasicPioDevice(p), IntDev(this, p->int_latency), latency(p->pio_latency), 
-    clock(0),
     apicTimerEvent(this),
     pendingSmi(false), smiVector(0),
     pendingNmi(false), nmiVector(0),
@@ -631,6 +630,8 @@
     intSlaveHandler(this, this, latency),
     intSlavePort(name() + ".int_slave", this, intSlaveHandler)
 {
+    // Override the default clock
+    clock = 0;
     pioSize = PageBytes;
     memset(regs, 0, sizeof(regs));
     //Set the local apic DFR to the flat model.
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/arch/x86/utility.cc
--- a/src/arch/x86/utility.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/arch/x86/utility.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -173,7 +173,9 @@
     interrupts->setRegNoEffect(APIC_ID, cpuId << 24);
 
     interrupts->setRegNoEffect(APIC_VERSION, (5 << 16) | 0x14);
-    
+
+    // @todo: Control the relative frequency, in this case 16:1, of
+    // the clocks in the Python code
     interrupts->setClock(tc->getCpuPtr()->ticks(16));
 
     // TODO Set the SMRAM base address (SMBASE) to 0x00030000
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/cpu/BaseCPU.py	Thu Jul 19 10:07:40 2012 +0100
@@ -145,9 +145,6 @@
     defer_registration = Param.Bool(False,
         "defer registration with system (for sampling)")
 
-    clock = Param.Clock('1t', "clock speed")
-    phase = Param.Latency('0ns', "clock phase")
-
     tracer = Param.InstTracer(default_tracer, "Instruction tracer")
 
     icache_port = MasterPort("Instruction Port")
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/cpu/base.hh
--- a/src/cpu/base.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/cpu/base.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -88,8 +88,7 @@
 class BaseCPU : public MemObject
 {
   protected:
-    // CPU's clock period in terms of the number of ticks of curTime.
-    Tick clock;
+
     // @todo remove me after debugging with legion done
     Tick instCnt;
     // every cpu has an id, put it in the base cpu
@@ -165,30 +164,11 @@
     BaseMasterPort &getMasterPort(const std::string &if_name,
                                   PortID idx = InvalidPortID);
 
-//    Tick currentTick;
-    inline Tick frequency() const { return SimClock::Frequency / clock; }
-    inline Tick ticks(int numCycles) const { return clock * numCycles; }
-    inline Tick curCycle() const { return curTick() / clock; }
-    inline Tick tickToCycles(Tick val) const { return val / clock; }
     inline void workItemBegin() { numWorkItemsStarted++; }
     inline void workItemEnd() { numWorkItemsCompleted++; }
     // @todo remove me after debugging with legion done
     Tick instCount() { return instCnt; }
 
-    /** The next cycle the CPU should be scheduled, given a cache
-     * access or quiesce event returning on this cycle.  This function
-     * may return curTick() if the CPU should run on the current cycle.
-     */
-    Tick nextCycle();
-
-    /** The next cycle the CPU should be scheduled, given a cache
-     * access or quiesce event returning on the given Tick.  This
-     * function may return curTick() if the CPU should run on the
-     * current cycle.
-     * @param begin_tick The tick that the event is completing on.
-     */
-    Tick nextCycle(Tick begin_tick);
-
     TheISA::MicrocodeRom microcodeRom;
 
   protected:
@@ -333,8 +313,6 @@
 
     System *system;
 
-    Tick phase;
-
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/cpu/base.cc
--- a/src/cpu/base.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/cpu/base.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -116,14 +116,13 @@
 
 BaseCPU::BaseCPU(Params *p, CpuHandler &instHandler,
                  CpuHandler &dataHandler, bool is_checker)
-    : MemObject(p), clock(p->clock), instCnt(0), _cpuId(p->cpu_id),
+    : MemObject(p), instCnt(0), _cpuId(p->cpu_id),
       _instMasterId(p->system->getMasterId(name() + ".inst")),
       _dataMasterId(p->system->getMasterId(name() + ".data")),
       icachePort(name() + ".icache_port", this, instHandler),
       dcachePort(name() + ".dcache_port", this, dataHandler),
       interrupts(p->interrupts),
-      numThreads(p->numThreads), system(p->system),
-      phase(p->phase)
+      numThreads(p->numThreads), system(p->system)
 {
 //    currentTick = curTick();
 
@@ -320,27 +319,6 @@
         return MemObject::getMasterPort(if_name, idx);
 }
 
-Tick
-BaseCPU::nextCycle()
-{
-    Tick next_tick = curTick() - phase + clock - 1;
-    next_tick -= (next_tick % clock);
-    next_tick += phase;
-    return next_tick;
-}
-
-Tick
-BaseCPU::nextCycle(Tick begin_tick)
-{
-    Tick next_tick = begin_tick;
-    if (next_tick % clock != 0)
-        next_tick = next_tick - (next_tick % clock) + clock;
-    next_tick += phase;
-
-    assert(next_tick >= curTick());
-    return next_tick;
-}
-
 void
 BaseCPU::registerThreadContexts()
 {
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/cpu/testers/memtest/memtest.hh
--- a/src/cpu/testers/memtest/memtest.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/cpu/testers/memtest/memtest.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -68,8 +68,6 @@
     // register statistics
     virtual void regStats();
 
-    inline Tick ticks(int numCycles) const { return numCycles; }
-
     // main simulation loop (one cycle)
     void tick();
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/cpu/testers/networktest/networktest.hh
--- a/src/cpu/testers/networktest/networktest.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/cpu/testers/networktest/networktest.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -63,8 +63,6 @@
 
     virtual void init();
 
-    inline Tick ticks(int numCycles) const { return numCycles; }
-
     // main simulation loop (one cycle)
     void tick();
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/CopyEngine.py
--- a/src/dev/CopyEngine.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/CopyEngine.py	Thu Jul 19 10:07:40 2012 +0100
@@ -52,8 +52,8 @@
     ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
     XferCap = Param.MemorySize('4kB', "Number of bits of transfer size that are supported")
 
-
-    clock = Param.Clock('500MHz', "Clock speed of the device")
+    # Override the default clock
+    clock = '500MHz'
     latBeforeBegin = Param.Latency('20ns', "Latency after a DMA command is seen before it's proccessed")
     latAfterCompletion = Param.Latency('20ns', "Latency after a DMA command is complete before it's reported as such")
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/Ethernet.py
--- a/src/dev/Ethernet.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/Ethernet.py	Thu Jul 19 10:07:40 2012 +0100
@@ -79,7 +79,8 @@
         "Number of enteries in the rx descriptor cache")
     tx_desc_cache_size = Param.Int(64,
         "Number of enteries in the rx descriptor cache")
-    clock = Param.Clock('500MHz', "Clock speed of the device")
+    # Override the default clock
+    clock = '500MHz'
     VendorID = 0x8086
     SubsystemID = 0x1008
     SubsystemVendorID = 0x8086
@@ -127,7 +128,8 @@
     hardware_address = Param.EthernetAddr(NextEthernetAddr,
         "Ethernet Hardware Address")
 
-    clock = Param.Clock('0ns', "State machine processor frequency")
+    # Override the default clock
+    clock = '0ns'
 
     dma_read_delay = Param.Latency('0us', "fixed delay for dma reads")
     dma_read_factor = Param.Latency('0us', "multiplier for dma reads")
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/arm/RealView.py
--- a/src/dev/arm/RealView.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/arm/RealView.py	Thu Jul 19 10:07:40 2012 +0100
@@ -118,7 +118,8 @@
     gic = Param.Gic(Parent.any, "Gic to use for interrupting")
     int_num_timer = Param.UInt32("Interrrupt number used per-cpu to GIC")
     int_num_watchdog = Param.UInt32("Interrupt number for per-cpu watchdog to GIC")
-    clock = Param.Clock('1GHz', "Clock speed at which the timer counts")
+    # Override the default clock
+    clock = '1GHz'
 
 class PL031(AmbaIntDevice):
     type = 'PL031'
@@ -134,7 +135,8 @@
 
 class Pl111(AmbaDmaDevice):
     type = 'Pl111'
-    clock = Param.Clock('24MHz', "Clock speed of the input")
+    # Override the default clock
+    clock = '24MHz'
     vnc   = Param.VncServer(Parent.any, "Vnc server for remote frame buffer display")
     amba_id = 0x00141111
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/arm/pl111.hh
--- a/src/dev/arm/pl111.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/arm/pl111.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -228,9 +228,6 @@
     /** Cursor masked interrupt status register - const */
     InterruptReg clcdCrsrMis;
 
-    /** Clock speed */
-    Tick clock;
-
     /** VNC server */
     VncServer *vncserver;
 
@@ -291,10 +288,6 @@
     /** DMA done event */
     void dmaDone();
 
-    /** Next cycle event */
-    Tick nextCycle();
-    Tick nextCycle(Tick beginTick);
-
     /** DMA framebuffer read event */
     EventWrapper<Pl111, &Pl111::readFramebuffer> readEvent;
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/arm/pl111.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -63,7 +63,7 @@
       lcdRis(0), lcdMis(0),
       clcdCrsrCtrl(0), clcdCrsrConfig(0), clcdCrsrPalette0(0),
       clcdCrsrPalette1(0), clcdCrsrXY(0), clcdCrsrClip(0), clcdCrsrImsc(0),
-      clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0), clock(p->clock),
+      clcdCrsrIcr(0), clcdCrsrRis(0), clcdCrsrMis(0),
       vncserver(p->vnc), bmp(NULL), width(LcdMaxWidth), height(LcdMaxHeight),
       bytesPerPixel(4), startTime(0), startAddr(0), maxAddr(0), curAddr(0),
       waterMark(0), dmaPendingNum(0), readEvent(this), fillFifoEvent(this),
@@ -512,26 +512,6 @@
         schedule(fillFifoEvent, nextCycle());
 }
 
-
-Tick
-Pl111::nextCycle()
-{
-    Tick nextTick = curTick() + clock - 1;
-    nextTick -= nextTick%clock;
-    return nextTick;
-}
-
-Tick
-Pl111::nextCycle(Tick beginTick)
-{
-    Tick nextTick = beginTick;
-    if (nextTick%clock!=0)
-        nextTick = nextTick - (nextTick%clock) + clock;
-
-    assert(nextTick >= curTick());
-    return nextTick;
-}
-
 void
 Pl111::serialize(std::ostream &os)
 {
@@ -586,7 +566,6 @@
     uint8_t clcdCrsrMis_serial = clcdCrsrMis;
     SERIALIZE_SCALAR(clcdCrsrMis_serial);
 
-    SERIALIZE_SCALAR(clock);
     SERIALIZE_SCALAR(height);
     SERIALIZE_SCALAR(width);
     SERIALIZE_SCALAR(bytesPerPixel);
@@ -689,7 +668,6 @@
     UNSERIALIZE_SCALAR(clcdCrsrMis_serial);
     clcdCrsrMis = clcdCrsrMis_serial;
 
-    UNSERIALIZE_SCALAR(clock);
     UNSERIALIZE_SCALAR(height);
     UNSERIALIZE_SCALAR(width);
     UNSERIALIZE_SCALAR(bytesPerPixel);
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/arm/timer_cpulocal.cc
--- a/src/dev/arm/timer_cpulocal.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/arm/timer_cpulocal.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -58,7 +58,7 @@
         localTimer[i].parent = this;
         localTimer[i].intNumTimer = p->int_num_timer;
         localTimer[i].intNumWatchdog = p->int_num_watchdog;
-        localTimer[i].clock = p->clock;
+        localTimer[i].clock = clock;
         localTimer[i].cpuNum = i;
     }
     pioSize = 0x38;
@@ -339,7 +339,6 @@
     DPRINTF(Checkpoint, "Serializing Arm CpuLocalTimer\n");
     SERIALIZE_SCALAR(intNumTimer);
     SERIALIZE_SCALAR(intNumWatchdog);
-    SERIALIZE_SCALAR(clock);
 
     uint32_t timer_control_serial = timerControl;
     uint32_t watchdog_control_serial = watchdogControl;
@@ -379,7 +378,6 @@
 
     UNSERIALIZE_SCALAR(intNumTimer);
     UNSERIALIZE_SCALAR(intNumWatchdog);
-    UNSERIALIZE_SCALAR(clock);
 
     uint32_t timer_control_serial;
     UNSERIALIZE_SCALAR(timer_control_serial);
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/i8254xGBe.hh
--- a/src/dev/i8254xGBe.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/i8254xGBe.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -523,9 +523,7 @@
 
     virtual EtherInt *getEthPort(const std::string &if_name, int idx);
 
-    Tick clock;
     Tick lastInterrupt;
-    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
     virtual Tick read(PacketPtr pkt);
     virtual Tick write(PacketPtr pkt);
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/i8254xGBe.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -67,7 +67,7 @@
       tadvEvent(this), tidvEvent(this), tickEvent(this), interEvent(this),
       rxDescCache(this, name()+".RxDesc", p->rx_desc_cache_size),
       txDescCache(this, name()+".TxDesc", p->tx_desc_cache_size),
-      clock(p->clock), lastInterrupt(0)
+      lastInterrupt(0)
 {
     etherInt = new IGbEInt(name() + ".int", this);
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/ns_gige.hh
--- a/src/dev/ns_gige.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/ns_gige.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -196,10 +196,6 @@
     ns_desc64 txDesc64;
     ns_desc64 rxDesc64;
 
-    /* state machine cycle time */
-    Tick clock;
-    inline Tick ticks(int numCycles) const { return numCycles * clock; }
-
     /* tx State Machine */
     TxState txState;
     bool txEnable;
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/ns_gige.cc
--- a/src/dev/ns_gige.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/ns_gige.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -99,7 +99,6 @@
       txFifo(p->tx_fifo_size), rxFifo(p->rx_fifo_size),
       txPacket(0), rxPacket(0), txPacketBufPtr(NULL), rxPacketBufPtr(NULL),
       txXferLen(0), rxXferLen(0), rxDmaFree(false), txDmaFree(false),
-      clock(p->clock),
       txState(txIdle), txEnable(false), CTDD(false), txHalt(false),
       txFragPtr(0), txDescCnt(0), txDmaState(dmaIdle), rxState(rxIdle),
       rxEnable(false), CRDD(false), rxPktBytes(0), rxHalt(false),
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/sinic.hh
--- a/src/dev/sinic.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/sinic.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -50,8 +50,6 @@
   protected:
     bool rxEnable;
     bool txEnable;
-    Tick clock;
-    inline Tick ticks(int numCycles) const { return numCycles * clock; }
 
   protected:
     Tick intrDelay;
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/dev/sinic.cc
--- a/src/dev/sinic.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/dev/sinic.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -78,7 +78,7 @@
 // Sinic PCI Device
 //
 Base::Base(const Params *p)
-    : PciDev(p), rxEnable(false), txEnable(false), clock(p->clock),
+    : PciDev(p), rxEnable(false), txEnable(false),
       intrDelay(p->intr_delay), intrTick(0), cpuIntrEnable(false),
       cpuPendingIntr(false), intrEvent(0), interface(NULL)
 {
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/Bus.py
--- a/src/mem/Bus.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/Bus.py	Thu Jul 19 10:07:40 2012 +0100
@@ -47,7 +47,8 @@
     abstract = True
     slave = VectorSlavePort("vector port for connecting masters")
     master = VectorMasterPort("vector port for connecting slaves")
-    clock = Param.Clock("1GHz", "bus clock speed")
+    # Override the default clock
+    clock = '1GHz'
     header_cycles = Param.Int(1, "cycles of overhead per transaction")
     width = Param.Int(8, "bus width (bytes)")
     block_size = Param.Int(64, "The default block size if not set by " \
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/MemObject.py
--- a/src/mem/MemObject.py	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/MemObject.py	Thu Jul 19 10:07:40 2012 +0100
@@ -26,8 +26,8 @@
 #
 # Authors: Ron Dreslinski
 
-from m5.SimObject import SimObject
+from ClockedObject import ClockedObject
 
-class MemObject(SimObject):
+class MemObject(ClockedObject):
     type = 'MemObject'
     abstract = True
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/bus.hh
--- a/src/mem/bus.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/bus.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -228,8 +228,6 @@
 
     };
 
-    /** the clock speed for the bus */
-    Tick clock;
     /** cycles of overhead per transaction */
     int headerCycles;
     /** the width of the bus in bytes */
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/bus.cc
--- a/src/mem/bus.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/bus.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -47,7 +47,6 @@
  * Definition of a bus object.
  */
 
-#include "base/intmath.hh"
 #include "base/misc.hh"
 #include "base/trace.hh"
 #include "debug/Bus.hh"
@@ -55,7 +54,7 @@
 #include "mem/bus.hh"
 
 BaseBus::BaseBus(const BaseBusParams *p)
-    : MemObject(p), clock(p->clock),
+    : MemObject(p),
       headerCycles(p->header_cycles), width(p->width),
       defaultPortID(InvalidPortID),
       useDefaultRange(p->use_default_range),
@@ -113,7 +112,7 @@
 {
     // determine the current time rounded to the closest following
     // clock edge
-    Tick now = divCeil(curTick(), clock) * clock;
+    Tick now = nextCycle();
 
     Tick headerTime = now + headerCycles * clock;
 
@@ -285,7 +284,7 @@
 
         // determine the current time rounded to the closest following
         // clock edge
-        Tick now = divCeil(curTick(), clock) * clock;
+        Tick now = bus.nextCycle();
 
         occupyLayer(now + clock);
     }
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/mem_object.hh
--- a/src/mem/mem_object.hh	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/mem_object.hh	Thu Jul 19 10:07:40 2012 +0100
@@ -51,13 +51,13 @@
 
 #include "mem/port.hh"
 #include "params/MemObject.hh"
-#include "sim/sim_object.hh"
+#include "sim/clocked_object.hh"
 
 /**
- * The MemObject class extends the SimObject with accessor functions
+ * The MemObject class extends the ClockedObject with accessor functions
  * to get its master and slave ports.
  */
-class MemObject : public SimObject
+class MemObject : public ClockedObject
 {
   public:
     typedef MemObjectParams Params;
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/mem/mem_object.cc
--- a/src/mem/mem_object.cc	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/mem/mem_object.cc	Thu Jul 19 10:07:40 2012 +0100
@@ -44,7 +44,7 @@
 #include "mem/mem_object.hh"
 
 MemObject::MemObject(const Params *params)
-    : SimObject(params)
+    : ClockedObject(params)
 {
 }
 
diff -r 7aa59ccc2d8e -r 89d2b9da0a82 src/sim/SConscript
--- a/src/sim/SConscript	Thu Jul 19 08:10:27 2012 +0100
+++ b/src/sim/SConscript	Thu Jul 19 10:07:40 2012 +0100
@@ -31,6 +31,7 @@
 Import('*')
 
 SimObject('BaseTLB.py')
+SimObject('ClockedObject.py')
 SimObject('Root.py')
 SimObject('InstTracer.py')