diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/arch/arm/ArmTLB.py --- a/src/arch/arm/ArmTLB.py Sat Jul 28 17:41:42 2012 +0100 +++ b/src/arch/arm/ArmTLB.py Sat Jul 28 18:13:20 2012 +0100 @@ -47,9 +47,6 @@ cxx_class = 'ArmISA::TableWalker' port = MasterPort("Port for TableWalker to do walk the translation with") sys = Param.System(Parent.any, "system object parameter") - min_backoff = Param.Tick(0, "Minimum backoff delay after failed send") - max_backoff = Param.Tick(100000, "Minimum backoff delay after failed send") - class ArmTLB(SimObject): type = 'ArmTLB' diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/arch/arm/table_walker.hh --- a/src/arch/arm/table_walker.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/arch/arm/table_walker.hh Sat Jul 28 18:13:20 2012 +0100 @@ -287,9 +287,8 @@ * A snooping DMA handler merely calls the construtor of * the DMA handler. */ - SnoopingDmaHandler(MemObject *dev, System *s, Tick min_backoff, - Tick max_backoff) : - DmaHandler(dev, s, min_backoff, max_backoff) + SnoopingDmaHandler(MemObject *dev, System *s) : + DmaHandler(dev, s) { } }; diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/arch/arm/table_walker.cc --- a/src/arch/arm/table_walker.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/arch/arm/table_walker.cc Sat Jul 28 18:13:20 2012 +0100 @@ -51,8 +51,7 @@ TableWalker::TableWalker(const Params *p) : MemObject(p), - handler(this, params()->sys, params()->min_backoff, - params()->max_backoff), + handler(this, params()->sys), port(this->name() + "-tablewalker-port", this, handler), tlb(NULL), currState(NULL), pending(false), masterId(p->sys->getMasterId(name())), diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/arch/x86/pagetable_walker.cc --- a/src/arch/x86/pagetable_walker.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/arch/x86/pagetable_walker.cc Sat Jul 28 18:13:20 2012 +0100 @@ -561,63 +561,49 @@ Walker::WalkerState::recvPacket(PacketPtr pkt) { assert(pkt->isResponse()); - if (!pkt->wasNacked()) { - assert(inflight); - assert(state == Waiting); - assert(!read); - inflight--; - if (pkt->isRead()) { - state = nextState; - nextState = Ready; - PacketPtr write = NULL; - read = pkt; - timingFault = stepWalk(write); - state = Waiting; - assert(timingFault == NoFault || read == NULL); - if (write) { - writes.push_back(write); - } - sendPackets(); + assert(inflight); + assert(state == Waiting); + assert(!read); + inflight--; + if (pkt->isRead()) { + state = nextState; + nextState = Ready; + PacketPtr write = NULL; + read = pkt; + timingFault = stepWalk(write); + state = Waiting; + assert(timingFault == NoFault || read == NULL); + if (write) { + writes.push_back(write); + } + sendPackets(); + } else { + sendPackets(); + } + if (inflight == 0 && read == NULL && writes.size() == 0) { + state = Ready; + nextState = Waiting; + if (timingFault == NoFault) { + /* + * Finish the translation. Now that we now the right entry is + * in the TLB, this should work with no memory accesses. + * There could be new faults unrelated to the table walk like + * permissions violations, so we'll need the return value as + * well. + */ + bool delayedResponse; + Fault fault = walker->tlb->translate(req, tc, NULL, mode, + delayedResponse, true); + assert(!delayedResponse); + // Let the CPU continue. + translation->finish(fault, req, tc, mode); } else { - sendPackets(); + // There was a fault during the walk. Let the CPU know. + translation->finish(timingFault, req, tc, mode); } - if (inflight == 0 && read == NULL && writes.size() == 0) { - state = Ready; - nextState = Waiting; - if (timingFault == NoFault) { - /* - * Finish the translation. Now that we now the right entry is - * in the TLB, this should work with no memory accesses. - * There could be new faults unrelated to the table walk like - * permissions violations, so we'll need the return value as - * well. - */ - bool delayedResponse; - Fault fault = walker->tlb->translate(req, tc, NULL, mode, - delayedResponse, true); - assert(!delayedResponse); - // Let the CPU continue. - translation->finish(fault, req, tc, mode); - } else { - // There was a fault during the walk. Let the CPU know. - translation->finish(timingFault, req, tc, mode); - } - return true; - } - } else { - DPRINTF(PageTableWalker, "Request was nacked. Entering retry state\n"); - pkt->reinitNacked(); - if (!walker->sendTiming(this, pkt)) { - inflight--; - retrying = true; - if (pkt->isWrite()) { - writes.push_back(pkt); - } else { - assert(!read); - read = pkt; - } - } + return true; } + return false; } diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/cpu/o3/fetch_impl.hh --- a/src/cpu/o3/fetch_impl.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/cpu/o3/fetch_impl.hh Sat Jul 28 18:13:20 2012 +0100 @@ -360,8 +360,6 @@ DPRINTF(Fetch, "[tid:%u] Waking up from cache miss.\n", tid); - assert(!pkt->wasNacked()); - // Only change the status if it's still waiting on the icache access // to return. if (fetchStatus[tid] != IcacheWaitResponse || diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/cpu/o3/lsq_unit_impl.hh --- a/src/cpu/o3/lsq_unit_impl.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/cpu/o3/lsq_unit_impl.hh Sat Jul 28 18:13:20 2012 +0100 @@ -95,8 +95,6 @@ //iewStage->ldstQueue.removeMSHR(inst->threadNumber,inst->seqNum); - assert(!pkt->wasNacked()); - // If this is a split access, wait until all packets are received. if (TheISA::HasUnalignedMemAcc && !state->complete()) { delete pkt->req; diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/cpu/simple/timing.cc --- a/src/cpu/simple/timing.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/cpu/simple/timing.cc Sat Jul 28 18:13:20 2012 +0100 @@ -713,25 +713,14 @@ bool TimingSimpleCPU::IcacheHandler::recvTimingResp(PacketPtr pkt) { - if (!pkt->wasNacked()) { - DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); - // delay processing of returned data until next CPU clock edge - Tick next_tick = cpu->nextCycle(); + DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); + // delay processing of returned data until next CPU clock edge + Tick next_tick = cpu->nextCycle(); - if (next_tick == curTick()) - cpu->completeIfetch(pkt); - else - tickEvent.schedule(pkt, next_tick); - - return true; - } else { - assert(cpu->_status == IcacheWaitResponse); - pkt->reinitNacked(); - if (!sendTimingReq(pkt)) { - cpu->_status = IcacheRetry; - cpu->ifetch_pkt = pkt; - } - } + if (next_tick == curTick()) + cpu->completeIfetch(pkt); + else + tickEvent.schedule(pkt, next_tick); return true; } @@ -833,32 +822,21 @@ bool TimingSimpleCPU::DcacheHandler::recvTimingResp(PacketPtr pkt) { - if (!pkt->wasNacked()) { - // delay processing of returned data until next CPU clock edge - Tick next_tick = cpu->nextCycle(); + // delay processing of returned data until next CPU clock edge + Tick next_tick = cpu->nextCycle(); - if (next_tick == curTick()) { - cpu->completeDataAccess(pkt); + if (next_tick == curTick()) { + cpu->completeDataAccess(pkt); + } else { + if (!tickEvent.scheduled()) { + tickEvent.schedule(pkt, next_tick); } else { - if (!tickEvent.scheduled()) { - tickEvent.schedule(pkt, next_tick); - } else { - // In the case of a split transaction and a cache that is - // faster than a CPU we could get two responses before - // next_tick expires - if (!retryEvent.scheduled()) - cpu->schedule(retryEvent, next_tick); - return false; - } - } - - return true; - } else { - assert(cpu->_status == DcacheWaitResponse); - pkt->reinitNacked(); - if (!sendTimingReq(pkt)) { - cpu->_status = DcacheRetry; - cpu->dcache_pkt = pkt; + // In the case of a split transaction and a cache that is + // faster than a CPU we could get two responses before + // next_tick expires + if (!retryEvent.scheduled()) + cpu->schedule(retryEvent, next_tick); + return false; } } diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/dev/Device.py --- a/src/dev/Device.py Sat Jul 28 17:41:42 2012 +0100 +++ b/src/dev/Device.py Sat Jul 28 18:13:20 2012 +0100 @@ -46,11 +46,6 @@ type = 'DmaDevice' abstract = True dma = MasterPort("DMA port") - min_backoff_delay = Param.Latency('4ns', - "min time between a nack packet being received and the next request made by the device") - max_backoff_delay = Param.Latency('10us', - "max time between a nack packet being received and the next request made by the device") - class IsaFake(BasicPioDevice): diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/dev/copy_engine.cc --- a/src/dev/copy_engine.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/dev/copy_engine.cc Sat Jul 28 18:13:20 2012 +0100 @@ -77,9 +77,7 @@ CopyEngine::CopyEngineChannel::CopyEngineChannel(CopyEngine *_ce, int cid) - : ceHandler(_ce, _ce->sys, - _ce->params()->min_backoff_delay, - _ce->params()->max_backoff_delay), + : ceHandler(_ce, _ce->sys), cePort(_ce->name() + "-dma", _ce, ceHandler), ce(_ce), channelId(cid), busy(false), underReset(false), refreshNext(false), latBeforeBegin(ce->params()->latBeforeBegin), diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/dev/dma_device.hh --- a/src/dev/dma_device.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/dev/dma_device.hh Sat Jul 28 18:13:20 2012 +0100 @@ -87,16 +87,6 @@ * here.*/ Event *drainEvent; - /** time to wait between sending another packet, increases as NACKs are - * recived, decreases as responses are recived. */ - Tick backoffTime; - - /** Minimum time that device should back off for after failed sendTiming */ - Tick minBackoffDelay; - - /** Maximum time that device should back off for after failed sendTiming */ - Tick maxBackoffDelay; - /** If the port is currently waiting for a retry before it can send whatever * it is that it's sending. */ bool inRetry; @@ -108,12 +98,8 @@ void queueDma(PacketPtr pkt, bool front = false); void sendDma(); - /** event to give us a kick every time we backoff time is reached. */ - EventWrapper backoffEvent; - public: - DmaHandler(MemObject *dev, System *s, Tick min_backoff, - Tick max_backoff); + DmaHandler(MemObject *dev, System *s); void dmaAction(Packet::Command cmd, Addr addr, int size, Event *event, uint8_t *data, Tick delay, Request::Flags flag = 0); diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/dev/dma_device.cc --- a/src/dev/dma_device.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/dev/dma_device.cc Sat Jul 28 18:13:20 2012 +0100 @@ -46,37 +46,18 @@ #include "dev/dma_device.hh" #include "sim/system.hh" -DmaHandler::DmaHandler(MemObject *dev, System *s, Tick min_backoff, - Tick max_backoff) +DmaHandler::DmaHandler(MemObject *dev, System *s) : device(dev), sys(s), masterId(s->getMasterId(dev->name())), pendingCount(0), drainEvent(NULL), - backoffTime(0), minBackoffDelay(min_backoff), - maxBackoffDelay(max_backoff), inRetry(false), - backoffEvent(this) + inRetry(false) { } bool DmaHandler::recvTimingResp(PacketPtr pkt) { - if (pkt->wasNacked()) { - DPRINTF(DMA, "Received nacked %s addr %#x\n", - pkt->cmdString(), pkt->getAddr()); - - if (backoffTime < minBackoffDelay) - backoffTime = minBackoffDelay; - else if (backoffTime < maxBackoffDelay) - backoffTime <<= 1; - - device->reschedule(backoffEvent, curTick() + backoffTime, true); - - DPRINTF(DMA, "Backoff time set to %d ticks\n", backoffTime); - - pkt->reinitNacked(); - queueDma(pkt, true); - } else if (pkt->senderState) { + if (pkt->senderState) { DmaReqState *state; - backoffTime >>= 2; DPRINTF(DMA, "Received response %s addr %#x size %#x\n", pkt->cmdString(), pkt->getAddr(), pkt->req->getSize()); @@ -116,8 +97,7 @@ } DmaDevice::DmaDevice(const Params *p) - : PioDevice(p), dmaHandler(this, sys, params()->min_backoff_delay, - params()->max_backoff_delay), + : PioDevice(p), dmaHandler(this, sys), dmaPort(this->name() + ".dma", this, dmaHandler) { } @@ -168,16 +148,10 @@ inRetry = true; DPRINTF(DMA, "-- Failed, queued\n"); } - } while (!backoffTime && result && transmitList.size()); + } while (result && transmitList.size()); - if (transmitList.size() && backoffTime && !inRetry) { - DPRINTF(DMA, "Scheduling backoff for %d\n", curTick()+backoffTime); - if (!backoffEvent.scheduled()) - device->schedule(backoffEvent, backoffTime + curTick()); - } - DPRINTF(DMA, "TransmitList: %d, backoffTime: %d inRetry: %d es: %d\n", - transmitList.size(), backoffTime, inRetry, - backoffEvent.scheduled()); + DPRINTF(DMA, "TransmitList: %d, inRetry: %d\n", + transmitList.size(), inRetry); } void @@ -234,8 +208,8 @@ Enums::MemoryMode state = sys->getMemoryMode(); if (state == Enums::timing) { - if (backoffEvent.scheduled() || inRetry) { - DPRINTF(DMA, "Can't send immediately, waiting for retry or backoff timer\n"); + if (inRetry) { + DPRINTF(DMA, "Can't send immediately, waiting for retry\n"); return; } @@ -252,14 +226,7 @@ inRetry = true; DPRINTF(DMA, "-- Failed: queued\n"); } - } while (result && !backoffTime && transmitList.size()); - - if (transmitList.size() && backoffTime && !inRetry && - !backoffEvent.scheduled()) { - DPRINTF(DMA, "-- Scheduling backoff timer for %d\n", - backoffTime+curTick()); - device->schedule(backoffEvent, backoffTime + curTick()); - } + } while (result && transmitList.size()); } else if (state == Enums::atomic) { transmitList.pop_front(); diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/mem/cache/cache_impl.hh --- a/src/mem/cache/cache_impl.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/mem/cache/cache_impl.hh Sat Jul 28 18:13:20 2012 +0100 @@ -689,8 +689,6 @@ DPRINTF(Cache, "Receive response: %s for addr %x in state %i\n", bus_pkt->cmdString(), bus_pkt->getAddr(), old_state); - assert(!bus_pkt->wasNacked()); - // If packet was a forward, the response (if any) is already // in place in the bus_pkt == pkt structure, so we don't need // to do anything. Otherwise, use the separate bus_pkt to @@ -820,12 +818,6 @@ assert(mshr); - if (pkt->wasNacked()) { - //pkt->reinitFromRequest(); - warn("NACKs from devices not connected to the same bus " - "not implemented\n"); - return; - } if (is_error) { DPRINTF(Cache, "Cache received packet with error for address %x, " "cmd: %s\n", pkt->getAddr(), pkt->cmdString()); @@ -1642,12 +1634,6 @@ bool Cache::MemSideHandler::recvTimingResp(PacketPtr pkt) { - // this needs to be fixed so that the cache updates the mshr and sends the - // packet back out on the link, but it probably won't happen so until this - // gets fixed, just panic when it does - if (pkt->wasNacked()) - panic("Need to implement cache resending nacked packets!\n"); - cache->handleResponse(pkt); return true; } diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/mem/packet.hh --- a/src/mem/packet.hh Sat Jul 28 17:41:42 2012 +0100 +++ b/src/mem/packet.hh Sat Jul 28 18:13:20 2012 +0100 @@ -120,7 +120,6 @@ // @TODO these should be classified as responses rather than // requests; coding them as requests initially for backwards // compatibility - NetworkNackError, // nacked at network layer (not by protocol) InvalidDestError, // packet dest field invalid BadAddressError, // memory address invalid FunctionalReadError, // unable to fulfill functional read @@ -466,20 +465,12 @@ // their encoding keeps changing (from result field to command // field, etc.) void - setNacked() - { - assert(isResponse()); - cmd = MemCmd::NetworkNackError; - } - - void setBadAddress() { assert(isResponse()); cmd = MemCmd::BadAddressError; } - bool wasNacked() const { return cmd == MemCmd::NetworkNackError; } bool hadBadAddress() const { return cmd == MemCmd::BadAddressError; } void copyError(Packet *pkt) { assert(pkt->isError()); cmd = pkt->cmd; } @@ -669,20 +660,6 @@ } } - /** - * Take a request packet that has been returned as NACKED and - * modify it so that it can be sent out again. Only packets that - * need a response can be NACKED, so verify that that is true. - */ - void - reinitNacked() - { - assert(wasNacked()); - cmd = origCmd; - assert(needsResponse()); - clearDest(); - } - void setSize(unsigned size) { diff -r 2ca2cdf7ef3d -r 85d0fc326753 src/mem/packet.cc --- a/src/mem/packet.cc Sat Jul 28 17:41:42 2012 +0100 +++ b/src/mem/packet.cc Sat Jul 28 18:13:20 2012 +0100 @@ -154,8 +154,6 @@ MessageResp, "MessageReq" }, /* IntResp -- for interrupts */ { SET2(IsWrite, IsResponse), InvalidCmd, "MessageResp" }, - /* NetworkNackError -- nacked at network layer (not by protocol) */ - { SET2(IsResponse, IsError), InvalidCmd, "NetworkNackError" }, /* InvalidDestError -- packet dest field invalid */ { SET2(IsResponse, IsError), InvalidCmd, "InvalidDestError" }, /* BadAddressError -- memory address invalid */