diff -r 6121b6dcad93 -r 10fd4f94efa4 src/arch/arm/table_walker.cc
--- a/src/arch/arm/table_walker.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/arch/arm/table_walker.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -740,7 +740,7 @@
 TableWalker::nextWalk(ThreadContext *tc)
 {
     if (pendingQueue.size())
-        schedule(doProcessEvent, tc->getCpuPtr()->nextCycle(curTick()+1));
+        schedule(doProcessEvent, tc->getCpuPtr()->clockEdge(1));
 }
 
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/arch/x86/mmapped_ipr.hh
--- a/src/arch/x86/mmapped_ipr.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/arch/x86/mmapped_ipr.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -62,7 +62,7 @@
         // Make sure we don't trot off the end of data.
         assert(offset + pkt->getSize() <= sizeof(MiscReg));
         pkt->setData(((uint8_t *)&data) + offset);
-        return xc->getCpuPtr()->ticks(1);
+        return 1;
     }
 
     inline Tick
@@ -76,7 +76,7 @@
         assert(offset + pkt->getSize() <= sizeof(MiscReg));
         pkt->writeData(((uint8_t *)&data) + offset);
         xc->setMiscReg(index, gtoh(data));
-        return xc->getCpuPtr()->ticks(1);
+        return 1;
     }
 }
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/base.cc
--- a/src/cpu/base.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/base.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -91,7 +91,7 @@
 {
     Counter temp = cpu->totalOps();
 #ifndef NDEBUG
-    double ipc = double(temp - lastNumInst) / (_interval / cpu->ticks(1));
+    double ipc = double(temp - lastNumInst) / (_interval / cpu->clockPeriod());
 
     DPRINTFN("%s progress event, total committed:%i, progress insts committed: "
              "%lli, IPC: %0.8d\n", cpu->name(), temp, temp - lastNumInst,
@@ -266,9 +266,7 @@
     }
 
     if (params()->progress_interval) {
-        Tick num_ticks = ticks(params()->progress_interval);
-
-        new CPUProgressEvent(this, num_ticks);
+        new CPUProgressEvent(this, params()->progress_interval);
     }
 }
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/inorder/cpu.hh
--- a/src/cpu/inorder/cpu.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/inorder/cpu.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -198,7 +198,7 @@
     void scheduleTickEvent(int delay)
     {
         assert(!tickEvent.scheduled() || tickEvent.squashed());
-        reschedule(&tickEvent, nextCycle(curTick() + ticks(delay)), true);
+        reschedule(&tickEvent, clockEdge(delay), true);
     }
 
     /** Unschedule tick event, regardless of its current state. */
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/inorder/cpu.cc
--- a/src/cpu/inorder/cpu.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/inorder/cpu.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -210,7 +210,7 @@
 InOrderCPU::CPUEvent::scheduleEvent(int delay)
 {
     assert(!scheduled() || squashed());
-    cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
+    cpu->reschedule(this, cpu->clockEdge(delay), true);
 }
 
 void
@@ -399,7 +399,7 @@
     frontEndSked = createFrontEndSked();
     faultSked = createFaultSked();
 
-    lastRunningCycle = curTick();
+    lastRunningCycle = curCycle();
 
     lockAddr = 0;
     lockFlag = false;
@@ -759,17 +759,17 @@
     if (!tickEvent.scheduled()) {
         if (_status == SwitchedOut) {
             // increment stat
-            lastRunningCycle = curTick();
+            lastRunningCycle = curCycle();
         } else if (!activityRec.active()) {
             DPRINTF(InOrderCPU, "sleeping CPU.\n");
-            lastRunningCycle = curTick();
+            lastRunningCycle = curCycle();
             timesIdled++;
         } else {
             //Tick next_tick = curTick() + cycles(1);
             //tickEvent.schedule(next_tick);
-            schedule(&tickEvent, nextCycle(curTick() + 1));
+            schedule(&tickEvent, clockEdge(1));
             DPRINTF(InOrderCPU, "Scheduled CPU for next tick @ %i.\n", 
-                    nextCycle(curTick() + 1));
+                    clockEdge(1));
         }
     }
 
@@ -957,15 +957,10 @@
     CPUEvent *cpu_event = new CPUEvent(this, c_event, fault, tid, inst,
                                        event_pri);
 
-    Tick sked_tick = nextCycle(curTick() + ticks(delay));
-    if (delay >= 0) {
-        DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
-                eventNames[c_event], curTick() + delay, tid);
-        schedule(cpu_event, sked_tick);
-    } else {
-        cpu_event->process();
-        cpuEventRemoveList.push(cpu_event);
-    }
+    Tick sked_tick = clockEdge(delay);
+    DPRINTF(InOrderCPU, "Scheduling CPU Event (%s) for cycle %i, [tid:%i].\n",
+            eventNames[c_event], curTick() + delay, tid);
+    schedule(cpu_event, sked_tick);
 
     // Broadcast event to the Resource Pool
     // Need to reset tid just in case this is a dummy instruction
@@ -1694,7 +1689,9 @@
 
     DPRINTF(Activity, "Waking up CPU\n");
 
-    Tick extra_cycles = tickToCycles((curTick() - 1) - lastRunningCycle);
+    Tick extra_cycles = curCycle() - lastRunningCycle;
+    if (extra_cycles != 0)
+        --extra_cycles;
 
     idleCycles += extra_cycles;    
     for (int stage_num = 0; stage_num < NumStages; stage_num++) {
@@ -1703,7 +1700,7 @@
 
     numCycles += extra_cycles;
 
-    schedule(&tickEvent, nextCycle(curTick()));
+    schedule(&tickEvent, nextCycle());
 }
 
 // Lots of copied full system code...place into BaseCPU class?
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/inorder/resource.cc
--- a/src/cpu/inorder/resource.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/inorder/resource.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -372,7 +372,7 @@
 void
 Resource::scheduleExecution(int slot_num)
 {
-    if (latency >= 1) {
+    if (latency > 0) {
         scheduleEvent(slot_num, latency);
     } else {
         execute(slot_num);
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/inorder/resource_pool.cc
--- a/src/cpu/inorder/resource_pool.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/inorder/resource_pool.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -238,7 +238,7 @@
 {
     assert(delay >= 0);
 
-    Tick when = cpu->nextCycle(curTick() + cpu->ticks(delay));
+    Tick when = cpu->clockEdge(delay);
 
     switch ((int)e_type)
     {
@@ -460,7 +460,7 @@
 {
     InOrderCPU *cpu = resPool->cpu;
     assert(!scheduled() || squashed());
-    cpu->reschedule(this, cpu->nextCycle(curTick() + cpu->ticks(delay)), true);
+    cpu->reschedule(this, cpu->clockEdge(delay), true);
 }
 
 /** Unschedule resource event, regardless of its current state. */
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/O3CPU.py	Fri Aug 03 12:55:33 2012 +0100
@@ -76,8 +76,8 @@
     renameToROBDelay = Param.Unsigned(1, "Rename to reorder buffer delay")
     commitWidth = Param.Unsigned(8, "Commit width")
     squashWidth = Param.Unsigned(8, "Squash width")
-    trapLatency = Param.Tick(13, "Trap latency")
-    fetchTrapLatency = Param.Tick(1, "Fetch trap latency")
+    trapLatency = Param.Unsigned(13, "Trap latency")
+    fetchTrapLatency = Param.Unsigned(1, "Fetch trap latency")
 
     backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
     forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/commit.hh
--- a/src/cpu/o3/commit.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/commit.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -409,7 +409,7 @@
     /** The latency to handle a trap.  Used when scheduling trap
      * squash event.
      */
-    Tick trapLatency;
+    uint trapLatency;
 
     /** The interrupt fault. */
     Fault interrupt;
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/commit_impl.hh
--- a/src/cpu/o3/commit_impl.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/commit_impl.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -374,7 +374,6 @@
     cpu->activateStage(O3CPU::CommitIdx);
 
     cpu->activityThisCycle();
-    trapLatency = cpu->ticks(trapLatency);
 }
 
 template <class Impl>
@@ -509,7 +508,7 @@
 
     TrapEvent *trap = new TrapEvent(this, tid);
 
-    cpu->schedule(trap, curTick() + trapLatency);
+    cpu->schedule(trap, cpu->clockEdge(trapLatency));
     trapInFlight[tid] = true;
     thread[tid]->trapPending = true;
 }
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/cpu.hh
--- a/src/cpu/o3/cpu.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/cpu.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -211,9 +211,9 @@
     void scheduleTickEvent(int delay)
     {
         if (tickEvent.squashed())
-            reschedule(tickEvent, nextCycle(curTick() + ticks(delay)));
+            reschedule(tickEvent, clockEdge(delay));
         else if (!tickEvent.scheduled())
-            schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
+            schedule(tickEvent, clockEdge(delay));
     }
 
     /** Unschedule tick event, regardless of its current state. */
@@ -253,9 +253,9 @@
         // Schedule thread to activate, regardless of its current state.
         if (activateThreadEvent[tid].squashed())
             reschedule(activateThreadEvent[tid],
-                nextCycle(curTick() + ticks(delay)));
+                       clockEdge(delay));
         else if (!activateThreadEvent[tid].scheduled()) {
-            Tick when = nextCycle(curTick() + ticks(delay));
+            Tick when = clockEdge(delay);
 
             // Check if the deallocateEvent is also scheduled, and make
             // sure they do not happen at same time causing a sleep that
@@ -316,10 +316,10 @@
         // Schedule thread to activate, regardless of its current state.
         if (deallocateContextEvent[tid].squashed())
             reschedule(deallocateContextEvent[tid],
-                nextCycle(curTick() + ticks(delay)));
+                       clockEdge(delay));
         else if (!deallocateContextEvent[tid].scheduled())
             schedule(deallocateContextEvent[tid],
-                nextCycle(curTick() + ticks(delay)));
+                     clockEdge(delay));
     }
 
     /** Unschedule thread deallocation in CPU */
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/cpu.cc
--- a/src/cpu/o3/cpu.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/cpu.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -386,7 +386,7 @@
     // Setup the ROB for whichever stages need it.
     commit.setROB(&rob);
 
-    lastRunningCycle = curTick();
+    lastRunningCycle = curCycle();
 
     lastActivatedCycle = 0;
 #if 0
@@ -623,13 +623,13 @@
             getState() == SimObject::Drained) {
             DPRINTF(O3CPU, "Switched out!\n");
             // increment stat
-            lastRunningCycle = curTick();
+            lastRunningCycle = curCycle();
         } else if (!activityRec.active() || _status == Idle) {
             DPRINTF(O3CPU, "Idle!\n");
-            lastRunningCycle = curTick();
+            lastRunningCycle = curCycle();
             timesIdled++;
         } else {
-            schedule(tickEvent, nextCycle(curTick() + ticks(1)));
+            schedule(tickEvent, clockEdge(1));
             DPRINTF(O3CPU, "Scheduling next tick!\n");
         }
     }
@@ -762,7 +762,10 @@
         activityRec.activity();
         fetch.wakeFromQuiesce();
 
-        quiesceCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+        Tick cycles = curCycle() - lastRunningCycle;
+        if (cycles != 0)
+            --cycles;
+        quiesceCycles += cycles;
 
         lastActivatedCycle = curTick();
 
@@ -801,7 +804,7 @@
         unscheduleTickEvent();
 
     DPRINTF(Quiesce, "Suspending Context\n");
-    lastRunningCycle = curTick();
+    lastRunningCycle = curCycle();
     _status = Idle;
 }
 
@@ -1269,7 +1272,7 @@
     if (!tickEvent.scheduled())
         schedule(tickEvent, nextCycle());
 
-    lastRunningCycle = curTick();
+    lastRunningCycle = curCycle();
 }
 
 template <class Impl>
@@ -1663,8 +1666,11 @@
 
     DPRINTF(Activity, "Waking up CPU\n");
 
-    idleCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
-    numCycles += tickToCycles((curTick() - 1) - lastRunningCycle);
+    Tick cycles = curCycle() - lastRunningCycle;
+    if (cycles != 0)
+        --cycles;
+    idleCycles += cycles;
+    numCycles += cycles;
 
     schedule(tickEvent, nextCycle());
 }
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/fetch_impl.hh
--- a/src/cpu/o3/fetch_impl.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/fetch_impl.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -645,7 +645,7 @@
             assert(!finishTranslationEvent.scheduled());
             finishTranslationEvent.setFault(fault);
             finishTranslationEvent.setReq(mem_req);
-            cpu->schedule(finishTranslationEvent, cpu->nextCycle(curTick() + cpu->ticks(1)));
+            cpu->schedule(finishTranslationEvent, cpu->clockEdge(1));
             return;
         }
         DPRINTF(Fetch, "[tid:%i] Got back req with addr %#x but expected %#x\n",
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/inst_queue_impl.hh
--- a/src/cpu/o3/inst_queue_impl.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/inst_queue_impl.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -828,7 +828,7 @@
                 FUCompletion *execution = new FUCompletion(issuing_inst,
                                                            idx, this);
 
-                cpu->schedule(execution, curTick() + cpu->ticks(op_latency - 1));
+                cpu->schedule(execution, cpu->clockEdge(op_latency - 1));
 
                 // @todo: Enforce that issue_latency == 1 or op_latency
                 if (issue_latency > 1) {
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/o3/lsq_unit.hh
--- a/src/cpu/o3/lsq_unit.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/o3/lsq_unit.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -624,7 +624,7 @@
             delete snd_data_pkt;
         }
         WritebackEvent *wb = new WritebackEvent(load_inst, data_pkt, this);
-        cpu->schedule(wb, curTick() + delay);
+        cpu->schedule(wb, cpu->clockEdge(delay));
         return NoFault;
     }
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/simple/atomic.cc
--- a/src/cpu/simple/atomic.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/simple/atomic.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -207,10 +207,10 @@
     assert(!tickEvent.scheduled());
 
     notIdleFraction++;
-    numCycles += tickToCycles(thread->lastActivate - thread->lastSuspend);
+    numCycles += tickToCycle(thread->lastActivate - thread->lastSuspend);
 
     //Make sure ticks are still on multiples of cycles
-    schedule(tickEvent, nextCycle(curTick() + ticks(delay)));
+    schedule(tickEvent, clockEdge(delay));
     _status = Running;
 }
 
@@ -517,7 +517,7 @@
                 stall_ticks += dcache_latency;
 
             if (stall_ticks) {
-                Tick stall_cycles = stall_ticks / ticks(1);
+                Tick stall_cycles = stall_ticks / clockPeriod();
                 Tick aligned_stall_ticks = ticks(stall_cycles);
 
                 if (aligned_stall_ticks < stall_ticks)
@@ -532,8 +532,8 @@
     }
 
     // instruction takes at least one cycle
-    if (latency < ticks(1))
-        latency = ticks(1);
+    if (latency < clockPeriod())
+        latency = clockPeriod();
 
     if (_status != Idle)
         schedule(tickEvent, curTick() + latency);
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/simple/timing.hh
--- a/src/cpu/simple/timing.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/simple/timing.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -244,7 +244,7 @@
     PacketPtr ifetch_pkt;
     PacketPtr dcache_pkt;
 
-    Tick previousTick;
+    Tick previousCycle;
 
   public:
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/simple/timing.cc
--- a/src/cpu/simple/timing.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/simple/timing.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -87,13 +87,10 @@
 TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
     : BaseSimpleCPU(p, icacheHandler, dcacheHandler),
       fetchTranslation(this), icacheHandler(this), dcacheHandler(this),
-      fetchEvent(this)
+      ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), fetchEvent(this)
 {
     _status = Idle;
 
-    ifetch_pkt = dcache_pkt = NULL;
-    drainEvent = NULL;
-    previousTick = 0;
     changeState(SimObject::Running);
     system->totalNumInsts = 0;
 }
@@ -155,7 +152,7 @@
 {
     assert(_status == Running || _status == Idle);
     _status = SwitchedOut;
-    numCycles += tickToCycles(curTick() - previousTick);
+    numCycles += curCycle() - previousCycle;
 
     // If we've been scheduled to resume but are then told to switch out,
     // we'll need to cancel it.
@@ -183,7 +180,7 @@
         _status = Idle;
     }
     assert(threadContexts.size() == 1);
-    previousTick = curTick();
+    previousCycle = curCycle();
 }
 
 
@@ -201,7 +198,7 @@
     _status = Running;
 
     // kick things off by initiating the fetch of the next instruction
-    schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
+    schedule(fetchEvent, clockEdge(delay));
 }
 
 
@@ -230,9 +227,8 @@
 {
     RequestPtr req = pkt->req;
     if (req->isMmappedIpr()) {
-        Tick delay;
-        delay = TheISA::handleIprRead(thread->getTC(), pkt);
-        new IprEvent(pkt, this, nextCycle(curTick() + delay));
+        Tick delay = TheISA::handleIprRead(thread->getTC(), pkt);
+        new IprEvent(pkt, this, clockEdge(delay));
         _status = DcacheWaitResponse;
         dcache_pkt = NULL;
     } else if (!dcachePort->sendTimingReq(pkt)) {
@@ -321,8 +317,8 @@
 {
     // fault may be NoFault in cases where a fault is suppressed,
     // for instance prefetches.
-    numCycles += tickToCycles(curTick() - previousTick);
-    previousTick = curTick();
+    numCycles += curCycle() - previousCycle;
+    previousCycle = curCycle();
 
     if (traceData) {
         // Since there was a fault, we shouldn't trace this instruction.
@@ -445,9 +441,8 @@
 {
     RequestPtr req = dcache_pkt->req;
     if (req->isMmappedIpr()) {
-        Tick delay;
-        delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
-        new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
+        Tick delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
+        new IprEvent(dcache_pkt, this, clockEdge(delay));
         _status = DcacheWaitResponse;
         dcache_pkt = NULL;
     } else if (!dcachePort->sendTimingReq(dcache_pkt)) {
@@ -566,8 +561,8 @@
         _status = IcacheWaitResponse;
         completeIfetch(NULL);
 
-        numCycles += tickToCycles(curTick() - previousTick);
-        previousTick = curTick();
+        numCycles += curCycle() - previousCycle;
+        previousCycle = curCycle();
     }
 }
 
@@ -599,8 +594,8 @@
         advanceInst(fault);
     }
 
-    numCycles += tickToCycles(curTick() - previousTick);
-    previousTick = curTick();
+    numCycles += curCycle() - previousCycle;
+    previousCycle = curCycle();
 }
 
 
@@ -646,8 +641,8 @@
 
     _status = Running;
 
-    numCycles += tickToCycles(curTick() - previousTick);
-    previousTick = curTick();
+    numCycles += curCycle() - previousCycle;
+    previousCycle = curCycle();
 
     if (getState() == SimObject::Draining) {
         if (pkt) {
@@ -721,7 +716,7 @@
     if (!pkt->wasNacked()) {
         DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
         // delay processing of returned data until next CPU clock edge
-        Tick next_tick = cpu->nextCycle(curTick());
+        Tick next_tick = cpu->nextCycle();
 
         if (next_tick == curTick())
             cpu->completeIfetch(pkt);
@@ -764,8 +759,8 @@
     assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
            pkt->req->getFlags().isSet(Request::NO_ACCESS));
 
-    numCycles += tickToCycles(curTick() - previousTick);
-    previousTick = curTick();
+    numCycles += curCycle() - previousCycle;
+    previousCycle = curCycle();
 
     if (pkt->senderState) {
         SplitFragmentSenderState * send_state =
@@ -840,7 +835,7 @@
 {
     if (!pkt->wasNacked()) {
         // delay processing of returned data until next CPU clock edge
-        Tick next_tick = cpu->nextCycle(curTick());
+        Tick next_tick = cpu->nextCycle();
 
         if (next_tick == curTick()) {
             cpu->completeDataAccess(pkt);
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/testers/memtest/memtest.cc
--- a/src/cpu/testers/memtest/memtest.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/testers/memtest/memtest.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -260,7 +260,7 @@
 MemTest::tick()
 {
     if (!tickEvent.scheduled())
-        schedule(tickEvent, curTick() + ticks(1));
+        schedule(tickEvent, clockEdge(1));
 
     if (++noResponseCycles >= 500000) {
         if (issueDmas) {
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/cpu/testers/networktest/networktest.cc
--- a/src/cpu/testers/networktest/networktest.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/cpu/testers/networktest/networktest.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -178,7 +178,7 @@
         exitSimLoop("Network Tester completed simCycles");
     else {
         if (!tickEvent.scheduled())
-            schedule(tickEvent, curTick() + ticks(1));
+            schedule(tickEvent, clockEdge(1));
     }
 }
 
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/dev/arm/pl111.cc
--- a/src/dev/arm/pl111.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/dev/arm/pl111.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -440,7 +440,7 @@
         schedule(intEvent, nextCycle());
 
     curAddr = 0;
-    startTime = curTick();
+    startTime = curCycle();
 
     maxAddr = static_cast<Addr>(length * bytesPerPixel);
 
@@ -475,12 +475,12 @@
 void
 Pl111::dmaDone()
 {
-    Tick maxFrameTime = lcdTiming2.cpl * height * clock;
+    Tick maxFrameTime = lcdTiming2.cpl * height;
 
     --dmaPendingNum;
 
     if (maxAddr == curAddr && !dmaPendingNum) {
-        if ((curTick() - startTime) > maxFrameTime) {
+        if ((curCycle() - startTime) > maxFrameTime) {
             warn("CLCD controller buffer underrun, took %d cycles when should"
                  " have taken %d\n", curTick() - startTime, maxFrameTime);
             lcdRis.underflow = 1;
@@ -498,11 +498,13 @@
         pic->seekp(0);
         bmp->write(pic);
 
-        DPRINTF(PL111, "-- schedule next dma read event at %d tick \n",
-                maxFrameTime + curTick());
-
+        // schedule the next read based on when the last frame started
+        // and the desired fps (i.e. maxFrameTime), we turn the
+        // argument into a relative number of cycles in the future by
+        // subtracting curCycle()
         if (lcdControl.lcden)
-            schedule(readEvent, nextCycle(startTime + maxFrameTime));
+            schedule(readEvent, clockEdge(startTime + maxFrameTime -
+                                          curCycle()));
     }
 
     if (dmaPendingNum > (maxOutstandingDma - waterMark))
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/dev/i8254xGBe.cc
--- a/src/dev/i8254xGBe.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/dev/i8254xGBe.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -2051,7 +2051,7 @@
 {
     if (!tickEvent.scheduled() && (rxTick || txTick || txFifoTick) &&
         getState() == SimObject::Running)
-        schedule(tickEvent, (curTick() / ticks(1)) * ticks(1) + ticks(1));
+        schedule(tickEvent, clockEdge(1));
 }
 
 unsigned int
@@ -2433,7 +2433,7 @@
 
 
     if (rxTick || txTick || txFifoTick)
-        schedule(tickEvent, curTick() + ticks(1));
+        schedule(tickEvent, curTick() + clockPeriod());
 }
 
 void
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/dev/ns_gige.cc
--- a/src/dev/ns_gige.cc	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/dev/ns_gige.cc	Fri Aug 03 12:55:33 2012 +0100
@@ -1147,7 +1147,7 @@
         }
 
         // Go to the next state machine clock tick.
-        rxKickTick = curTick() + ticks(1);
+        rxKickTick = curTick() + clockPeriod();
     }
 
     switch(rxDmaState) {
@@ -1594,7 +1594,7 @@
         }
 
         // Go to the next state machine clock tick.
-        txKickTick = curTick() + ticks(1);
+        txKickTick = curTick() + clockPeriod();
     }
 
     switch(txDmaState) {
@@ -2015,7 +2015,7 @@
 
     DPRINTF(Ethernet, "transfer complete: data in txFifo...schedule xmit\n");
 
-    reschedule(txEvent, curTick() + ticks(1), true);
+    reschedule(txEvent, curTick() + clockPeriod(), true);
 }
 
 bool
diff -r 6121b6dcad93 -r 10fd4f94efa4 src/sim/clocked_object.hh
--- a/src/sim/clocked_object.hh	Fri Aug 03 12:55:31 2012 +0100
+++ b/src/sim/clocked_object.hh	Fri Aug 03 12:55:33 2012 +0100
@@ -58,6 +58,12 @@
 
   private:
 
+    // The cycle as seen the last time we updated
+    mutable Tick cycle;
+
+    // The tick as seen the last time we updated
+    mutable Tick tick;
+
     /**
      * Prevent inadvertent use of the copy constructor and assignment
      * operator by making them private.
@@ -65,6 +71,28 @@
     ClockedObject(ClockedObject&);
     ClockedObject& operator=(ClockedObject&);
 
+    /**
+     *  Align cycle and tick to the next clock edge if not already done.
+     */
+    void update() const
+    {
+        if (tick == curTick())
+            return;
+
+        // see if we did something the last cycle
+        tick += clock;
+
+        if (tick == curTick()) {
+            // if so, increment the cycle count.
+            cycle += 1;
+            return;
+        }
+
+        // if not, we must manually recalculate everything
+        cycle = divCeil(curTick(), clock);
+        tick = cycle * clock;
+    }
+
   protected:
 
     // Clock period in ticks
@@ -74,7 +102,8 @@
      * Create a clocked object and set the clock based on the
      * parameters.
      */
-    ClockedObject(const ClockedObjectParams* p) : SimObject(p), clock(p->clock)
+    ClockedObject(const ClockedObjectParams* p) :
+        SimObject(p), cycle(0), tick(0), clock(p->clock)
     { }
 
     /**
@@ -85,33 +114,53 @@
   public:
 
     /**
+     * Determine the tick when a cycle begins, by default the current
+     * one, but the argument also enables the caller to determine a
+     * future cycle.
+     *
+     * @param cycles The number of cycles into the future
+     *
+     * @return The tick when the clock edge occurs
+     */
+    inline Tick clockEdge(int cycles = 0) const
+    {
+        // align tick to the next clock edge
+        update();
+
+        // figure out when this future cycle is
+        return tick + ticks(cycles);
+    }
+
+    /**
+     * Determine the current cycle, corresponding to a tick aligned to
+     * a clock edge.
+     *
+     * @return The current cycle
+     */
+    inline Tick curCycle() const
+    {
+        // align cycle to the next clock edge.
+        update();
+
+        return cycle;
+    }
+
+    /**
      * Based on the clock of the object, determine the tick when the
-     * next cycle begins, in other words, round the curTick() to the
-     * next tick that is a multiple of the clock.
+     * next cycle begins, in other words, return the next clock edge.
      *
      * @return The tick when the next cycle starts
      */
     Tick nextCycle() const
-    { return divCeil(curTick(), clock) * clock; }
-
-    /**
-     * Determine the next cycle starting from a given tick instead of
-     * curTick().
-     *
-     * @param begin_tick The tick to round to a clock edge
-     *
-     * @return The tick when the cycle after or on begin_tick starts
-     */
-    Tick nextCycle(Tick begin_tick) const
-    { return divCeil(begin_tick, clock) * clock; }
+    { return clockEdge(); }
 
     inline Tick frequency() const { return SimClock::Frequency / clock; }
 
-    inline Tick ticks(int numCycles) const { return clock * numCycles; }
+    inline Tick ticks(int cycles) const { return clock * cycles; }
 
-    inline Tick curCycle() const { return curTick() / clock; }
+    inline Tick clockPeriod() const { return clock; }
 
-    inline Tick tickToCycles(Tick val) const { return val / clock; }
+    inline Tick tickToCycle(Tick tick) const { return tick / clock; }
 
 };