diff --git a/configs/example/fs.py b/configs/example/fs.py
--- a/configs/example/fs.py
+++ b/configs/example/fs.py
@@ -136,6 +136,8 @@
     fatal("You cannot use fastmem in combination with caches!")
 
 for i in xrange(np):
+    if options.caches:
+        test_sys.cpu[i].cacheLineSize = options.cacheline_size
     if options.fastmem:
         test_sys.cpu[i].fastmem = True
     if options.checker:
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -223,17 +223,25 @@
         return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
       case MISCREG_CTR:
         {
+            CTR ctr = 0;
+            //b100 - gem5 format is ARMv7
+            ctr.format = 0x4;
+
             //all caches have the same line size in gem5
             //4 byte words in ARM
-            unsigned lineSizeWords =
-                tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
+            unsigned lineSizeWords = tc->getCpuPtr()->cacheLineSize / 4;
+
+            //if we don't have caches, it doesn't
+            //make sense to set the other values
+            if (!lineSizeWords)
+                return ctr;
+
             unsigned log2LineSizeWords = 0;
 
             while (lineSizeWords >>= 1) {
                 ++log2LineSizeWords;
             }
 
-            CTR ctr = 0;
             //log2 of minimun i-cache line size (words)
             ctr.iCacheLineSize = log2LineSizeWords;
             //b11 - gem5 uses pipt
@@ -244,8 +252,6 @@
             ctr.erg = log2LineSizeWords;
             //log2 of max writeback size (words)
             ctr.cwg = log2LineSizeWords;
-            //b100 - gem5 format is ARMv7
-            ctr.format = 0x4;
 
             return ctr;
         }
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -80,6 +80,7 @@
     system = Param.System(Parent.any, "system object")
     cpu_id = Param.Int(-1, "CPU identifier")
     numThreads = Param.Unsigned(1, "number of HW thread contexts")
+    cacheLineSize = Param.Int(0, "Cache Line Size")
 
     function_trace = Param.Bool(False, "Enable function trace")
     function_trace_start = Param.Tick(0, "Cycle to start function trace")
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -330,6 +330,8 @@
 
     Tick phase;
 
+    int cacheLineSize;
+
     /**
      * Serialize this object to the given output stream.
      * @param os The stream to serialize to.
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -120,7 +120,7 @@
       _dataMasterId(p->system->getMasterId(name() + ".data")),
       interrupts(p->interrupts),
       numThreads(p->numThreads), system(p->system),
-      phase(p->phase)
+      phase(p->phase), cacheLineSize(p->cacheLineSize)
 {
 //    currentTick = curTick();
 
diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/O3CPU.py
--- a/src/cpu/o3/O3CPU.py
+++ b/src/cpu/o3/O3CPU.py
@@ -142,6 +142,7 @@
             self.checker.itb = ArmTLB(size = self.itb.size)
             self.checker.dtb = ArmTLB(size = self.dtb.size)
             self.checker.cpu_id = self.cpu_id
+            self.checker.cacheLineSize = self.cacheLineSize
 
         else:
             print "ERROR: Checker only supported under ARM ISA!"
diff --git a/src/cpu/o3/checker_builder.cc b/src/cpu/o3/checker_builder.cc
--- a/src/cpu/o3/checker_builder.cc
+++ b/src/cpu/o3/checker_builder.cc
@@ -97,6 +97,7 @@
     params->progress_interval = 0;
     temp2++;
 
+    params->cacheLineSize = cacheLineSize;
     params->itb = itb;
     params->dtb = dtb;
     params->system = system;
diff --git a/tests/configs/realview-o3-checker.py b/tests/configs/realview-o3-checker.py
--- a/tests/configs/realview-o3-checker.py
+++ b/tests/configs/realview-o3-checker.py
@@ -82,6 +82,7 @@
 system = FSConfig.makeArmSystem('timing', "RealView_PBX", None, False)
 
 system.cpu = cpu
+system.cpu.cacheLineSize = 64
 #create the l1/l2 bus
 system.toL2Bus = CoherentBus()
 system.iocache = IOCache()
diff --git a/tests/configs/realview-o3-dual.py b/tests/configs/realview-o3-dual.py
--- a/tests/configs/realview-o3-dual.py
+++ b/tests/configs/realview-o3-dual.py
@@ -93,6 +93,7 @@
     # connect cpu level-1 caches to shared level-2 cache
     c.connectAllPorts(system.toL2Bus, system.membus)
     c.clock = '2GHz'
+    c.cacheLineSize = 64
 
 
 root = Root(full_system=True, system=system)
diff --git a/tests/configs/realview-o3.py b/tests/configs/realview-o3.py
--- a/tests/configs/realview-o3.py
+++ b/tests/configs/realview-o3.py
@@ -93,6 +93,7 @@
 # connect cpu level-1 caches to shared level-2 cache
 cpu.connectAllPorts(system.toL2Bus, system.membus)
 cpu.clock = '2GHz'
+cpu.cacheLineSize = 64
 
 root = Root(full_system=True, system=system)
 m5.ticks.setGlobalFrequency('1THz')