diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -223,17 +223,27 @@
         return 0x00001; // !Timer | !Virti | !M Profile | !TrustZone | ARMv4
       case MISCREG_CTR:
         {
+            CTR ctr = 0;
+            //b100 - gem5 format is ARMv7
+            ctr.format = 0x4;
+
+            SlavePort& cachePort =
+                tc->getCpuPtr()->getInstPort().getSlavePort();
+
+            // if we don't have caches, it doesn't
+            // make sense to set the other values
+            if (cachePort.name().find("icache") == std::string::npos)
+                return ctr;
+
             //all caches have the same line size in gem5
             //4 byte words in ARM
-            unsigned lineSizeWords =
-                tc->getCpuPtr()->getInstPort().peerBlockSize() / 4;
+            unsigned lineSizeWords = cachePort.deviceBlockSize() / 4;
             unsigned log2LineSizeWords = 0;
 
             while (lineSizeWords >>= 1) {
                 ++log2LineSizeWords;
             }
 
-            CTR ctr = 0;
             //log2 of minimun i-cache line size (words)
             ctr.iCacheLineSize = log2LineSizeWords;
             //b11 - gem5 uses pipt
@@ -244,8 +254,6 @@
             ctr.erg = log2LineSizeWords;
             //log2 of max writeback size (words)
             ctr.cwg = log2LineSizeWords;
-            //b100 - gem5 format is ARMv7
-            ctr.format = 0x4;
 
             return ctr;
         }