diff -r 6d347f9ff68d -r 5ac3ca2456dd src/cpu/checker/cpu.hh
--- a/src/cpu/checker/cpu.hh	Sun Aug 26 06:11:22 2012 +0100
+++ b/src/cpu/checker/cpu.hh	Sun Aug 26 06:12:37 2012 +0100
@@ -98,42 +98,40 @@
   public:
     virtual void init();
 
-  public:
     typedef CheckerCPUParams Params;
-    const Params *params() const
-    { return reinterpret_cast<const Params *>(_params); }
     CheckerCPU(Params *p);
     virtual ~CheckerCPU();
 
-    std::vector<Process*> workload;
-
     void setSystem(System *system);
 
-    System *systemPtr;
-
     void setIcachePort(CpuPort *icache_port);
 
-    CpuPort *icachePort;
-
     void setDcachePort(CpuPort *dcache_port);
 
-    CpuPort *dcachePort;
-
     CpuPort &getDataPort()
     {
-        panic("Not supported on checker!");
+        // the checker does not have ports on its own so return the
+        // data port of the actual CPU core
+        assert(dcachePort);
         return *dcachePort;
     }
 
     CpuPort &getInstPort()
     {
-        panic("Not supported on checker!");
+        // the checker does not have ports on its own so return the
+        // data port of the actual CPU core
+        assert(icachePort);
         return *icachePort;
     }
 
-  public:
-    // Primary thread being run.
-    SimpleThread *thread;
+  protected:
+
+    std::vector<Process*> workload;
+
+    System *systemPtr;
+
+    CpuPort *icachePort;
+    CpuPort *dcachePort;
 
     ThreadContext *tc;
 
@@ -167,6 +165,11 @@
 
     std::queue<int> miscRegIdxs;
 
+  public:
+
+    // Primary thread being run.
+    SimpleThread *thread;
+
     TheISA::TLB* getITBPtr() { return itb; }
     TheISA::TLB* getDTBPtr() { return dtb; }
 
diff -r 6d347f9ff68d -r 5ac3ca2456dd src/cpu/checker/cpu.cc
--- a/src/cpu/checker/cpu.cc	Sun Aug 26 06:11:22 2012 +0100
+++ b/src/cpu/checker/cpu.cc	Sun Aug 26 06:12:37 2012 +0100
@@ -65,7 +65,8 @@
 }
 
 CheckerCPU::CheckerCPU(Params *p)
-    : BaseCPU(p, true), thread(NULL), tc(NULL)
+    : BaseCPU(p, true), systemPtr(NULL), icachePort(NULL), dcachePort(NULL),
+      tc(NULL), thread(NULL)
 {
     memReq = NULL;
     curStaticInst = NULL;
@@ -83,9 +84,7 @@
     warnOnlyOnLoadError = p->warnOnlyOnLoadError;
     itb = p->itb;
     dtb = p->dtb;
-    systemPtr = NULL;
     workload = p->workload;
-    thread = NULL;
 
     updateOnError = true;
 }